TMS416800P-60DZ [TI]
2MX8 FAST PAGE DRAM, 60ns, PDSO28;
| 型号： | TMS416800P-60DZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX8 FAST PAGE DRAM, 60ns, PDSO28 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总25页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
Organization . . . 2097152 × 8
DZ PACKAGE
(TOP VIEW)
Single 5 V Power Supply (±10% Tolerance)
Performance Ranges:
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
SS
CC
ACCESS ACCESS ACCESS READ OR
TIME
2
DQ0
DQ1
DQ2
DQ3
W
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
TIME
TIME
WRITE
CYCLE
MIN
3
t
t
t
RAC
CAC
AA
MAX
MAX
MAX
4
’41x800-60
’41x800-70
’41x800-80
60 ns
70 ns
80 ns
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
5
6
7
RAS
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
†
8
A11
9
A10
A0
A1
A2
A3
A8
High-Impedance State Unlatched Output
10
11
12
13
14
A7
High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
A6
A5
A4
Operating Free-Air Temperature Range
V
V
SS
CC
0°C to 70°C
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC ) Technology by
Texas Instruments (TI )
PIN NOMENCLATURE
†
A0–A11
CAS
Address Inputs
Column-Address Strobe
DQ0–DQ7
OE
Data In/Data Out
Output Enable
Row-Address Strobe
5 V
description
RAS
The TMS41x800 series is a set of high-speed,
16777216-bit dynamic random-access memo-
ries (DRAMs) organized as 2097152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
V
V
CC
Ground
SS
W
Write Enable
†
A11 is NC (no internal connection) for TMS417800.
These devices feature maximum RAS access
timesof60ns, 70ns, and80ns. Alladdressesand
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The TMS416800 and TMS417800 are offered in
a 28-lead plastic surface-mount SOJ package
(DZ suffix). This package is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
operation
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by t
(RAS) low time.
, the maximum row-address strobe
RASP
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS)
is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the
devicestooperateatahigherdatabandwidththanconventionalpage-modepartsbecausedataretrievalbegins
as soon as the column address is valid rather than when CAS goes low. This performance improvement is
referred to as enhanced page mode. A valid column address can be presented immediately after row-address
hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained
aftert
max(accesstimefromCASlow)ift max(accesstimefromcolumnaddress)andt
(accesstime
CAC
AA
RAC
from RAS) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes
high, access time for the next cycle is determined by the later occurrence of t (access time from CAS
CPA
precharge) or t
.
CAC
address: A0–A11 (TMS416800) and A0–A10 (TMS417800)
Twenty-one address bits are required to decode one of 2097152 storage cell locations. For the TMS416800,
12 row-address bits are set up on A0 through A11 and latched on the chip by the RAS. Nine column-address
bits are set up on A0 through A8. For the TMS417800, 11 row-address bits are set up on inputs A0 through A10
and latched on the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be
stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and
latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ0–DQ7)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ0–DQ7)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t
(which begins with
CAC
the negative transition of CAS) as long as t
and t are satisfied.
RAC
AA
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
RAS-only refresh
TMS416800
A refresh operation must be performed at least once every 64 ms to retain data. The refresh operation can be
achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
TMS417800
A refresh operation must be performed at least once every 32 ms to retain data. The refresh operation can be
achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. The hidden refresh operation
is accomplished by holding CAS at V after a read or write operation and cycling RAS after a specified
IL
precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address
is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter t
) and then holding it low
CSR
after RAS falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling
CHR
RAS. The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V
(RAS-only or CBR) cycle.
level. The eight initialization cycles must include at least one refresh
CC
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
†
logic symbol for TMS416800
RAM 2M x 8
10
A0
A1
20D9/21D0
11
12
13
16
17
18
19
20
21
9
A2
A3
A4
0
A5
A
2 097 151
A6
A7
A8
20D17/21D8
20D18
A9
A10
A11
20D19
8
20D20
C20[ROW]
G23/[REFRESH ROW]
7
RAS
24[PWR DWN]
C21[COL]
G24
23
6
CAS
W
&
23C22
24,25EN
23,21D
G25
22
2
OE
DQ0
A,22D
26
A,Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
5
24
25
26
27
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
†
logic symbol for TMS417800
RAM 2M x 8
10
11
12
13
16
17
18
19
20
21
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
20D10/21D0
0
A
2 097 151
20D19/21D9
20D20
A10
C20[ROW]
G23/[REFRESH ROW]
7
RAS
24[PWR DWN]
C21[COL]
G24
23
6
CAS
W
&
23C22
24,25EN
23,21D
G25
22
2
OE
DQ0
A,22D
26
A,Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
5
24
25
26
27
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
functional block diagram
TMS416800
RAS CAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
256K Array
8
Column-
Address
Buffers
Data-
In
R
o
8
256K Array
A8
Reg.
8
w
I/O
8
Buffers
D
e
c
o
d
e
64
Data-
Out
Reg.
Row-
Address
Buffers
12
256K Array
DQ0–DQ7
A9, A10, A11
12
TMS417800
RAS CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
8
Column-
Address
Buffers
256K Array
256K Array
256K Array
256K Array
Data-
In
R
o
8
A9
Reg.
8
w
I/O
8
Buffers
D
e
c
o
d
e
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
256K Array
11
256K Array
DQ0–DQ7
A10
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS41x800
MIN NOM
UNIT
MAX
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416800
’416800-60
’416800-70
’416800-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
µA
I
CC
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
± 10
± 10
± 10
µA
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
80
70
60
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh current
(RAS-only refresh or
CBR)
‡§
‡¶
I
I
80
70
70
60
60
50
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
Average page current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
IL
IH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417800
’417800-60
’417800-70
’417800-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
µA
I
CC
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V
,
CC
CC
CAS high
O
± 10
± 10
± 10
µA
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
110
100
90
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CAS high (RAS
CC
Average refresh current
(RAS-only refresh or
CBR)
RAS cycling,
only),
RAS low after CAS low (CBR)
‡§
‡¶
I
I
110
70
100
60
90
50
mA
mA
CC3
V
= 5.5 V, = MIN,
t
CC
RAS low,
PC
CAS cycling
Average page current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
IL
IH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
†
C
C
C
C
C
Input capacitance, A0–A11
5
7
7
7
7
i(A)
Input capacitance, OE
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
†
A11 is NC (no internal connection) for TMS417800.
NOTE 3: = NOM supply voltage ±10%, and the bias on pins under test is 0 V.
V
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x800-60
’41x800-70
’41x800-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Access time from column address
30
15
35
60
15
35
18
40
70
18
40
20
45
80
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Access time from CAS
CAC
CPA
RAC
OEA
CLZ
OH
Access time from CAS precharge
Access time from RAS
Access time from OE
Delay time, CAS to output in the low-impedance state
Output data hold time from CAS
Output data hold time from OE
0
3
3
0
0
0
3
3
0
0
0
3
3
0
0
OHO
OFF
OEZ
Output buffer turn-off delay from CAS (see Note 5)
Output buffer turn-off delay from OE (see Note 5)
15
15
18
18
20
20
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
5.
t
and t are specified when the output is no longer driven.
OEZ
OFF
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x800-60
’41x800-70
’41x800-80
UNIT
MIN
110
110
155
40
MAX
MIN
130
130
181
45
MAX
MIN
150
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write
WC
Cycle time, read-write
RWC
PC
Cycle time, page-mode read or write (see Note 6)
Cycle time, page-mode read-write
Pulse duration, RAS active, page mode (see Note 7)
Pulse duration, RAS active, nonpage mode (see Note 7)
Pulse duration, CAS active (see Note 8)
Pulse duration, CAS precharge
85
96
105
PRWC
RASP
RAS
CAS
CP
60 100 000
70 100 000
80 100 000
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, RAS precharge
RP
Pulse duration, write command
WP
Setup time, column address
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data-in (see Note 9)
Setup time, read command
0
0
0
0
0
0
RCS
CWL
RWL
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
15
15
18
18
20
20
Setup time, write command before CAS active (early-write
only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
t
t
t
Setup time, CAS referenced to RAS (CBR refresh only)
Hold time, column address
5
10
10
10
0
5
15
15
10
0
5
15
15
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSR
CAH
DH
Hold time, data-in (see Note 9)
Hold time, row address
RAH
RCH
RRH
WCH
RHCP
OEH
ROH
Hold time, read command referenced to CAS (see Note 10)
Hold time, read command referenced to RAS (see Note 10)
Hold time, write command during CAS active (early-write only)
Hold time, RAS active from CAS precharge
Hold time, OE command
0
0
0
10
35
15
10
15
40
18
10
15
45
20
10
Hold time, RAS referenced to OE
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
6. To ensure t
7. In a read-write cycle, t
8. In a read-write cycle, t
min, t
should be ≥ to t
.
CP
PC
ASC
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
9. Referenced to the later of CAS or W in write operations
10. Either t or t must be satisfied for a read cycle.
RRH
RCH
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’41x800-60
’41x800-70
’41x800-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, column address to write command
(read-write operation only)
t
55
63
70
ns
AWD
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CAS referenced to RAS (CBR refresh only)
Delay time, CAS precharge to RAS
10
5
10
5
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHR
CRP
CSH
CWD
OED
RAD
RAL
Delay time, RAS active to CAS precharge
60
40
15
15
30
30
20
0
70
46
18
15
35
35
20
0
80
50
20
15
40
40
20
0
Delay time, CAS to write command (read-write operation only)
Delay time, OE to data in
Delay time, RAS to column address (see Note 11)
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 11)
30
45
35
52
40
60
CAL
RCD
RPC
RSH
RWD
CPW
Delay time, RAS precharge to CAS
Delay time, CAS active to RAS precharge
15
85
60
18
98
68
20
110
75
Delay time, RAS to write command (read-write operation only)
Delay time, CAS precharge to write command (read-write only)
’416800
’417800
64
32
30
64
32
30
64
32
30
t
Refresh time interval
ms
ns
REF
t
T
Transition time
3
3
3
NOTE 11: The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
5 V
828 Ω
218 Ω
Output Under Test
Output Under Test
295 Ω
C
= 100 pF
L
C
= 100 pF
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
L
Figure 1. Load Circuits for Timing Parameters
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
CP
t
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Row
Column
Don’t Care
Address
t
t
RRH
RCS
t
CAH
t
RCH
Don’t Care
Don’t Care
W
t
CAC
t
OFF
OH
t
AA
t
Valid Data Out
DQ0–DQ7
Hi-Z
See Note A
t
CLZ
t
OHO
t
RAC
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
t
CAL
RAS
t
RP
t
T
t
RSH
t
RCD
t
CAS
t
CRP
t
CSH
t
CAS
Address
W
ASR
t
CP
t
ASC
t
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
t
CWL
t
t
RAD
RWL
t
WCH
Don’t Care
Don’t Care
t
WCS
t
WP
t
DH
t
DS
Valid Data
Don’t Care
DQ0–DQ7
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CSH
t
t
CAS
ASR
t
CP
t
ASC
t
RAL
CAL
t
t
RAH
t
CAH
Row
Column
Don’t Care
Address
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WP
t
DS
t
DH
Don’t Care
Valid Data
Don’t Care
DQ0–DQ7
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 4. Write-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
t
CRP
RCD
t
CAS
t
ASR
t
CP
t
RAH
t
CAH
t
RAD
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWD
t
RWL
t
AWD
t
CWD
Don’t Care
Don’t Care
Don’t Care
W
DQ0–DQ7
OE
t
t
CAC
WP
t
DS
t
t
DH
AA
t
CLZ
Data
Out
Data
In
See Note A
t
RAC
t
t
OEH
OEZ
t
OHO
t
t
OED
OEA
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RHCP
t
PC
RAS
t
RCD
t
CRP
t
t
t
CSH
RSH
CP
t
CAS
CAS
Address
W
t
RAH
t
CAL
t
t
t
CAH
ASR
t
ASC
RAL
Row
Column
Column
Don’t Care
†
t
t
AA
RRH
t
RCH
t
RCS
†
t
CAC
t
RAD
†
t
CPA
t
CAC
t
AA
t
OFF
t
RAC
t
OH
t
CLZ
Valid
Out
Valid
Out
DQ0–DQ7
See Note A
t
t
OHO
OHO
t
t
OEZ
OEZ
t
OEA
t
OEA
Don’t Care
OE
†
Access time is t
-, t
CPA CAC
-, or t -dependent.
AA
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
PC
t
CSH
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
ASR
CAH
Address
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
CWL
t
t
RWL
WP
t
WCS
t
WCH
W
Don’t Care
Don’t Care
Don’t Care
t
DH
t
DS
Valid
In
Valid Data In
Don’t Care
DQ0–DQ7
OE
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 7. Enhanced-Page-Mode Early-Write-Cycle Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
PC
t
CSH
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
CAH
ASR
Address
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
t
CWL
t
RWL
WP
t
DS
W
Don’t Care
Don’t Care
Don’t Care
t
OEH
t
DH
Valid
In
Don’t Care
Valid Data In
OEH
Don’t Care
DQ0–DQ7
OE
t
t
OED
Don’t Care
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
RHCP
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
CAS
t
ASR
t
ASC
t
RAD
t
CAH
Column
Don’t Care
Row
Column
Address
t
RAH
t
CWL
t
CWD
t
t
AWD
RWD
CPW
t
RWL
t
t
WP
W
t
CPA
t
OEH
t
RCS
t
t
DH
AA
t
t
DS
†
RAC
Valid Out
t
CAC
Valid
In
Valid
In
DQ0–DQ7
t
CLZ
Valid Out
t
OED
t
OEZ
t
OEH
t
OEA
OE
t
OHO
†
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
t
ASR
t
RAH
Row
Don’t Care
Row
Address
W
Don’t Care
DQ0–DQ7
OE
Hi-Z
Don’t Care
Figure 10. RAS-Only Refresh-Cycle Timing
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
RPC
t
CHR
t
T
Don’t Care
Don’t Care
Don’t Care
W
Address
OE
Hi-Z
DQ0–DQ7
Figure 11. Automatic-CBR-Refresh-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
RP
Memory Cycle
t
RP
t
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
Address
t
RRH
t
RCS
Don’t Care
W
t
CAC
AA
t
t
OFF
t
RAC
Valid Data Out
DQ0–DQ7
OE
t
CLZ
t
OEZ
t
OEA
Figure 12. Hidden-Refresh-Cycle (Read) Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Don’t Care
Row
Col
Address
t
RRH
t
WCS
t
WP
W
t
WCH
t
DH
t
DS
Don’t Care
Valid Data
DQ0–DQ7
OE
Don’t Care
Figure 13. Hidden-Refresh-Cycle (Write) Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J28)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.730 (18,54)
0.720 (18,29)
28
15
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
14
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.380 (9,65)
0.360 (9,14)
0.007 (0,18)
M
0.050 (1,27)
0.008 (0,20) NOM
4040094-3/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416800 illustrated)
-SS
TI
Speed ( -60, - 70, -80)
Package Code
TMS416800 DZ
W
C
Y M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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