TMS416809-70DZ [TI]
2MX8 EDO DRAM, 70ns, PDSO28, 0.400 INCH, PLASTIC, SOJ-28;
| 型号： | TMS416809-70DZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX8 EDO DRAM, 70ns, PDSO28, 0.400 INCH, PLASTIC, SOJ-28 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
DZ PACKAGE
(TOP VIEW)
Organization . . . 2097152 × 8
Single 5 V Power Supply (±10% Tolerance)
Performance Ranges:
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
SS
ACCESS ACCESS ACCESS
TIME TIME TIME
EDO
CYCLE
CC
2
DQ0
DQ1
DQ2
DQ3
W
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
t
t
t
t
RAC
CAC
AA
HPC
3
MAX
60 ns
70 ns
80 ns
MAX
15 ns
18 ns
20 ns
MAX
30 ns
35 ns
40 ns
MIN
4
’41x809-60
’41x809-70
’41x809-80
25 ns
30 ns
35 ns
5
6
7
Extended Data Out (EDO) Operation
CAS-Before-RAS (CBR) Refresh
High-Impedance State Unlatched Output
High-Reliability Plastic 28-Lead (DZ Suffix)
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
RAS
†
8
A11
9
A10
A0
A1
A2
A3
A8
10
11
12
13
14
A7
A6
A5
A4
Operating Free-Air Temperature Range
0°C to 70°C
V
V
SS
CC
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC ) Technology by
Texas Instruments (TI )
†
A11 is NC (no internal connection) for TMS417809.
PIN NOMENCLATURE
AVAILABLE OPTIONS
A0–A11
DQ0–DQ7
CAS
NC
OE
Address Inputs
POWER
SUPPLY
REFRESH
CYCLES
Data In/Data Out
Column-Address Strobe
No Internal Connection
Output Enable
DEVICE
TMS416809
TMS417809
5 V
5 V
4096 in 64 ms
2048 in 32 ms
RAS
Row-Address Strobe
5 V Supply
Ground
‡
V
description
CC
V
SS
W
Write Enable
The TMS41x809 series is a set of high-speed,
16777216-bit dynamic random-access memo-
ries (DRAMs) organized as 2097152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
‡
See Available Options Table.
These devices feature maximum RAS access
timesof60ns, 70ns, and80ns. Alladdressesand
data-in lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
The TMS41x809 is offered in a 28-lead plastic
surface-mount SOJ package (DZ suffix). This
package is characterized for operation from 0°C
to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
operation
extended data out
Extended data out (EDO) allows data output rates up to 40 MHz for 60-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold, and for
address multiplex is eliminated. The maximum number of columns that can be accessed is determined by
t
, the maximum RAS low time.
RASP
Extended data out does not place the data in/data out pins (DQs) into the high-impedance state with the rising
edgeofCAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes
the next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO
operation benefit.
address: A0–A11 (TMS416809) and A0–A10 (TMS417809)
Twenty-one address bits are required to decode 1 of 2097152 storage-cell locations. For the TMS416809,
12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (RAS).
Nine column-address bits are set up on A0 through A8. For the TMS417809, 11 row-address bits are set up on
inputs A0 through A10 and latched onto the chip by RAS. Ten column-address bits are set up on A0 through
A9. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar to a chip enable
because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffers and latching the address bits into the column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for t
(hold time, OE
CHO
fromCAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of t
(precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
OEP
transitions on OE until CAS falls again (see Figure 7).
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 8).
data in/data out (DQ0–DQ7)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE descriptions.
RAS-only refresh
TMS416809
Arefreshoperationmustbeperformedatleastonceevery64mstoretaindata. Thiscanbeachievedbystrobing
each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
TMS417809
Arefreshoperationmustbeperformedatleastonceevery32mstoretaindata. Thiscanbeachievedbystrobing
each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a
IL
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter t
) and holding it low after
CSR
RAS falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
CHR
The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or CBR) cycle.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
†
logic symbol (TMS416809)
RAM 2M x 8
10
A0
A1
20D9/21D0
11
12
13
16
17
18
19
20
21
9
A2
A3
A4
0
A5
A
2 097 151
A6
A7
A8
20D17/21D8
20D18
A9
A10
A11
20D19
8
20D20
C20[ROW]
G23/[REFRESH ROW]
7
RAS
24[PWR DWN]
C21[COL]
G24
23
6
CAS
W
&
23C22
24,25EN
23,21D
G25
22
2
OE
DQ0
A,22D
26
A,Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
5
24
25
26
27
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
†
logic symbol (TMS417809)
RAM 2M x 8
10
11
12
13
16
17
18
19
20
21
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
20D10/21D0
0
A
2 097 151
20D19/21D9
20D20
C20[ROW]
G23/[REFRESH ROW]
7
RAS
24[PWR DWN]
C21[COL]
G24
23
6
CAS
W
&
23C22
24,25EN
23,21D
G25
22
2
OE
DQ0
A,22D
26
A,Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
5
24
25
26
27
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
functional block diagram (TMS416809)
RAS
CAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
256K Array
8
Column-
Address
Buffers
Data-
In
Reg.
R
o
8
256K Array
A8
8
w
I/O
Buffers
8
D
e
c
o
d
e
64
Data-
Out
Reg.
Row-
Address
Buffers
12
256K Array
DQ0–DQ7
A9–
A11
12
functional block diagram (TMS417809)
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
8
Column-
Address
Buffers
256K Array
256K Array
256K Array
256K Array
Data-
In
Reg.
R
o
8
A9
8
w
I/O
Buffers
D
e
c
o
d
e
8
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
DQ0–DQ7
A10
256K Array
11
256K Array
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416809
’416809-60
’416809-70
’416809-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
µA
I
CC
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
± 10
± 10
± 10
µA
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
80
70
60
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh current
(RAS-only refresh or
CBR)
‡§
‡¶
I
I
80
90
70
80
60
70
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
HPC
CAS cycling
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
IL
IH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417809
’417809-60
’417809-70
’417809-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
110
0.4
± 10
± 10
100
0.4
± 10
± 10
90
OL
OL
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
Input current (leakage)
µA
µA
mA
I
CC
Output current
(leakage)
V
= 5.5 V,
CC
CAS high
V
= 0 V to V ,
CC
O
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
IH
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After 1 memory cycle,
RAS and CAS high
Average refresh
current (RAS-only
refresh or CBR)
V
= 5.5 V,
Minimum cycle,
CAS high (RAS only),
RAS low after CAS low (CBR)
CC
RAS cycling,
‡§
‡¶
I
I
110
90
100
80
90
70
mA
mA
CC3
V
= 5.5 V, = MIN,
t
CC
RAS low,
HPC
CAS cycling
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
IL
IH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
†
C
C
C
C
C
Input capacitance, A0–A11
5
7
7
7
7
i(A)
Input capacitance, OE
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
†
A11 is NC (no internal connection) for TMS417809.
NOTE 3: = NOM supply voltage ±10%, and the bias on pins under test is 0 V.
V
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x809-60
’41x809-70
’41x809-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Access time from column address
30
15
35
60
15
35
18
40
70
18
40
20
45
80
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Access time from CAS
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CAS precharge
Access time from RAS
Access time from OE
Delay time, CAS to output in low impedance
Output buffer turn off delay from RAS (see Note 5)
Output buffer turn off delay from CAS (see Note 5)
Output buffer turn off delay from OE (see Note 5)
Output buffer turn off delay from W (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
15
15
15
15
18
18
18
18
20
20
20
20
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
5. Maximum t
, t
, t
, and t
are specified when the output is no longer driven.
WEZ
REZ CEZ OEZ
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x809-60
’41x809-70
’41x809-80
UNIT
MIN
25
80
50
10
3
MAX
MIN
30
90
55
10
3
MAX
MIN
35
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
OCH
CP
100
60
Delay time, RAS active to CAS precharge
Hold time, OE from CAS
10
Hold time, output from CAS
3
Pulse duration, CAS active
10 10000
12 10000
15 10000
Pulse duration, W active (output disable only)
Setup time, OE before CAS
5
10
5
5
10
5
5
10
5
Pulse duration, CAS precharge
Precharge time, OE
5
5
5
OEP
NOTE 4: With ac parameters, it is assumed that t = 5 ns.
T
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x809-60
’41x809-70
’41x809-80
UNIT
MIN
110
150
MAX
MIN
130
175
MAX
MIN
150
200
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, read-write
RWC
RASP
RAS
RP
Pulse duration, RAS active, fast page mode (see Note 6)
Pulse duration, RAS active, non-page mode (see Note 6)
Pulse duration, RAS precharge
60 100 000
70 100 000
80 100 000
60
40
10
0
10 000
70
50
10
0
10 000
80
60
10
0
10 000
Pulse duration, write command
WP
Setup time, column address
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data in (see Note 7)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
WCS
CSR
CAH
DH
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
Setup time, write command before CAS active (early-write only)
Setup time, CAS referenced to RAS (CBR refresh only)
Hold time, column address
10
10
0
12
12
0
15
15
0
5
5
5
10
10
10
0
12
12
10
0
15
15
10
0
Hold time, data in (see Note 7)
Hold time, row address
RAH
RCH
RRH
WCH
ROH
Hold time, read command referenced to CAS (see Note 8)
Hold time, read command referenced to RAS (see Note 8)
Hold time, write command during CAS active (early-write only)
Hold time, RAS referenced to OE
0
0
0
10
10
12
10
15
10
Hold time, CAS referenced to RAS (CBR refresh
only)
t
15
15
20
ns
CHR
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, OE command
15
55
0
18
63
0
20
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OEH
AWD
CRP
CWD
OED
RAD
RAL
Delay time, column address to write command (read-write only)
Delay time, CAS precharge to RAS
Delay time, CAS to write command (read-write only)
Delay time, OE to data in
40
15
15
30
20
20
0
46
18
15
35
25
20
0
50
20
15
40
30
20
0
Delay time, RAS to column address
30
45
35
52
40
60
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 9)
Delay time, RAS precharge to CAS
CAL
RCD
RPC
RSH
RWD
Delay time, CAS active to RAS precharge
Delay time, RAS to write command (read-write only)
10
85
12
98
15
110
’416809
64
32
30
64
32
30
64
32
30
t
Refresh time interval
’417809
ms
ns
REF
t
T
Transition time
2
2
2
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
6. In a read-write cycle, t
and t must be observed.
RWD
RWL
7. Referenced to the later of CAS or W in write operations
8. Either t or t must be satisfied for a read cycle.
RRH
RCH
9. The maximum value is specified only to ensure access time.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
1.31 V
5 V
218 Ω
828 Ω
295 Ω
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
L
Figure 1. Load Circuits for Timing Parameters
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
t
CP
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Don’t Care
Row
Column
Address
t
RCS
t
t
RRH
RCH
t
CAH
Don’t Care
Don’t Care
W
t
CAC
t
CEZ
REZ
t
t
AA
Valid Data Out
Hi-Z
DQ0–DQ7
See Note A
CLZ
t
t
WEZ
t
RAC
t
WPE
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CSH
t
t
CAS
ASR
t
CP
t
ASC
t
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
Address
t
CWL
t
RAD
t
RWL
t
WCH
t
WCS
Don’t Care
Don’t Care
W
t
WP
t
DH
t
DS
Don’t Care
Valid Data
DQ0–DQ7
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CAS
t
CSH
t
CAS
ASR
t
t
CP
ASC
t
RAL
t
RAH
t
CAH
Don’t Care
Row
Column
Address
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WP
t
DS
t
DH
DQ0–DQ7
Valid Data
Don’t Care
Don’t Care
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 4. Write-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
CRP
RCD
t
CAS
t
ASR
t
t
CP
RAH
t
CAH
t
RAD
t
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWL
t
RWD
t
WP
t
AWD
t
CWD
Don’t Care
W
DQ0–DQ7
OE
t
CAC
t
DS
t
AA
t
DH
t
CLZ
Data
Out
Data
In
Don’t Care
Hi-Z
See Note A
t
RAC
t
OEZ
t
OEA
t
OEH
t
OED
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
t
RP
t
T
t
t
RSH
RCD
t
CSH
t
t
CRP
HPC
t
CAS
t
CP
CAS
t
RAH
t
ASC
t
CAL
t
ASR
t
RAL
t
CAH
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
RCH
t
OEA
OE
t
RCS
t
CAC
t
RRH
t
DOH
W
t
CAC
t
AA
t
t
CEZ
AA
t
CPA
t
RAC
t
REZ
t
CLZ
DATA #1
DATA #2
DATA #3
DQ0–DQ7
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is t - or t -dependent.
CPA AA
Figure 6. Extended-Data-Out Read Cycle
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
CSH
t
HPC
t
CP
t
t
CAS
RSH
t
ASR
t
RAH
t
CAL
t
ASC
t
RAL
t
CAH
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
OCH
t
t
CHO
OEP
t
OEP
OE
t
OEA
t
RRH
t
RCS
t
RCH
t
OEA
t
CAC
W
t
DOH
t
CLZ
t
OEZ
t
CAC
t
t
CEZ
CPA
t
AA
t
REZ
t
OEZ
t
RAC
t
AA
DATA #1
DATA #1
DATA #2
DATA #3
DQ0–DQ7
Figure 7. Extended-Data-Out Read-Cycle With OE Control
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
CAS
t
RP
t
CSH
t
CRP
t
t
HPC
RSH
t
CP
t
CAS
t
ASR
t
RAH
t
CAH
t
CAL
t
ASC
t
RAL
Column #3
Row
Column #1
Column #2
Address
OE
t
RAD
t
OEA
t
CAC
t
RCS
t
CAC
t
WPE
t
RCH
t
RRH
W
t
DOH
t
CAC
t
WEZ
t
CPA
t
CEZ
t
AA
t
CPA
t
AA
t
AA
t
CLZ
t
REZ
t
RAC
DATA #1
DATA #2
DATA #3
DQ0–DQ7
Figure 8. Extended-Data-Out Read-Cycle With W Control
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
HPC
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASC
t
RAH
t
CP
t
t
CAH
RAL
t
t
CAL
ASR
Row
Column
Column
Don’t Care
Address
t
CWL
t
CWL
t
RAD
t
t
RWL
WP
Don’t Care
Don’t Care
Don’t Care
W
t
DH
t
DS
Data In
Data In
DQ0–DQ7
OE
Don’t Care
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 9. EDO-Early-Write-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
HPC
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASC
t
RAH
t
CP
t
t
CAH
RAL
t
t
CAL
ASR
Row
Column
Column
Don’t Care
Address
t
t
CWL
t
CWL
t
RAD
t
RWL
WP
Don’t Care
Don’t Care
Don’t Care
W
t
t
OEH
DH
t
DS
DQ0–DQ7
OE
Data In
Data In
Don’t Care
t
t
OEH
OED
Don’t Care
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 10. EDO-Write-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
t
CAS
ASR
t
ASC
t
CAL
t
CAH
t
RAL
t
RAD
Row
Column 1
Column 2
Don’t Care
Address
t
RAH
t
CWL
t
CWD
t
AWD
RWD
t
RWL
t
WP
t
W
t
RCS
t
CPA
t
OEH
t
AA
t
DH
t
t
Valid Out 2
RAC
t
DS
See Note A
t
CAC
Valid
In 1
Valid
In 2
DQ0–DQ7
Valid
Out 1
t
CLZ
t
OED
OEA
t
OEH
t
OEZ
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 11. EDO Read-Write-Cycle Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
CAS
t
RAH
t
ASR
Address
Row
Don’t Care
Row
Don’t Care
W
DQ0–DQ7
OE
Hi Z
Don’t Care
Figure 12. RAS-Only Refresh-Cycle Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
Don’t Care
Don’t Care
Don’t Care
Hi-Z
W
Address
OE
DQ0–DQ7
Figure 13. Automatic-CBR-Refresh-Cycle Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
t
RP
t
RP
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Row
Col
Address
t
RRH
t
RCS
Don’t Care
W
t
CAC
t
t
REZ
t
AA
t
CEZ
RAC
Valid Data Out
DQ0–DQ7
OE
t
CLZ
t
OEZ
t
OEA
Figure 14. Hidden-Refresh Cycle (Read)
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Memory Cycle
Refresh Cycle
t
RAS
Refresh Cycle
t
RP
t
RAS
t
RP
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Address
Row
Col
Don’t Care
t
RRH
t
WCS
t
WP
Don’t Care
W
t
DS
t
WCH
t
DH
Valid Data
Don’t Care
DQ0–DQ7
OE
Don’t Care
Figure 15. Hidden-Refresh Cycle (Write) Timing
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416809, TMS417809
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS885A – DECEMBER 1995 – REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J28)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.730 (18,54)
0.720 (18,29)
28
15
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
14
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.380 (9,65)
0.360 (9,14)
0.007 (0,18)
M
0.050 (1,27)
0.008 (0,20) NOM
4040094-3/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416809 illustrated)
TI
-SS
Speed ( -60, - 70, -80)
TMS416809 DZ
Package Code
W
C
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明