TMS320C5532_技术文档

TMS320C5535

TMS320C5534, TMS320C5533, TMS320C5532

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SPRS737–AUGUST 2011

TMS320C5535, 'C5534, 'C5533, 'C5532 Fixed-Point Digital Signal Processors

Check for Samples: TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532

1 Fixed-Point Digital Signal Processor

1.1 Features

1

– Four Inter-IC Sound (I²S Bus™) for Data

Transport

– Device USB Port With Integrated 2.0

• CORE:

– High-Performance, Low-Power, TMS320C55x

Fixed-Point Digital Signal Processor

High-Speed PHY that Supports:

•

20-, 10-ns Instruction Cycle Time

50-, 100-MHz Clock Rate

One/Two Instruction(s) Executed per

Cycle

•

USB 2.0 Full- and High-Speed Device

– LCD Bridge With Asynchronous Interface

– 10-Bit 4-Input Successive Approximation

(SAR) ADC

– IEEE-1149.1 (JTAG™)

•

Dual Multipliers [Up to 200 Million

Multiply-Accumulates per Second

(MMACS)]

Boundary-Scan-Compatible

– Up to 20 General-Purpose I/O (GPIO) Pins

(Multiplexed With Other Device Functions)

• POWER:

•

Two Arithmetic/Logic Units (ALUs)

Three Internal Data/Operand Read Buses

and Two Internal Data/Operand Write

Buses

– Four Core Isolated Power Supply Domains:

Analog, RTC, CPU and Peripherals, and USB

– Three I/O Isolated Power Supply Domains:

•

Software-Compatible With C55x Devices

Industrial Temperature Devices Available

RTC I/O, USB PHY, and DV_DDIO

– 320K Bytes Zero-Wait State On-Chip RAM,

– Three integrated LDOs (DSP_LDO,

ANA_LDO, and USB_LDO) to power the

isolated domains: DSP Core, Analog, and

USB Core, respectively

Composed of:

•

64K Bytes of Dual-Access RAM (DARAM),

8 Blocks of 4K x 16-Bit

256K Bytes of Single-Access RAM

(SARAM), 32 Blocks of 4K x 16-Bit

– 1.05-V Core (50 MHz), 1.8-V, 2.5-V, 2.75-V, or

3.3-V I/Os

– 128K Bytes of Zero Wait-State On-Chip ROM

– 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.75-V, or

3.3-V I/Os

• CLOCK:

(4 Blocks of 16K x 16-Bit)

– Tightly-Coupled FFT Hardware Accelerator

• PERIPHERAL:

– Real-Time Clock (RTC) With Crystal Input,

With Separate Clock Domain, Separate

Power Supply

– Direct Memory Access (DMA) Controller

•

Four DMA With 4 Channels Each

(16-Channels Total)

– Low-Power S/W Programmable

– Three 32-Bit General-Purpose Timers

One Selectable as a Watchdog and/or GP

Phase-Locked Loop (PLL) Clock Generator

• BOOTLOADER:

•

– Two Embedded Multimedia Card/Secure

Digital (eMMC/SD) Interfaces

– Universal Asynchronous

Receiver/Transmitter (UART)

– Serial-Port Interface (SPI) With Four

Chip-Selects

– Master/Slave Inter-Integrated Circuit (I²C

Bus™)

– On-Chip ROM Bootloader (RBL) to Boot

From SPI EEPROM, SPI Serial Flash or I2C

EEPROM eMMC/SD/SDHC, UART, and USB

• PACKAGE:

– 144-Terminal Pb-Free Plastic BGA (Ball Grid

Array) (ZHH Suffix)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS320C5535

TMS320C5534, TMS320C5533, TMS320C5532

SPRS737–AUGUST 2011

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1.2 Applications

•

Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones)

Echo Cancellation Headphones

Portable Medical Devices

Voice Applications

Industrial Controls

Fingerprint Biometrics

Software-defined Radio

1.3 Description

These devices are members of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product

family and are designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP

architecture achieves high performance and low power through increased parallelism and total focus on

power savings. The CPU supports an internal bus structure that is composed of one program bus, one

32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses

dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data

reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each

with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention.

Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the

CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit

multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by

an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize

parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data

Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction

Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the

Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and

Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids

pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions, along with the 10-bit SAR ADC on the TMS320C5535,

provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces.

Serial media is supported through two Secure Digital (SD) peripherals, four Inter-IC Sound (I2S Bus™)

modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave

interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

Additional peripherals include: a high-speed Universal Serial Bus (USB 2.0) device mode only (not

available on TMS320C5532), a real-time clock (RTC), three general-purpose timers with one configurable

as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the TMS320C5535 includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled

FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes three integrated LDOs to power different sections of the device:

•

ANA_LDO (All devices)—Provides 1.3 V to the DSP PLL (V_{DDA_PLL}), SAR, and power management

circuits (V_{DDA_ANA}).

2

Fixed-Point Digital Signal Processor

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•

DSP_LDO (TMS320C5535 and 'C5534)—Provides 1.3 V or 1.05 V to the DSP core (CV_DD), selectable

on-the-fly by software as long as operating frequency ranges are observed. For lowest power

operation, the programmer can shut down the internal DSP_LDO, cutting power to the DSP core

(CV_DD) while an external supply provides power to the RTC (CV_DDRTCand DV_DDRTC). The RTC alarm

interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP

core.

When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the

50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for

proper operation after reset.

•

USB_LDO (TMS320C5535, 'C5534, and 'C5533)—Provides 1.3 V to the USB core digital

(USB_V_DD1P3) and PHY circuits (USB_V_DDA1P3).

These devices are supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™

Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the

industry’s largest third-party network. Code Composer Studio IDE features code generation tools including

a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and

evaluation modules. The devices are also supported by the C55x DSP Library which features more than

50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip

support libraries.

Fixed-Point Digital Signal Processor

3

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the devices.

Figure 1-1. Functional Block Diagram

DSP System

JTAG Interface

C55x DSP CPU

Input

Clock(s)

Power

Management

PLL/Clock

Generator

64 KB DARAM

128 KB ROM

Multiplexing

TMS320C5532

TMS320C5533

TMS320C5534

No SARAM

64 KB SARAM

192 KB SARAM

256 KB SARAM

TMS320C5535

FFT Hardware

Accelerator

Switched Central Resource (SCR)

Peripherals

TMS320C5535

TMS320C5534

TMS320C5533

Connectivity

Program/Data

Storage

Application

Specific

Interconnect

Display

USB 2.0

PHY (HS)

[DEVICE]

Not Applicable

TMS320C5532

eMMC/SD

SDHC

(x2)

DMA

(x4)

10-Bit

SAR

ADC

LCD

Bridge

System

Serial Interfaces

I²S

I²C

(x4)

GP Timer

(x2)

GP Timer

or WD

RTC

ANA_LDO

USB_LDO

DSP_LDO

TMS320C5532

TMS320C5533

SPI

UART

TMS320C5535/C5534

4

Fixed-Point Digital Signal Processor

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1

Fixed-Point Digital Signal Processor ............... 1

6.1 Parameter Information .............................. 83

6.2

Recommended Clock and Control Signal Transition

1.1 Features .............................................. 1

1.2 Applications .......................................... 2

1.3 Description ........................................... 2

Behavior ............................................ 83

6.3 Power Supplies ..................................... 84

6.4

External Clock Input From RTC_XI, CLKIN, and

USB_MXI Pins ...................................... 87

1.4 Functional Block Diagram ............................ 4

6.5 Clock PLLs ......................................... 91

2

Device Overview ........................................ 6

6.6

Direct Memory Access (DMA) Controller ........... 93

2.1 Device Differences ................................... 6

2.2 Device Characteristics ............................... 6

2.3 C55x CPU .......................................... 13

2.4 Memory Map Summary ............................. 20

Device Pins ............................................. 24

3.1 Pin Assignments .................................... 24

6.7 Reset ............................................... 94

6.8 Wake-up Events, Interrupts, and XF ............... 98

6.9 Secure Digital (SD) ................................ 100

6.10 Real-Time Clock (RTC) ........................... 105

3

4

6.11 Inter-Integrated Circuit (I2C) ...................... 108

6.12 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 112

3.2 Terminal Functions ................................. 28

Device Configuration ................................. 55

6.13 Inter-IC Sound (I2S) ............................... 114

6.14 Liquid Crystal Display Controller (LCDC) — C5535

Only ............................................... 121

4.1 System Registers ................................... 55

4.2 Power Considerations .............................. 56

4.3 Clock Considerations ............................... 64

4.4 Boot Sequence ..................................... 66

4.5 Configurations at Reset ............................ 69

4.6 Configurations After Reset ......................... 70

4.7 Multiplexed Pin Configurations ..................... 72

4.8 Debugging Considerations ......................... 76

Device Operating Conditions ....................... 78

6.15 10-Bit SAR ADC — C5535 Only .................. 130

6.16 Serial Port Interface (SPI) ......................... 131

6.17 Universal Serial Bus (USB) 2.0 Controller — Does

Not Apply to C5532 ............................... 134

6.18 General-Purpose Timers .......................... 141

6.19 General-Purpose Input/Output .................... 143

6.20 IEEE 1149.1 JTAG ................................ 147

Device and Documentation Support ............. 149

7.1 Device Support .................................... 149

5

6

7

8

5.1

Absolute Maximum Ratings Over Operating Case

Temperature Range (Unless Otherwise Noted) .... 78

7.2 Community Resources ............................ 150

Mechanical Packaging and Orderable

Information ............................................ 151

8.1 Thermal Data for ZHH ............................. 151

8.2 Packaging Information ............................ 151

5.2 Recommended Operating Conditions .............. 79

5.3

Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted) ............ 80

Peripheral Information and Electrical

Specifications .......................................... 83

Contents

5

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2 Device Overview

2.1 Device Differences

Table 2-1 lists the important differences between all four devices, including on-chip RAM, peripheral

support, and LDOs.

Table 2-1. Device Differences

Device

Digital Core Supply

Voltage (CV_DD

On-chip

DARAM

On-chip

SARAM

USB

LCD

Interface

Tightly-

Coupled

FFT

SAR

ADC

LDO

)

1.05 V 1.3 V

Maximum CPU Speed

TMS320C5535A05

TMS320C5535A10

50 MHz

-

ANA, DSP,

and USB

64 KB

256 KB

192 KB

64 KB

0 KB

x⁽¹⁾

x

-

x

-

100 MHz

TMS320C5534A05

TMS320C5534A10

50 MHz

-

ANA, DSP,

and USB

(2)

x

-

100 MHz

TMS320C5533A05

TMS320C5533A10

50 MHz

-

ANA and

USB

-

100 MHz

TMS320C5532A05

TMS320C5532A10

50 MHz

-

ANA only

100 MHz

(1) x — Supported

(2) - — Not supported

2.2 Device Characteristics

Table 2-2 through Table 2-5 provide an overview of all four devices. The tables show significant features

of each device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the

package type with pin count. For more detailed information on the actual device part number and

maximum device operating frequency, see Section 7.1.2, Device and Development-Support Tool

Nomenclature.

Table 2-2. Characteristics of the 'C5535 Processor

HARDWARE FEATURES

TMS320C5535A05, 'C5535A10

Peripherals

Not all peripheral pins are

available at the same time

(for more detail, see the

Device Configurations

section).

Four DMA controllers each with four channels,

for a total of 16 channels

DMA

2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer and/or a

Watchdog

Timers

UART

1 (with RTS/CTS flow control)

1 with 4 chip selects

SPI

I²C

1 (Master/Slave)

I²S

4 (Two Channel, Full Duplex Communication)

High- and Full-Speed Device

USB 2.0 (Device only)

2 SD, 256-byte read/write buffer, max 50-MHz clock and

signaling for DMA transfers

SD

LCD Bridge

1 (8-bit or 16-bit asynchronous parallel bus)

1 (10-bit, 4-input, 16-μs conversion time)

ADC (Successive Approximation [SAR])

Real-Time Clock (RTC)

FFT Hardware Accelerator

1 (Crystal Input, Separate Clock Domain and Power Supply)

1 (Supports 8 to 1024-point 16-bit real and complex FFT)

6

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Table 2-2. Characteristics of the 'C5535 Processor (continued)

HARDWARE FEATURES

General-Purpose Input/Output Port (GPIO)

Size (Bytes)

TMS320C5535A05, 'C5535A10

Up to 20 pins (with 1 Additional General-Purpose Output (XF)

and 4 Special-Purpose Outputs for Use With SAR)

320 KB RAM, 128KB ROM

•

64 KB On-Chip Dual-Access RAM (DARAM)

256 KB On-Chip Single-Access RAM (SARAM)

128 KB On-Chip Single-Access ROM (SAROM)

On-Chip Memory

Organization

JTAGID Register

(Value is: 0x1B8F E02F)

JTAG BSDL_ID

CPU Frequency

see Figure 6-38

1.05-V Core

50 MHz

100 MHz (TMS320C5535A10 only)

20 ns

MHz

1.3-V Core

1.05-V Core

Cycle Time

ns

1.3-V Core

10 ns (TMS320C5535A10 only)

1.05 V – 50 MHz

Core (V)

Voltage

LDOs

1.3 V – 100 MHz (TMS320C5535A10 only)

1.8 V, 2.5 V, 2.75 V, 3.3 V

I/O (V)

DSP_LDO

1.3 V or 1.05 V, 250 mA max current for DSP CPU (CV_DD

1.3 V, 4 mA max current to supply power to PLL (V_{DDA_PLL}),

SAR, and power management circuits (V_{DDA_ANA}

1.3 V, 25 mA max current to supply power to USB core digital

)

ANA_LDO

USB_LDO

)

(USB_V_DD1P3) and PHY circuits (USB_V_DDA1P3

)

Active @ Room Temp 25°C, 75% DMAC +

25% ADD

0.15 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Power Characterization

Active @ Room Temp 25°C, 75% DMAC +

25% NOP

0.14 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM and SARAM in Active

Mode)

0.26 mW @ 1.05 V

0.44 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Retention and

SARAM in Active Mode)

0.23 mW @ 1.05 V

0.40 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Active Mode and

SARAM in Retention)

0.15 mW @ 1.05 V

0.28 mW @ 1.3 V

PLL Options

Software Programmable Multiplier

12 x 12 mm

x4 to x4099 multiplier

144-Pin BGA (ZHH)

BGA Package

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽¹⁾

PD

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Device Overview

7

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Table 2-3. Characteristics of the 'C5534 Processor

HARDWARE FEATURES

TMS320C5534A05, 'C5534A10

Peripherals

Not all peripheral pins are

available at the same time

(for more detail, see the

Device Configurations

section).

Four DMA controllers each with four channels, for a total of 16

channels

DMA

2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer and/or a

Watchdog

Timers

UART

1 (with RTS/CTS flow control)

1 with 4 chip selects

SPI

I²C

1 (Master/Slave)

I²S

4 (Two Channel, Full Duplex Communication)

High- and Full-Speed Device

USB 2.0 (Device only)

2 SD, 256-byte read/write buffer, max 50-MHz clock and

signaling for DMA transfers

SD

Real-Time Clock (RTC)

1 (Crystal Input, Separate Clock Domain and Power Supply)

Up to 20 pins (with 1 Additional General-Purpose Output (XF))

256 KB RAM, 128KB ROM

General-Purpose Input/Output Port (GPIO)

Size (Bytes)

•

64 KB On-Chip Dual-Access RAM (DARAM)

192 KB On-Chip Single-Access RAM (SARAM)

128 KB On-Chip Single-Access ROM (SAROM)

On-Chip Memory

Organization

•

JTAGID Register

(Value is: 0x1B8F E02F)

JTAG BSDL_ID

CPU Frequency

see Figure 6-38

1.05-V Core

50 MHz

100 MHz (TMS320C5534A10 only)

20 ns

MHz

1.3-V Core

1.05-V Core

Cycle Time

ns

1.3-V Core

10 ns (TMS320C5534A10 only)

1.05 V – 50 MHz

Core (V)

Voltage

LDOs

1.3 V – 100 MHz (TMS320C5534A10 only)

1.8 V, 2.5 V, 2.75 V, 3.3 V

I/O (V)

DSP_LDO

1.3 V or 1.05 V, 250 mA max current for DSP CPU (CV_DD)

1.3 V, 4 mA max current to supply power to PLL (V_{DDA_PLL}

and power management circuits (V_{DDA_ANA}

)

ANA_LDO

USB_LDO

)

1.3 V, 25 mA max current to supply power to USB core digital

(USB_V_DD1P3) and PHY circuits (USB_V_DDA1P3

)

Active @ Room Temp 25°C, 75% DMAC +

25% ADD

0.15 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Power Characterization

Active @ Room Temp 25°C, 75% DMAC +

25% NOP

0.14 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM and SARAM in Active

Mode)

0.26 mW @ 1.05 V

0.44 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Retention and

SARAM in Active Mode)

0.23 mW @ 1.05 V

0.40 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Active Mode and

SARAM in Retention)

0.15 mW @ 1.05 V

0.28 mW @ 1.3 V

PLL Options

Software Programmable Multiplier

12 x 12 mm

x4 to x4099 multiplier

144-Pin BGA (ZHH)

BGA Package

8

Device Overview

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Table 2-3. Characteristics of the 'C5534 Processor (continued)

HARDWARE FEATURES

TMS320C5534A05, 'C5534A10

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽¹⁾

PD

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Device Overview

9

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Table 2-4. Characteristics of the 'C5533 Processor

HARDWARE FEATURES

TMS320C5533A05, 'C5533A10

Peripherals

Not all peripheral pins are

available at the same time

(for more detail, see the

Device Configurations

section).

Four DMA controllers each with four channels,

for a total of 16 channels

DMA

2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer and/or a

Watchdog

Timers

UART

1 (with RTS/CTS flow control)

1 with 4 chip selects

SPI

I²C

1 (Master/Slave)

I²S

4 (Two Channel, Full Duplex Communication)

High- and Full-Speed Device

USB 2.0 (Device only)

2 SD, 256-byte read/write buffer, max 50-MHz clock and

signaling for DMA transfers

SD

Real-Time Clock (RTC)

1 (Crystal Input, Separate Clock Domain and Power Supply)

Up to 20 pins (with 1 Additional General-Purpose Output (XF))

128 KB RAM, 128KB ROM

General-Purpose Input/Output Port (GPIO)

Size (Bytes)

•

64 KB On-Chip Dual-Access RAM (DARAM)

64 KB On-Chip Single-Access RAM (SARAM)

128 KB On-Chip Single-Access ROM (SAROM)

On-Chip Memory

Organization

•

JTAGID Register

(Value is: 0x1B8F E02F)

JTAG BSDL_ID

CPU Frequency

see Figure 6-38

1.05-V Core

50 MHz

100 MHz (TMS320C5533A10 only)

20 ns

MHz

1.3-V Core

1.05-V Core

Cycle Time

ns

1.3-V Core

10 ns (TMS320C5533A10 only)

1.05 V – 50 MHz

Core (V)

Voltage

LDOs

1.3 V – 100 MHz (TMS320C5533A10 only)

1.8 V, 2.5 V, 2.75 V, 3.3 V

I/O (V)

1.3 V, 4 mA max current to supply power to PLL (V_{DDA_PLL}

)

ANA_LDO

and power management circuits (V_{DDA_ANA}

)

1.3 V, 25 mA max current to supply power to USB core digital

USB_LDO

(USB_V_DD1P3) and PHY circuits (USB_V_DDA1P3

)

Active @ Room Temp 25°C, 75% DMAC +

25% ADD

0.15 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Power Characterization

Active @ Room Temp 25°C, 75% DMAC +

25% NOP

0.14 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM and SARAM in Active

Mode)

0.26 mW @ 1.05 V

0.44 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Retention and

SARAM in Active Mode)

0.23 mW @ 1.05 V

0.40 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Active Mode and

SARAM in Retention)

0.15 mW @ 1.05 V

0.28 mW @ 1.3 V

PLL Options

Software Programmable Multiplier

12 x 12 mm

x4 to x4099 multiplier

144-Pin BGA (ZHH)

BGA Package

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Table 2-4. Characteristics of the 'C5533 Processor (continued)

HARDWARE FEATURES

TMS320C5533A05, 'C5533A10

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽¹⁾

PD

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Table 2-5. Characteristics of the C5532 Processor

HARDWARE FEATURES

TMS320C5532A05, 'C5532A10

Peripherals

Not all peripheral pins are

available at the same time

(for more detail, see the

Device Configurations

section).

Four DMA controllers each with four channels,

for a total of 16 channels

DMA

2 32-Bit General-Purpose (GP) Timers

1 Additional Timer Configurable as a 32-Bit GP Timer and/or a

Watchdog

Timers

UART

SPI

1 (with RTS/CTS flow control)

1 with 4 chip selects

I²C

1 (Master/Slave)

I²S

4 (Two Channel, Full Duplex Communication)

2 SD, 256-byte read/write buffer, max 50-MHz clock and

signaling for DMA transfers

SD

Real-Time Clock (RTC)

1 (Crystal Input, Separate Clock Domain and Power Supply)

Up to 20 pins (with 1 Additional General-Purpose Output (XF))

64 KB RAM, 128KB ROM

General-Purpose Input/Output Port (GPIO)

Size (Bytes)

On-Chip Memory

•

64 KB On-Chip Dual-Access RAM (DARAM)

128 KB On-Chip Single-Access ROM (SAROM)

Organization

•

JTAGID Register

(Value is: 0x1B8F E02F)

JTAG BSDL_ID

CPU Frequency

see Figure 6-38

1.05-V Core

50 MHz

100 MHz (TMS320C5532A10 only)

20 ns

MHz

1.3-V Core

1.05-V Core

Cycle Time

Voltage

ns

1.3-V Core

10 ns (TMS320C5532A10 only)

1.05 V – 50 MHz

Core (V)

1.3 V – 100 MHz (TMS320C5532A10 only)

1.8 V, 2.5 V, 2.75 V, 3.3 V

I/O (V)

1.3 V, 4 mA max current for PLL (V_{DDA_PLL}) power

LDO

ANA_LDO

management circuits (V_{DDA_ANA}

)

Active @ Room Temp 25°C, 75% DMAC +

25% ADD

0.15 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Power Characterization

Active @ Room Temp 25°C, 75% DMAC +

25% NOP

0.14 mW/MHz @ 1.05 V, 50 MHz

0.22 mW/MHz @ 1.3 V, 100 MHz

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM and SARAM in Active

Mode)

0.26 mW @ 1.05 V

0.44 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Retention and

SARAM in Active Mode)

0.23 mW @ 1.05 V

0.40 mW @ 1.3 V

Standby (Master Clock Disabled) @ Room

Temp 25°C (DARAM in Active Mode and

SARAM in Retention)

0.15 mW @ 1.05 V

0.28 mW @ 1.3 V

PLL Options

Software Programmable Multiplier

12 x 12 mm

x4 to x4099 multiplier

144-Pin BGA (ZHH)

BGA Package

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽¹⁾

PD

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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2.3 C55x CPU

The TMS320C5535, 'C5534, 'C5533, and 'C5532 fixed-point digital signal processors (DSP) are based on

the C55x CPU 3.3 generation processor core. The C55x DSP architecture achieves high performance and

low power through increased parallelism and total focus on power savings. The CPU supports an internal

bus structure that is composed of one program bus, three data read buses (one 32-bit data read bus and

two 16-bit data read buses), two 16-bit data write buses, and additional buses dedicated to peripheral and

DMA activity. These buses provide the ability to perform up to four data reads and two data writes in a

single cycle. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and

independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit

multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional

16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel

activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit

(DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The

Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a

128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit

decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.

Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.

For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide

(literature number SWPU073).

2.3.1 On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h − 00FFFFh and is composed of eight blocks of

4K words each (see Table 2-6). Each DARAM block can perform two accesses per cycle (two reads, two

writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.

Table 2-6. DARAM Blocks

CPU

DMA CONTROLLER

BYTE ADDRESS RANGE

MEMORY BLOCK

BYTE ADDRESS RANGE

000000h – 001FFFh

002000h – 003FFFh

004000h – 005FFFh

006000h – 007FFFh

008000h – 009FFFh

00A000h – 00BFFFh

00C000h – 00DFFFh

00E000h – 00FFFFh

0001 0000h – 0001 1FFFh

0001 2000h – 0001 3FFFh

0001 4000h – 0001 5FFFh

0001 6000h – 0001 7FFFh

0001 8000h – 0001 9FFFh

0001 A000h – 0001 BFFFh

0001 C000h – 0001 DFFFh

0001 E000h – 0001 FFFFh

DARAM 0⁽¹⁾

DARAM 1

DARAM 2

DARAM 3

DARAM 4

DARAM 5

DARAM 6

DARAM 7

(1) The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 2-1, Memory Map

Summary.

2.3.2 On-Chip Read-Only Memory (ROM)

The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is

composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be

mapped by software to the internal ROM.

The standard device includes a Bootloader program resident in the ROM.

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When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range

FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status

register is set through software, the on-chip ROM is disabled and not present in the memory map, and

byte address range FE0000h – FFFFFFh is unmapped. A hardware reset always clears the MPNMC bit,

so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect

the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is

a one cycle per word access memory.

2.3.3 On-Chip Single-Access RAM (SARAM)

Section 2.3.3.1 explains the SARAM blocks for the C5535. Section 2.3.3.2 explains the SARAM blocks for

the C5534. Section 2.3.3.3 explains the SARAM blocks for the C5533. The C5532 has no SARAM blocks.

2.3.3.1 SARAM for C5535

The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of

4K words each (see Table 2-7). Each SARAM block can perform one access per cycle (one read or one

write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed

by the USB and LCD DMA buses.

Table 2-7. SARAM Blocks for C5535

CPU

DMA/USB CONTROLLER

BYTE ADDRESS RANGE

MEMORY BLOCK

BYTE ADDRESS RANGE

010000h − 011FFFh

012000h − 013FFFh

014000h − 015FFFh

016000h − 017FFFh

018000h − 019FFFh

01A000h − 01BFFFh

01C000h − 01DFFFh

01E000h − 01FFFFh

020000h − 021FFFh

022000h − 023FFFh

024000h − 025FFFh

026000h − 027FFFh

028000h − 029FFFh

02A000h − 02BFFFh

02C000h − 02DFFFh

02E000h − 02FFFFh

030000h − 031FFFh

032000h − 033FFFh

034000h − 035FFFh

036000h − 037FFFh

038000h − 039FFFh

03A000h − 03BFFFh

03C000h − 03DFFFh

03E000h − 03FFFFh

040000h – 041FFFh

042000h – 043FFFh

044000h – 045FFFh

046000h – 047FFFh

0009 0000h – 0009 1FFFh

0009 2000h – 0009 3FFFh

0009 4000h – 0009 5FFFh

0009 6000h – 0009 7FFFh

0009 8000h – 0009 9FFFh

0009 A000h – 0009 BFFFh

0009 C000h – 0009 DFFFh

0009 E000h – 0009 FFFFh

000A 0000h – 000A 1FFFh

000A 2000h – 000A 3FFFh

000A 4000h – 000A 5FFFh

000A 6000h – 000A 7FFFh

000A 8000h – 000A 9FFFh

000A A000h – 000A BFFFh

000A C000h – 000A DFFFh

000A E000h – 000A FFFFh

000B 0000h – 000B 1FFFh

000B 2000h – 000B 3FFFh

000B 4000h – 000B 5FFFh

000B 6000h – 000B 7FFFh

000B 8000h – 000B 9FFFh

000B A000h – 000B BFFFh

000B C000h – 000B DFFFh

000B E000h – 000B FFFFh

000C 0000h – 000C 1FFFh

000C 2000h – 000C 3FFFh

000C 4000h – 000C 5FFFh

000C 6000h – 000C 7FFFh

SARAM 0

SARAM 1

SARAM 2

SARAM 3

SARAM 4

SARAM 5

SARAM 6

SARAM 7

SARAM 8

SARAM 9

SARAM 10

SARAM 11

SARAM 12

SARAM 13

SARAM 14

SARAM 15

SARAM 16

SARAM 17

SARAM 18

SARAM 19

SARAM 20

SARAM 21

SARAM 22

SARAM 23

SARAM 24

SARAM 25

SARAM 26

SARAM 27

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Table 2-7. SARAM Blocks for C5535 (continued)

CPU

DMA/USB CONTROLLER

BYTE ADDRESS RANGE

MEMORY BLOCK

BYTE ADDRESS RANGE

048000h – 049FFFh

04A000h – 04BFFFh

04C000h – 04DFFFh

04E000h – 04FFFFh

000C 8000h – 000C 9FFFh

000C A000h – 000C BFFFh

000C C000h – 000C DFFFh

000C E000h – 000C FFFFh

SARAM 28

SARAM 29

SARAM 30

SARAM 31⁽¹⁾

(1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot

process is complete, this memory space can be used.

2.3.3.2 SARAM for C5534

The SARAM is located at the byte address range 010000h – 03FFFFh and is composed of 24 blocks of

4K words each (see Table 2-8). Each SARAM block can perform one access per cycle (one read or one

write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed

by the USB bus.

Table 2-8. SARAM Blocks for C5534

CPU

DMA/USB CONTROLLER

BYTE ADDRESS RANGE

MEMORY BLOCK

BYTE ADDRESS RANGE

010000h − 011FFFh

012000h − 013FFFh

014000h − 015FFFh

016000h − 017FFFh

018000h − 019FFFh

01A000h − 01BFFFh

01C000h − 01DFFFh

01E000h − 01FFFFh

020000h − 021FFFh

022000h − 023FFFh

024000h − 025FFFh

026000h − 027FFFh

028000h − 029FFFh

02A000h − 02BFFFh

02C000h − 02DFFFh

02E000h − 02FFFFh

030000h − 031FFFh

032000h − 033FFFh

034000h − 035FFFh

036000h − 037FFFh

038000h − 039FFFh

03A000h − 03BFFFh

03C000h − 03DFFFh

03E000h − 03FFFFh

0009 0000h – 0009 1FFFh

0009 2000h – 0009 3FFFh

0009 4000h – 0009 5FFFh

0009 6000h – 0009 7FFFh

0009 8000h – 0009 9FFFh

0009 A000h – 0009 BFFFh

0009 C000h – 0009 DFFFh

0009 E000h – 0009 FFFFh

000A 0000h – 000A 1FFFh

000A 2000h – 000A 3FFFh

000A 4000h – 000A 5FFFh

000A 6000h – 000A 7FFFh

000A 8000h – 000A 9FFFh

000A A000h – 000A BFFFh

000A C000h – 000A DFFFh

000A E000h – 000A FFFFh

000B 0000h – 000B 1FFFh

000B 2000h – 000B 3FFFh

000B 4000h – 000B 5FFFh

000B 6000h – 000B 7FFFh

000B 8000h – 000B 9FFFh

000B A000h – 000B BFFFh

000B C000h – 000B DFFFh

000B E000h – 000B FFFFh

SARAM 0

SARAM 1

SARAM 2

SARAM 3

SARAM 4

SARAM 5

SARAM 6

SARAM 7

SARAM 8

SARAM 9

SARAM 10

SARAM 11

SARAM 12

SARAM 13

SARAM 14

SARAM 15

SARAM 16

SARAM 17

SARAM 18

SARAM 19

SARAM 20

SARAM 21

SARAM 22

SARAM 23

2.3.3.3 SARAM for C5533

The SARAM is located at the byte address range 010000h – 01FFFFh and is composed of 8 blocks of 4K

words each (see Table 2-9). Each SARAM block can perform one access per cycle (one read or one

write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed

by the USB bus.

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Table 2-9. SARAM Blocks for C5533

CPU

DMA/USB CONTROLLER

BYTE ADDRESS RANGE

MEMORY BLOCK

BYTE ADDRESS RANGE

010000h − 011FFFh

012000h − 013FFFh

014000h − 015FFFh

016000h − 017FFFh

018000h − 019FFFh

01A000h − 01BFFFh

01C000h − 01DFFFh

01E000h − 01FFFFh

0009 0000h – 0009 1FFFh

0009 2000h – 0009 3FFFh

0009 4000h – 0009 5FFFh

0009 6000h – 0009 7FFFh

0009 8000h – 0009 9FFFh

0009 A000h – 0009 BFFFh

0009 C000h – 0009 DFFFh

0009 E000h – 0009 FFFFh

SARAM 0

SARAM 1

SARAM 2

SARAM 3

SARAM 4

SARAM 5

SARAM 6

SARAM 7

2.3.4 I/O Memory

Each device DSP includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals

and system registers used for idle control, status monitoring and system configuration. I/O space is

separate from program/memory space and is accessed with separate instruction opcodes or via the

DMA's.

Table 2-10, Table 2-11, and Table 2-12 list the memory-mapped registers of each device. Note that not all

addresses in the 64K byte I/O space are used; these addresses should be treated as RESERVED and not

accessed by the CPU nor DMA. For the expanded tables of each peripheral, see Section 6, Peripheral

Information and Electrical Specifications of this document.

Some DMA controllers have access to the I/O-Space memory-mapped registers of the following

peripherals registers: I2C, UART, I2S, SD, USB, and SAR ADC.

Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is

not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the

Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).

Table 2-10. Peripheral I/O-Space Control Registers for C5535

WORD ADDRESS

0x0000 – 0x0004

PERIPHERAL

Idle Control

Reserved

DMA0

0x0005 – 0x000D through 0x0803 – 0x0BFF

0x0C00 – 0x0C7F

0x0C80 – 0x0CFF

0x0D00 – 0x0D7F

0x0D80 – 0x0DFF

0x0E00 – 0x0E7F

Reserved

DMA1

Reserved

DMA2

0x0E80 – 0x0EFF

0x0F00 – 0x0F7F

Reserved

DMA3

0x0F80 – 0x17FF

Reserved

Timer0

0x1800 – 0x181F

0x1820 – 0x183F

Reserved

Timer1

0x1840 – 0x185F

0x1860 – 0x187F

Reserved

Timer2

0x1880 – 0x189F

0x1900 – 0x197F

RTC

0x1980 – 0x19FF

Reserved

I2C

0x1A00 – 0x1A6C

0x1A6D – 0x1AFF

Reserved

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Table 2-10. Peripheral I/O-Space Control Registers for C5535 (continued)

WORD ADDRESS

0x1B00 – 0x1B1F

PERIPHERAL

UART

0x1B80 – 0x1BFF

0x1C00 – 0x1CFF

0x1D00 – 0x1FFF through 0x2600 – 0x27FF

0x2800 – 0x2840

Reserved

System Control

Reserved

I2S0

0x2900 – 0x2940

I2S1

0x2A00 – 0x2A40

I2S2

0x2B00 – 0x2B40

I2S3

0x2C41 – 0x2DFF

0x2E00 – 0x2E40

Reserved

LCD

0x2E41 – 0x2FFF

Reserved

0x3000 – 0x300F

SPI

0x3010 – 0x39FF

Reserved

0x3A00 – 0x3A1F

SD0

0x3A20 – 0x3AFF

0x3B00 – 0x3B1F

Reserved

SD1

0x3B2F – 0x6FFF

0x7000 – 0x70FF

Reserved

SAR and Analog Control Registers

0x7100 – 0x7FFF

Reserved

USB

0x8000 – 0xFFFF

Table 2-11. Peripheral I/O-Space Control Registers for C5534 and C5533

WORD ADDRESS

0x0000 – 0x0004

PERIPHERAL

Idle Control

Reserved

DMA0

0x0005 – 0x000D through 0x0803 – 0x0BFF

0x0C00 – 0x0C7F

0x0C80 – 0x0CFF

Reserved

DMA1

0x0D00 – 0x0D7F

0x0D80 – 0x0DFF

Reserved

DMA2

0x0E00 – 0x0E7F

0x0E80 – 0x0EFF

Reserved

DMA3

0x0F00 – 0x0F7F

0x0F80 – 0x0FFF

Reserved

Timer0

0x1000 – 0x10DD

0x10EE – 0x10FF through 0x1300 – 0x17FF

0x1800 – 0x181F

0x1820 – 0x183F

Reserved

Timer1

0x1840 – 0x185F

0x1860 – 0x187F

Reserved

Timer2

0x1880 – 0x189F

0x1900 – 0x197F

RTC

0x1980 – 0x19FF

Reserved

I2C

0x1A00 – 0x1A6C

0x1A6D – 0x1AFF

Reserved

UART

0x1B00 – 0x1B1F

0x1B80 – 0x1BFF

Reserved

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Table 2-11. Peripheral I/O-Space Control Registers for C5534 and

C5533 (continued)

WORD ADDRESS

PERIPHERAL

System Control

Reserved

I2S0

0x1C00 – 0x1CFF

0x1D00 – 0x1FFF through 0x2600 – 0x27FF

0x2800 – 0x2840

0x2900 – 0x2940

I2S1

0x2A00 – 0x2A40

I2S2

0x2B00 – 0x2B40

I2S3

0x2C41 – 0x2FFF

0x3000 – 0x300F

Reserved

SPI

0x3010 – 0x39FF

Reserved

SD0

0x3A00 – 0x3A1F

0x3A20 – 0x3AFF

0x3B00 – 0x3B1F

Reserved

SD1

0x3B2F – 0x7FFF

0x8000 – 0xFFFF

Reserved

USB

Table 2-12. Peripheral I/O-Space Control Registers for C5532

WORD ADDRESS

0x0000 – 0x0004

PERIPHERAL

Idle Control

Reserved

DMA0

0x0005 – 0x000D through 0x0803 – 0x0BFF

0x0C00 – 0x0C7F

0x0C80 – 0x0CFF

Reserved

DMA1

0x0D00 – 0x0D7F

0x0D80 – 0x0DFF

Reserved

DMA2

0x0E00 – 0x0E7F

0x0E80 – 0x0EFF

Reserved

DMA3

0x0F00 – 0x0F7F

0x0F80 – 0x0FFF

Reserved

Timer0

0x1000 – 0x10DD

0x10EE – 0x10FF through 0x1300 – 0x17FF

0x1800 – 0x181F

0x1820 – 0x183F

Reserved

Timer1

0x1840 – 0x185F

0x1860 – 0x187F

Reserved

Timer2

0x1880 – 0x189F

0x1900 – 0x197F

RTC

0x1980 – 0x19FF

Reserved

I2C

0x1A00 – 0x1A6C

0x1A6D – 0x1AFF

Reserved

UART

0x1B00 – 0x1B1F

0x1B80 – 0x1BFF

Reserved

System Control

Reserved

I2S0

0x1C00 – 0x1CFF

0x1D00 – 0x1FFF through 0x2600 – 0x27FF

0x2800 – 0x2840

0x2900 – 0x2940

I2S1

0x2A00 – 0x2A40

I2S2

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Table 2-12. Peripheral I/O-Space Control Registers for C5532 (continued)

WORD ADDRESS

0x2B00 – 0x2B40

PERIPHERAL

I2S3

0x2C41 – 0x2DFF through 0x2E41 - 0x2FFF

0x3000 – 0x300F

Reserved

SPI

0x3010 – 0x39FF

Reserved

SD0

0x3A00 – 0x3A1F

0x3A20 – 0x3AFF

Reserved

SD1

0x3B00 – 0x3B1F

0x3B2F – 0xFFFF

Reserved

Device Overview

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2.4 Memory Map Summary

The on-chip, dual-access RAM allows two accesses to a given block during the same cycle. There are 8

blocks of 8K bytes of dual-access RAM. The on-chip, single-access RAM allows one access to a given

block per cycle. In addition, there are 32 blocks of 8K bytes of single-access RAM.

The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the

four DMA controllers, LCD, and USB's CDMA (see Figure 2-1).

CPU BYTE

DMA/USB/LCD

ADDRESS^(A)BYTE ADDRESS^(A)

MEMORY BLOCKS

MMR (Reserved)^(B)

BLOCK SIZE

000000h

0000C0h

0001 0000h

0001 00C0h

DARAM^(C)

SARAM

64K Minus 192 Bytes

256K Bytes

010000h

050000h

0009 0000h

0100 0000h

Reserved

FE0000h

FFFFFFh

050E 0000h

050F FFFFh

Unmapped (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

ROM

(if MPNMC=0)

Reserved

(if MPNMC=1)

A. Address shown represents the first byte address in each block.

B. The first 192 bytes are reserved for memory-mapped registers (MMRs).

C. The USB and LCD controllers do not have access to DARAM.

Figure 2-1. C5535 Memory Map Summary

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CPU BYTE

DMA/USB

ADDRESS^(A)BYTE ADDRESS^(A)

MEMORY BLOCKS

BLOCK SIZE

000000h

0000C0h

0001 0000h

0001 00C0h

MMR (Reserved)^(B)

DARAM^(C)

64K Minus 192 Bytes

192K Bytes

010000h

040000h

0009 0000h

000C 0000h

SARAM

Reserved

050E 0000h

050F FFFFh

FE0000h

FFFFFFh

Unmapped (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

ROM

(if MPNMC=0)

Reserved

(if MPNMC=1)

A. Address shown represents the first byte address in each block.

B. The first 192 bytes are reserved for memory-mapped registers (MMRs).

C. The USB controller does not have access to DARAM.

Figure 2-2. C5534 Memory Map Summary

Device Overview

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CPU BYTE

DMA/USB

ADDRESS^(A)BYTE ADDRESS^(A)

MEMORY BLOCKS

MMR (Reserved)^(B)

BLOCK SIZE

000000h

0000C0h

0001 0000h

0001 00C0h

DARAM^(C)

SARAM

64K Minus 192 Bytes

64K Bytes

010000h

020000h

0009 0000h

000A 0000h

Reserved

FE0000h

FFFFFFh

050E 0000h

050F FFFFh

Unmapped (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

ROM

(if MPNMC=0)

Reserved

(if MPNMC=1)

A. Address shown represents the first byte address in each block.

B. The first 192 bytes are reserved for memory-mapped registers (MMRs).

C. The USB controller does not have access to DARAM.

Figure 2-3. C5533 Memory Map Summary

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CPU BYTE

DMA

ADDRESS^(A)BYTE ADDRESS^(A)

MEMORY BLOCKS

BLOCK SIZE

000000h

0000C0h

0001 0000h

0001 00C0h

MMR (Reserved)^(B)

64K Minus 192 Bytes

DARAM

010000h

0009 0000h

Reserved

FE0000h

FFFFFFh

050E 0000h

050F FFFFh

Unmapped (if MPNMC=1)

128K Bytes ROM (if MPNMC=0)

ROM

(if MPNMC=0)

Reserved

(if MPNMC=1)

A. Address shown represents the first byte address in each block.

B. The first 192 bytes are reserved for memory-mapped registers (MMRs).

Figure 2-4. C5532 Memory Map Summary

Device Overview

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3 Device Pins

3.1 Pin Assignments

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the

smallest possible package. Pin multiplexing is controlled using software programmable register settings.

For more information on pin muxing, see Section 4.7, Multiplexed Pin Configurations of this document.

3.1.1 Pin Map (Bottom View)

Figure 3-1 shows the bottom view of the package pin assignments.

SD0_D1/

I2S0_RX/

GP[3]

SD0_D3/

GP[5]

SD1_D1/

I2S1_RX/

GP[9]

SD0_D2/

GP[4]

SD0_CMD/

I2S0_FS/

GP[1]

SD1_D3/

GP[11]

SD1_D0/

I2S1_DX/

GP[8]

SD1_CLK/

I2S1_CLK/

GP[6]

SD0_CLK/

I2S0_CLK/

GP[0]

SD1_CMD/

I2S1_FS/

GP[7]

SD1_D2/

GP[10]

SD0_D0/

I2S0_DX/

GP[2]

USB_MXI

USB_MXO

DSP_LDO_

EN

INT0

DV

DDRTC

LDOI

INT1

LDOI

DSP_LDOO

Figure 3-1. C5535 Pin Map

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I2S2_CLK/

GP[18]/

SPI_CLK

SD0_D1/

I2S0_RX/

GP[3]

SD0_D3/

GP[5]

I2S2_RX/

GP[20]/

SPI_RX

SD1_D1/

I2S1_RX/

GP[9]

I2S2_DX/

GP[27]/

SPI_TX

UART_CTS/ UART_RXD/

GP[30]/

I2S3_RX

V

TRST

SS

GP[14]

GP[16]

TCK

V

P

N

M

L

GP[17]

SS

GP[29]/

I2S3_FS

I2S2_FS/

GP[19]/

SPI_CS0

UART_RTS/

GP[28]/

I2S3_CLK

SD0_D2/

GP[4]

SPI_CS2

GP[13]

TMS

GP[15]

DV

CV

DD

SPI_RX

TDO

DV

DDIO

SD0_CMD/

I2S0_FS/

GP[1]

UART_TXD/

GP[31]/

I2S3_DX

SD1_D3/

GP[11]

SD1_D0/

I2S1_DX/

GP[8]

SD1_CLK/

I2S1_CLK/

GP[6]

SD0_CLK/

I2S0_CLK/

GP[0]

DV

EMU1

SPI_CS0

SPI_TX

SPI_CS1

EMU0

TDI

SPI_CS3

CV

DD

V

CV

DD

DDIO

SS

SD1_CMD/

I2S1_FS/

GP[7]

SD1_D2/

GP[10]

RSV2

USB_VBUS

V

SS

SPI_CLK

DV

V

SS

DDIO

USB_V

SS1P3

V

CV

DD

RSV1

USB_V

DD1P3

K

J

SS

SD0_D0/

I2S0_DX/

GP[2]

USB_V

SSA1P3

V

USB_DM

USB_DP

USB_R1

GP[12]

XF

SS

USB_

RSV10

RSV9

RSV8

USB_V

SSA3P3

CV

DD

V

H

G

F

SS

V

DDA1P3

CV

DD

RSV12

USB_V

DDA3P3

DDPLL

USB_V

DD1P3

V

CV

DD

SSREF

SSPLL

SS

V

USB_V

USB_MXI

RSV11

RESET

E

D

C

B

A

RSV7

SS

DD1P3

DDOSC

SSOSC

V

SS

V

USB_LDOO

USB_MXO

CLK_SEL

CV

DD

V

CV

DD

SS

DSP_LDO_

EN

V

BG_CAP

V

INT0

V

CV

DD

V

LDOI

CLKIN

INT1

DV

SCL

V

DV

SSA_ANA

SS

SSRTC

DDRTC

DDIO

DDA_PLL

SS

LDOI

V

CV

RSV3

V

ANA_LDOO

RSV5

RSV6

CV

V

NC

SS

DDRTC

SS

SSA_ANA

DDRTC

DDA_ANA

V

SDA

NC

10

RSV0

NC

RSV4

11

CLKOUT

RTC_CLKOUT

WAKEUP

RTC_XO

RTC_XI

SSA_PLL

DSP_LDOO

V

SS

1

2

3

4

5

6

7

8

9

12

13

14

Figure 3-2. C5534 Pin Map

Device Pins

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I2S2_CLK/

GP[18]/

SPI_CLK

SD0_D1/

I2S0_RX/

GP[3]

SD0_D3/

GP[5]

I2S2_RX/

GP[20]/

SPI_RX

SD1_D1/

I2S1_RX/

GP[9]

I2S2_DX/

GP[27]/

SPI_TX

UART_CTS/ UART_RXD/

GP[30]/

I2S3_RX

V

TRST

SS

GP[14]

GP[16]

TCK

V

P

N

M

L

GP[17]

SS

GP[29]/

I2S3_FS

I2S2_FS/

GP[19]/

SPI_CS0

UART_RTS/

GP[28]/

I2S3_CLK

SD0_D2/

GP[4]

SPI_CS2

GP[13]

TMS

GP[15]

DV

CV

DD

SPI_RX

TDO

DV

DDIO

SD0_CMD/

I2S0_FS/

GP[1]

UART_TXD/

GP[31]/

I2S3_DX

SD1_D3/

GP[11]

SD1_D0/

I2S1_DX/

GP[8]

SD1_CLK/

I2S1_CLK/

GP[6]

SD0_CLK/

I2S0_CLK/

GP[0]

DV

EMU1

SPI_CS0

SPI_TX

SPI_CS1

EMU0

TDI

SPI_CS3

CV

DD

V

CV

DD

DDIO

SS

SD1_CMD/

I2S1_FS/

GP[7]

SD1_D2/

GP[10]

RSV2

USB_VBUS

V

SS

SPI_CLK

DV

V

SS

DDIO

USB_V

SS1P3

V

CV

DD

RSV1

USB_V

DD1P3

K

J

SS

SD0_D0/

I2S0_DX/

GP[2]

USB_V

SSA1P3

V

USB_DM

USB_DP

USB_R1

GP[12]

XF

SS

USB_

RSV10

RSV9

RSV8

USB_V

SSA3P3

CV

DD

V

H

G

F

SS

V

DDA1P3

CV

DD

RSV12

USB_V

DDA3P3

DDPLL

USB_V

DD1P3

V

CV

DD

SSREF

SSPLL

SS

V

USB_V

USB_MXI

RSV11

RESET

E

D

C

B

A

RSV7

SS

DD1P3

DDOSC

SSOSC

V

SS

V

USB_LDOO

USB_MXO

CLK_SEL

CV

DD

V

CV

DD

SS

DSP_LDO_

(1)

EN

V

BG_CAP

V

INT0

V

CV

DD

V

LDOI

CLKIN

INT1

DV

SCL

V

DV

SSA_ANA

SS

SSRTC

DDRTC

DDIO

DDA_PLL

SS

LDOI

V

CV

RSV3

V

ANA_LDOO

RSV5

RSV6

CV

V

NC

SS

DDRTC

SS

SSA_ANA

DDRTC

DDA_ANA

V

SDA

NC

10

RSV0

RSV4

11

CLKOUT

RTC_CLKOUT

WAKEUP

RTC_XO

RTC_XI

NC

8

SSA_PLL

DSP_LDOO

V

SS

1

2

3

4

5

6

7

9

12

13

14

(1) Pin is not supported on this device. To ensure proper device operation, this pin must be hooked up properly. See Table 3-15,

Regulators and Power Management Terminal Functions.

(2) Shaded pins are not supported on this device. To ensure proper device operation, these pins must be hooked up properly. See

Table 3-9, Unsupported USB 2.0 Terminal Functions.

Figure 3-3. C5533 Pin Map

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I2S2_CLK/

GP[18]/

SPI_CLK

SD0_D1/

I2S0_RX/

GP[3]

SD0_D3/

GP[5]

I2S2_RX/

GP[20]/

SPI_RX

SD1_D1/

I2S1_RX/

GP[9]

I2S2_DX/

GP[27]/

SPI_TX

UART_CTS/ UART_RXD/

GP[30]/

I2S3_RX

V

TRST

SS

GP[14]

GP[16]

TCK

V

P

N

M

L

GP[17]

SS

GP[29]/

I2S3_FS

I2S2_FS/

GP[19]/

SPI_CS0

UART_RTS/

GP[28]/

I2S3_CLK

SD0_D2/

GP[4]

SPI_CS2

GP[13]

TMS

GP[15]

DV

CV

DD

SPI_RX

TDO

DV

DDIO

SD0_CMD/

I2S0_FS/

GP[1]

UART_TXD/

GP[31]/

I2S3_DX

SD1_D3/

GP[11]

SD1_D0/

I2S1_DX/

GP[8]

SD1_CLK/

I2S1_CLK/

GP[6]

SD0_CLK/

I2S0_CLK/

GP[0]

DV

EMU1

SPI_CS0

SPI_TX

SPI_CS1

EMU0

TDI

SPI_CS3

CV

DD

V

CV

DD

DDIO

SS

SD1_CMD/

I2S1_FS/

GP[7]

SD1_D2/

GP[10]

RSV2

USB_V

BUS

V

SS

SPI_CLK

DV

V

SS

DDIO

USB_V

SS1P3

V

CV

DD

RSV1

USB_V

DD1P3

K

J

SS

SD0_D0/

I2S0_DX/

GP[2]

USB_V

SSA1P3

V

USB_DM

USB_DP

USB_R1

GP[12]

XF

SS

USB_

RSV10

RSV9

RSV8

USB_V

SSA3P3

CV

DD

V

H

G

F

SS

V

DDA1P3

CV

DD

RSV12

USB_V

DDA3P3

DDPLL

USB_V

DD1P3

V

CV

DD

SSREF

SSPLL

SS

V

USB_V

USB_MXI

RSV11

RESET

E

D

C

B

A

RSV7

SS

DD1P3

DDOSC

SSOSC

V

SS

V

USB_

(1)

LDOO

USB_MXO

CLK_SEL

CV

DD

V

CV

DD

SS

DSP_LDO_

(1)

EN

V

BG_CAP

V

INT0

V

CV

DD

V

LDOI

CLKIN

INT1

DV

SCL

V

DV

SSA_ANA

SS

SSRTC

DDRTC

DDIO

DDA_PLL

SS

LDOI

V

CV

RSV3

V

ANA_LDOO

RSV5

RSV6

CV

V

NC

SS

DDRTC

SS

SSA_ANA

DDRTC

DDA_ANA

DSP_

(1)

LDOO

V

SDA

NC

10

RSV0

RSV4

11

CLKOUT

RTC_CLKOUT

WAKEUP

RTC_XO

RTC_XI

NC

8

SSA_PLL

V

SS

1

2

3

4

5

6

7

9

12

13

14

(1) Pin is not supported on this device. To ensure proper device operation, this pin must be hooked up properly. See Table 3-15,

Regulators and Power Management Terminal Functions.

(2) Shaded pins are not supported on this device. To ensure proper device operation, these pins must be hooked up properly. See

Table 3-9, Unsupported USB 2.0 Terminal Functions.

Figure 3-4. C5532 Pin Map

Device Pins

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3.2 Terminal Functions

The terminal functions tables (Table 3-1 through Table 3-18) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin

has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more

detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging

considerations, see the Device Configuration section of this data manual.

For proper device operation, external pullup/pulldown resistors may be required on some pins.

Section 4.8.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are

required.

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Table 3-1. Oscillator/PLL Terminal Functions

TYPE⁽¹⁾

SIGNAL

OTHER^{(3) (4)}

DESCRIPTION

(2)

NAME

NO.

DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap

different clocks within the system clock generator. The SRC bits in the CLKOUT

Control Source Register (CCSSR) can be used to specify the CLKOUT pin source.

Additionally, the slew rate of the CLKOUT pin can be controlled by the Output

Slew Rate Control Register (OSRCR) [0x1C16].

–

The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55

register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At

reset the CLKOUT pin is enabled until the beginning of the boot sequence, when

the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z).

For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU

Reference Guide (literature number: SWPU073).

CLKOUT

A2

O/Z

DV_DDIO

BH

Note: This pin may consume static power if configured as Hi-Z and not externally

pulled low or high. Prevent current drain by externally terminating the pin.

Input clock. This signal is used to input an external clock when the 32-KHz on-chip

oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the

CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.

The CLK_SEL pin (D1) selects between the 32-KHz crystal clock or CLKIN.

–

When the CLK_SEL pin is low, this pin should be tied to ground (V_SS). When

CLK_SEL is high, this pin should be driven by an external clock source.

CLKIN

C1

I

DV_DDIO

BH

If CLK_SEL is high, this pin is used as the reference clock for the clock generator

and during bootup the bootloader bypasses the PLL and assumes the CLKIN

frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With

these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz and

the I2C clock rate at 400 KHz.

Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN.

0 = 32-KHz on-chip oscillator drives the RTC timer and the system clock generator

while CLKIN is ignored.

–

CLK_SEL

D1

I

DV_DDIO

BH

1 = CLKIN drives the system clock generator and the 32-KHz on-chip oscillator

drives only the RTC timer.

This pin is not allowed to change during device operation; it must be tied high or

low at the board.

1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120

MHz).

see Section 5.2,

ROC

V_{DDA_PLL}

C7

A1

PWR

GND

This signal can be powered from the ANA_LDOO pin.

Analog PLL ground for the system clock generator.

see Section 5.2,

ROC

V_{SSA_PLL}

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply

current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

Device Pins

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Table 3-2. Real-Time Clock (RTC) Terminal Functions

TYPE⁽¹⁾

SIGNAL

NAME

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

Real-time clock oscillator output. This pin operates at the RTC core voltage,

CV_DDRTC, and supports a 32.768-kHz crystal.

If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

CV_DDRTCand RTC_XO to floating or grounded. A voltage must still be applied to

CV_DDRTC(see Section 5.2, Recommended Operating Conditions).

–

RTC_XO

RTC_XI

A6

I/O/Z

CV_DDRTC

Note: When RTC oscillator is disabled, the RTC registers (I/O address range

1900h – 197Fh) are not accessible.

Real-time clock oscillator input.

If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

CV_DDRTCand RTC_XO to ground (V_SS). A voltage must still be applied to CV_DDRTC

(see Section 5.2, Recommended Operating Conditions).

–

A7

I

CV_DDRTC

Note: When RTC oscillator is disabled, the RTC registers (I/O address range

1900h – 197Fh) are not accessible.

Real-time clock output pin. This pin operates at DV_DDRTCvoltage. The

RTC_CLKOUT pin is enabled/disabled through the RTCCLKOUTEN bit in the RTC

Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is

disabled (high-impedance [Hi-Z]).

–

RTC_CLKOUT

WAKEUP

A3

A5

O/Z

DV_DDRTC

The pin is used to WAKEUP the core from idle condition. This pin defaults to an

input at CV_DDRTCpowerup, but can also be configured as an active-low open-drain

output signal to wakeup an external device from an RTC alarm.

–

I/O/Z

DV_DDRTC

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply

current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

30

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Table 3-3. RESET, Interrupts, and JTAG Terminal Functions

SIGNAL

NAME

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NO.

RESET

External Flag Output. XF is used for signaling other processors in

multiprocessor configurations or XF can be used as a fast

general-purpose output pin.

XF is set high by the BSET XF instruction and XF is set low by the

BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For

more information on the ST1_55 register, see the TMS320C55x 3.0

CPU Reference Guide (literature number: SWPU073).

–

XF

J3

O/Z

DV_DDIO

BH

For XF pin behavior at reset, see Section 6.7.2, Pin Behavior at Reset.

Note: This pin may consume static power if configured as Hi-Z and not

externally pulled low or high. Prevent current drain by externally

terminating the pin. XF pin is ONLY in the Hi-Z state when doing

boundary scan. Therefore, external termination is probably not required

for most applications.

Device reset. RESET causes the DSP to terminate execution and loads

the program counter with the contents of the reset vector. When

RESET is brought to a high level, the reset vector in ROM at FFFF00h

forces the program execution to branch to the location of the on-chip

ROM bootloader.

IPU

DV_DDIO

BH

RESET

D2

I

RESET affects the various registers and status bits.

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register but will be forced ON when RESET is asserted.

JTAG

[For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number:

SPRU589).]

IEEE standard 1149.1 test mode select. This serial control input is

clocked into the TAP controller on the rising edge of TCK.

If the emulation header is located greater than 6 inches from the

device, TMS must be buffered. In this case, the input buffer for TMS

IPU

DV_DDIO

BH

needs a pullup resistor connected to DV_DDIOto hold the signal at a

known value when the emulator is not connected. A resistor value of

4.7 kΩ or greater is suggested. For board design guidelines related to

the emulation header, see the XDS560 Emulator Technical Reference

(literature number: SPRU589).

TMS

N6

I

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

IEEE standard 1149.1 test data output. The contents of the selected

register (instruction or data) are shifted out of TDO on the falling edge

of TCK. TDO is in the high-impedance (Hi-Z) state except when the

scanning of data is in progress.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

–

TDO

N1

O/Z

DV_DDIO

BH

If the emulation header is located greater than 6 inches from the

device, TDO must be buffered.

Note: This pin may consume static power if configured as Hi-Z and not

externally pulled low or high. Prevent current drain by externally

terminating the pin. TDO pin will be in Hi-Z whenever not doing

emulation/boundary scan, so an external pullup is highly recommended.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply

current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

Device Pins

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Table 3-3. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL

NAME

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NO.

IEEE standard 1149.1 test data input. TDI is clocked into the selected

register (instruction or data) on a rising edge of TCK.

If the emulation header is located greater than 6 inches from the

device, TDI must be buffered. In this case, the input buffer for TDI

needs a pullup resistor connected to DV_DDIOto hold this signal at a

known value when the emulator is not connected. A resistor value of

4.7 kΩ or greater is suggested.

IPU

DV_DDIO

BH

TDI

K2

I

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

IEEE standard 1149.1 test clock. TCK is normally a free-running clock

signal with a 50% duty cycle. The changes on input signals TMS and

TDI are clocked into the TAP controller, instruction register, or selected

test data register on the rising edge of TCK. Changes at the TAP output

signal (TDO) occur on the falling edge of TCK.

IPU

DV_DDIO

BH

If the emulation header is located greater than 6 inches from the

device, TCK must be buffered.

TCK

N3

I

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

IEEE standard 1149.1 reset signal for test and emulation logic. TRST,

when high, allows the IEEE standard 1149.1 scan and emulation logic

to take control of the operations of the device. If TRST is not connected

or is driven low, the device operates in its functional mode, and the

IEEE standard 1149.1 signals are ignored. The device will not operate

properly if this reset pin is never asserted low.

IPD

DV_DDIO

BH

TRST

P4

I

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

It is recommended that an external pulldown resistor be used in

addition to the IPD -- especially if there is a long trace to an emulation

header.

Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator

system and is defined as input/output by way of the emulation logic.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

IPU

DV_DDIO

BH

An external pullup to DV_DDIOis required to provide a signal rise time of

less than 10 μsec. A 4.7-kΩ resistor is suggested for most applications.

EMU1

M1

I/O/Z

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

Emulator 0 pin. When TRST is driven low and then high, the state of

the EMU0 pin is latched and used to connect the JTAG pins (TCK,

TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when

the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the

latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an

interrupt to or from the emulator system and is defined as input/output

by way of the emulation logic.

IPU

DV_DDIO

BH

EMU0

L2

I/O/Z

An external pullup to DV_DDIOis required to provide a signal rise time of

less than 10 μsec. A 4.7-kΩ resistor is suggested for most applications.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

EXTERNAL INTERRUPTS

32

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Table 3-3. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL

NAME

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NO.

IPU

DV_DDIO

BH

External interrupt inputs (INT1 and INT0). These pins are maskable via

their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt

mode bit. The pins can be polled and reset by their specific Interrupt

Flag Register (IFR1, IFR0).

INT1

INT0

B1

I

IPU

DV_DDIO

BH

C2

The IPU resistor on these pins can be enabled or disabled via the

PDINHIBR2 register.

Table 3-4. Inter-Integrated Circuit (I2C) Terminal Functions

TYPE⁽¹⁾

SIGNAL

OTHER^{(3) (4)}

DESCRIPTION

(2)

NAME

NO.

I2C

DV_DDIO

BH

This pin is the I2C clock output. Per the I2C standard, an external pullup is required

on this pin.

SCL

SDA

C4

A4

I/O/Z

DV_DDIO

BH

This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup

is required on this pin.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply

current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

Device Pins

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Table 3-5. Inter-IC Sound (I2S0 – I2S3) Terminal Functions

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION⁽⁵⁾

(2)

NO.

Interface 0 (I2S0)

This pin is multiplexed between SD0, I2S0, and GPIO.

For I2S, it is I2S0 transmit data output I2S0_DX.

SD0_D0/

I2S0_DX/

GP[2]

IPD

DV_DDIO

BH

J1

I/O/Z

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD0, I2S0, and GPIO.

For I2S, it is I2S0 clock input/output I2S0_CLK.

SD0_CLK/

I2S0_CLK/

GP[0]

IPD

DV_DDIO

BH

M8

P6

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD0, I2S0, and GPIO.

For I2S, it is I2S0 receive data input I2S0_RX.

SD0_D1/

I2S0_RX/

GP[3]

IPD

DV_DDIO

BH

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD0, I2S0, and GPIO.

SD0_CMD/

I2S0_FS/

GP[1]

IPD

DV_DDIO

BH

For I2S, it is I2S0 frame synchronization input/output I2S0_FS.

M10

Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

Interface 1 (I2S1)

This pin is multiplexed between SD1, I2S1, and GPIO.

SD1_D0/

2S1_DX/

GP[8]

IPD

DV_DDIO

BH

For I2S, it is I2S1 transmit data output I2S1_DX.

M13

M14

P10

L11

I/O/Z

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD1, I2S1, and GPIO.

For I2S, it is I2S1 clock input/output I2S1_CLK.

SD1_CLK/

I2S1_CLK/

GP[6]

IPD

DV_DDIO

BH

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD1, I2S1, and GPIO.

For I2S, it is I2S1 receive data input I2S1_RX.

SD1_D1/

I2S1_RX/

GP[9]

IPD

DV_DDIO

BH

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

This pin is multiplexed between SD1, I2S2, and GPIO.

SD1_CMD/

I2S1_FS/

GP[7]

IPD

DV_DDIO

BH

For I2S, it is I2S1 frame synchronization input/output I2S1_FS.

Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply

current. If this is the case, enable IPD/IPU, if applicable, or externally terminate the pins.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

(5) LCD Bridge applies only to TMS320C5535.

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Table 3-5. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION⁽⁵⁾

(2)

NO.

Interface 2 (I2S2)

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

For I2S, it is I2S2 transmit data output I2S2_DX.

LCD_D[11]/

I2S2_DX/

GP[27]/

IPD

DV_DDIO

BH

P11

I/O/Z

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

SPI_TX

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

For I2S, it is I2S2 clock input/output I2S2_CLK.

LCD_D8]/

I2S2_CLK/

GP[18]/

IPD

DV_DDIO

BH

P5

P9

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

SPI_CLK

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

For I2S, it is I2S2 receive data input I2S2_RX.

LCD_D[10]/

I2S2_RX/

GP[20]/

IPD

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

SPI_RX

This pin is multiplexed between LCD Bridge, I2S2, and GPIO.

For I2S, it is I2S2 frame synchronization input/output I2S2_FS.

LCD_D[9]/

I2S2_FS/

GP[19]/

IPD

DV_DDIO

BH

N10

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

SPI_CS0

Interface 3 (I2S3)

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

LCD_D[15]/

UART_TXD/

GP[31]/

IPD

DV_DDIO

BH

For I2S, it is I2S3 transmit data output I2S3_DX.

M11

N12

P13

P12

I/O/Z

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

I2S3_DX

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

For I2S, it is I2S3 clock input/output I2S3_CLK.

LCD_D[12]/

UART_RTS/

GP[28]/

IPD

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

I2S3_CLK

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

For I2S, it is I2S3 receive data input I2S3_RX.

LCD_D[14]/

UART_RXD/

GP[30]/

IPD

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

I2S3_RX

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

For I2S, it is I2S3 frame synchronization input/output I2S3_FS.

LCD_D[13]/

UART_CTS/

GP[29]/

IPD

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR3 register.

I2S3_FS

Device Pins

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Table 3-6. Serial Peripheral Interface (SPI) Terminal Functions

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION⁽⁵⁾

(2)

NO.

Serial Port Interface (SPI)

This pin is multiplexed between LCD Bridge and SPI.

Mux control via the PPMODE bits in the EBSR.

LCD_CS0_E0/

SPI_CS0

DV_DDIO

BH

L1

I/O/Z

For SPI, this pin is SPI chip select SPI_CS0.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

LCD_D[9]/

I2S2_FS/

GP[19]/

IPD

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI chip select SPI_CS0.

N10

M2

SPI_CS0

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_CS1_E1/

SPI_CS1

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI chip select SPI_CS1.

This pin is multiplexed between LCD Bridge and SPI.

LCD_RW_WRB/

SPI_CS2

DV_DDIO

BH

N2

M5

I/O/Z

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI chip select SPI_CS2.

This pin is multiplexed between LCD Bridge and SPI.

LCD_RS/

SPI_CS3

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI chip select SPI_CS3.

This pin is multiplexed between LCD Bridge and SPI.

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is clock output SPI_CLK.

LCD_EN_RDB/

SPI_CLK

DV_DDIO

BH

L3

O/Z

Note: This pin may consume static power if configured as Hi-Z and not externally

pulled low or high. Prevent current drain by externally terminating the pin.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is clock output SPI_CLK.

LCD_D8]/

I2S2_CLK/

GP[18]/

IPD

DV_DDIO

BH

P5

K1

I/O/Z

SPI_CLK

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_D[1]/

SPI_TX

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI transmit data output.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR.

LCD_D[11]/

I2S2_DX/

GP[27]/

IPD

DV_DDIO

BH

P11

N4

P9

For SPI, this pin is SPI transmit data output.

SPI_TX

The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

LCD_D[0]/

SPI_RX

DV_DDIO

BH

Mux control via the PPMODE bits in the EBSR.

For SPI this pin is SPI receive data input.