TLV6700DDCT [TI]
采用集成基准的低功耗窗口比较器 | DDC | 6 | -40 to 125;
| 型号： | TLV6700DDCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用集成基准的低功耗窗口比较器 | DDC | 6 | -40 to 125 比较器 |
| 文件： | 总32页 (文件大小：2577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
具有 400mV 基准电压的 TLV6700 微功耗、18V 窗口比较器
1 特性
3 说明
1
•
宽电源电压范围：1.8V 至 18V
可调节阈值：低至 400mV
高阈值精度：
TLV6700 是一个工作电压范围为 1.8V 至 18V 的高电
压窗口比较器。该器件拥有两个内部基准电压为
400mV 的高精度比较器和两个额定电压为 18V 的开漏
输出。TLV6700 可以作为窗口比较器使用，也可以作
为两个独立的比较器使用。可以使用外部电阻器设定监
控电压。
•
•
–
–
25°C 时最高为 0.5%
在工作温度范围内最高为 1.0%
•
•
•
•
•
低静态电流：5.5µA（典型值）
开漏输出
当 INA+ 上的电压下降至低于 (VITP - VHYS)时，OUTA
被驱动至低电平，当电压返回到相应阈值 (VITP) 之上
时，OUTA 变为高电平。当 INB- 上的电压上升至高于
内部迟滞：5.5mV（典型值）
温度范围：–40°C 至 125°C
封装：
VITP时，OUTB 被驱动至低电平，当电压下降至低于相
–
–
薄型 SOT-23-6
应阈值 (VITP - VHYS) 时，OUTB 变为高电平。
TLV6700 中的两个比较器都具有用于抑制短时毛刺脉
冲的内置迟滞，从而确保稳定的输出运行，不会引起误
触发。
WSON-6
2 应用
•
•
•
•
•
•
•
•
笔记本电脑和平板电脑
TLV6700 采用薄型 SOT-23-6 和无引线 WSON-6 封
装，所有封装型号的额定结温范围为 –40°C 至 125°
C。
智能手机
数码相机
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继电器和断路器
便携式医疗设备
门窗传感器
器件信息(1)
器件型号
TLV6700
封装
SOT-23 (6)
WSON (6)
封装尺寸（标称值）
2.90mm × 1.60mm
1.50mm × 1.50mm
便携式电池供电类产品
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
输出响应
简化方框图
VPULL-UP
(Up To 18 V)
1.8 V to 18 V
VDD
VIT+
INA+
OUTA
INA+
OUTB
INBœ
VIT+
INB–
Reference
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAV2
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 15
9.3 Do's and Don'ts....................................................... 17
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Switching Characteristics.......................................... 6
7.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 器件支持................................................................ 20
12.2 接收文档更新通知 ................................................. 20
12.3 社区资源................................................................ 20
12.4 商标....................................................................... 20
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (April 2018) to Revision B
Page
•
已添加 添加了 WSON-6 封装 ................................................................................................................................................. 1
Changes from Original (Jan 2018) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”发布............................................................................................................................. 1
5 Device Comparison Table
Table 1. TLV67xx Integrated Comparator Family
OPERATING
VOLTAGE RANGE
THRESHOLD ACCURACY OVER
TEMPERATURE
PART NUMBER
CONFIGURATION
TLV6700
TLV6703
TLV6710
TLV6713
Window
1.8 V to 18 V
1.8 V to 18 V
1.8 V to 36 V
1.8 V to 36 V
1%
1%
Non-Inverting Single Channel
Window
0.75%
0.75%
Non-Inverting Single Channel
2
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
www.ti.com.cn
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
6 Pin Configuration and Functions
DDC Package
SOT-23-6
Top View
OUTA
GND
INA+
1
2
3
6
5
4
OUTB
VDD
INB-
DSE Package
WSON-6
Top View
OUTB
VDD
1
2
3
6
5
4
OUTA
GND
INA+
INB-
Pin Functions
PIN
DDC
I/O
DESCRIPTION
NAME
DSE
GND
2
5
—
Ground
This pin is connected to the voltage to be monitored with the use of an external
resistor divider. When the voltage at this terminal drops below the threshold voltage
(VITP – VHYS), OUTA is driven low.
INA+
INB–
3
4
3
6
I
I
This pin is connected to the voltage to be monitored with the use of an external
resistor divider. When the voltage at this terminal exceeds the threshold voltage
(VITP), OUTB is driven low.
4
1
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VITP – VHYS). The output goes high when the sense voltage
returns above the respective threshold (VITP).
OUTA
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VITP. The output goes high when the sense voltage returns
below the respective threshold (VITP – VHYS).
OUTB
VDD
6
5
1
2
O
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device.
Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
Copyright © 2018–2019, Texas Instruments Incorporated
3
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
V
VDD
Voltage(2)
OUTA, OUTB
20
V
INA+, INB–
7
V
Current
Output terminal current
40
mA
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
125
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX UNIT
VDD
VI
Supply voltage
Input voltage
Output voltage
18
6.5
18
V
V
V
INA+, INB–
VO
OUTA, OUTB
0
7.4 Thermal Information
TLV6700
DDC
(SOT)
DSE
THERMAL METRIC(1)
UNIT
(WSON)
6 PINS
194.9
128.9
153.8
11.9
6 PINS
204.6
50.5
54.3
0.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
52.8
N/A
157.4
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
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ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
Power-on reset voltage(1)
TEST CONDITIONS
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
VDD = 1.8V and 18 V, TJ = 25°C
MIN
TYP
MAX UNIT
V(POR)
VIT+
0.8
402.5
404
397.5
400
12
V
398
396
400
Positive-going input threshold voltage
Negative-going input threshold voltage
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
VDD = 1.8V and 18 V, TJ = 25°C
391.6
387
394.5
VIT–
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
Vhys
Hysteresis voltage (hys = VIT+ – VIT–
Input current (at the INA+ terminal)
Input current (at the INB– terminal)
)
5.5
1
mV
nA
nA
I(INA+)
I(INB–)
VDD = 1.8 V and 18 V, VI = 6.5 V
VDD = 1.8 V and 18 V, VI = 0.1 V
VDD = 1.3 V, IO = 0.4 mA
VDD = 1.8 V, IO = 3 mA
VDD = 5 V, IO = 5 mA
VDD = 1.8 V and 18 V, VO = VDD
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
VDD = 5 V
–25
–15
25
1
15
250
250
250
300
300
11
VOL
Low-level output voltage
mV
nA
Ilkg(OD)
Open-drain output leakage-current
5.5
6
13
IDD
Supply current
µA
VDD = 12 V
6
13
VDD = 18 V
7
13
Start-up delay(2)
Undervoltage lockout(3)
150
450
1.7
µs
V
UVLO
VDD falling
1.3
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
(3) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR)
.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
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7.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
tPHL
High-to-low propagation delay(1)
Low-to-high propagation delay(1)
18
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 1
tPLH
29
µs
(1) High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
7.7 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
Output rise time
Output fall time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tr
tf
2.2
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
0.22
µs
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 1. Timing Diagram
6
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
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ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
7.8 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
10
9
8
7
6
5
4
3
2
1
0
401
400.6
400.2
399.8
399.4
399
VDD = 1.8 V
VDD = 5 V
VDD = 1.2 V
VDD = 18 V
-40èC
0èC
25èC
85èC
125èC
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D001
D003
Figure 2. Supply Current (IDD) vs Supply Voltage (VDD
)
Figure 3. Rising Input Threshold Voltage (VIT+) vs
Temperature
9
8
7
6
5
4
3
31
29
27
25
23
21
19
17
15
13
11
9
VDD = 1.8 V, INB- to OUTB
VDD = 18 V, INB- to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D005
D004
Figure 5. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Figure 4. Hysteresis (Vhys) vs Temperature
30
28
26
24
22
20
18
16
14
12
10
8
20
18
16
14
12
10
8
INA+
INB–
6
VDD = 1.8 V, INB- to OUTB
VDD = 18 V, INB- to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
4
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
2.5
4
5.5
7
8.5
Positive-Going Input Threshold Overdrive (%)
10 11.5
13 14.5 16
D006
D007
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 6. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
Figure 7. Minimum Pulse Duration vs
Threshold Overdrive Voltage
Copyright © 2018–2019, Texas Instruments Incorporated
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TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
11
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
10
9
8
7
6
5
4
3
2
1
-40èC
0èC
25èC
85èC
125èC
500
250
0
0
4
8
12
16
20
24
Output Sink Current (mA)
28
32
36
40
0
0
0
5
10
15
20
25
Output Sink Current (mA)
30
35
40
D008
D009
Figure 8. Supply Current (IDD) vs
Output Sink Current
Figure 9. Output Voltage Low (VOL) vs
Output Sink Current (–40°C)
2000
1750
1500
1250
1000
750
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
500
500
250
250
0
0
0
5
10
15
Output Sink Current (mA)
20
25
30
35
40
5
10
15
Output Sink Current (mA)
20
25
30
35
40
D010
D011
Figure 10. Output Voltage Low (VOL) vs
Output Sink Current (0°C)
Figure 11. Output Voltage Low (VOL) vs
Output Sink Current (25°C)
2000
1750
1500
1250
1000
750
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
500
500
250
250
0
0
0
5
10
15
Output Sink Current (mA)
20
25
30
35
40
5
10
15
Output Sink Current (mA)
20
25
30
35
40
D012
D013
Figure 12. Output Voltage Low (VOL) vs
Output Sink Current (85°C)
Figure 13. Output Voltage Low (VOL) vs
Output Sink Current (125°C)
8
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TLV6700
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ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
8 Detailed Description
8.1 Overview
The TLV6700-Q1 device combines two comparators for overvoltage and undervoltage detection. The TLV6700-
Q1 has a wide-supply voltage range (1.8 V to 18 V) with a high-accuracy rising-input threshold of 400 mV (1%
over temperature) and built-in hysteresis. The outputs are also rated to 18 V, independant of supply voltage, and
can sink up to 40 mA.
The TLV6700-Q1 is designed to assert the output signals, as shown in Table 2. Each input terminal can be set to
monitor any voltage above 0.4 V using an external resistor divider network. Each input pin has very low input
leakage current, allowing the use of large resistor dividers without sacrificing system accuracy. With the use of
two input terminals of different polarities, the TLV6700-Q1 forms a window comparator. The relationship between
the inputs and the outputs is shown in Table 2. Broad voltage thresholds can be supported that allow the device
to be used in a wide array of applications.
Table 2. TLV6700-Q1 Truth Table
CONDITION
INA+ > VIT+
INA+ < VIT–
INB– > VIT+
INB– < VIT–
OUTPUT
OUTA high
OUTA low
OUTB low
OUTB high
OUTPUT STATE
Output A high impedance
Output A sinking
Output B sinking
Output B high impedance
8.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
8.3 Feature Description
8.3.1 Inputs (INA+, INB–)
The TLV6700-Q1 device combines two comparators. Each comparator has one external input (inverting and
noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling
hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although
not required in most cases, good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the
comparator input for extremely noisy applications to reduce sensitivity to transients and layout parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 1.
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TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Feature Description (continued)
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see
Figure 1. Together, these comparators form a window-detection function as discussed in the Window
Comparator section.
8.3.2 Outputs (OUTA, OUTB)
In a typical TLV6700-Q1 application, the outputs are connected to a GPIO input of the processor (such as a
digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]).
The TLV6700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to
hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to
the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels.
The TLV6700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. By using wired-OR
logic, OUTA and OUTB can merge into one logic signal that goes low if either outputs are asserted because of a
fault condition.
Table 2 and the Inputs (INA+, INB–) section describe how the outputs are asserted or deasserted. See Figure 1
for a timing diagram that describes the relationship between threshold voltages and the respective output.
8.3.3 Window Comparator
The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit
using a resistor divider network, as illustrated in Figure 14 and Figure 15. The input terminals can monitor any
system voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor
for undervoltage and overvoltage conditions, respectively.
Figure 14. Window Comparator Block Diagram
10
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TLV6700
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ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
Feature Description (continued)
Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 15. Window Comparator Timing Diagram
8.3.4 Immunity to Input Terminal Voltage Transients
The TLV6700-Q1 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity
to transients depends on both transient duration and amplitude; see the Minimum Pulse Duration vs Threshold
Overdrive Voltage curve (Figure 7) in the Typical Characteristics section.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to
the voltage on INA+ and INB– as listed in Table 2.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA+ and INB–.
8.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),
both outputs are in a high-impedance state.
Copyright © 2018–2019, Texas Instruments Incorporated
11
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 V to
18 V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window
comparator or as two independent voltage monitors. The monitored voltages are set with the use of external
resistors.
9.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However, some applications may require the outputs to be
pulled up to a higher or lower voltage than VDD to correctly interface with the input terminals of other devices.
Figure 16. Interfacing to Voltages Other Than VDD
12
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
www.ti.com.cn
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
Application Information (continued)
9.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
Figure 17. Monitoring the Same Voltage as VDD
9.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering VDD. In these types of applications the
resistor divider used to set the desired thresholds is connected to the rail that is being monitored.
Copyright © 2018–2019, Texas Instruments Incorporated
13
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Application Information (continued)
NOTE: The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 18. Monitoring a Voltage Other Than VDD
14
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
www.ti.com.cn
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
9.2 Typical Application
The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 to 18
V. The monitored voltages are set with the use of external resistors, so the device can be used either as a
window comparator or as two independent overvoltage and undervoltage monitors.
V
V
DD
PULLUP
C1
0.1 µF
R4
49.9 kꢀ
R5
49.9 kꢀ
U1
TLV6700DDC
R1
2.21 Mꢀ
V
DD
OUTA
5
1
INA+
OUTB
GND
3
4
6
2
INBœ
R2
13.7 kꢀ
R3
69.8 kꢀ
Figure 19. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the values summarized in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
12-V nominal rail with maximum rising and
falling thresholds of ±10%
VMON(UV)= 10.99 V (8.33%) ±2.94%,
VMON(OV)= 13.14 V (8.33%) ±2.94%
Monitored voltage
9.2.2 Detailed Design Procedure
9.2.2.1 Resistor Divider Selection
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltages.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100 times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
RT
R3 =
´ VIT+
VMON(OV)
where:
VMON(OV) is the target voltage at which an overvoltage condition is detected
(2)
Copyright © 2018–2019, Texas Instruments Incorporated
15
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
´ VIT+ - R3
VMON (no UV)
where:
VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
(3)
(4)
RT
R2 =
´ (VIT+ - Vhys
)
- R3
VMON(UV)
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450,
Optimizing Resistor Dividers at a Comparator Input (available for download at www.ti.com). An example of the
rising threshold error, VMON(OV), is given in Equation 5.
VIT+(INB)
0.4
13.2
% ACC = % TOL(VIT+(INB)) + 2 ´
´ % TOLR = 1% + 2 ´
1-
1-
´ 1% = 2.94%
VMON(OV)
(5)
9.2.2.2 Pullup Resistor Selection
To ensure proper voltage levels, the pullup resistor value is selected by ensuring that the pullup voltage divided
by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated by
verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater the
desired logic-high voltage. These values are specified in the Electrical Characteristics table.
Use Equation 6 to calculate the value of the pullup resistor.
(VHI - VPU)
VPU
IO
³ RPU
³
Ilkg(OD)
(6)
9.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the VDD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
9.2.2.4 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
16
Copyright © 2018–2019, Texas Instruments Incorporated
TLV6700
www.ti.com.cn
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
9.2.3 Application Curves
At TJ = 25°C
OUTB
C2
(2 V/div)
C2
(2 V/div)
OUTB
OUTA
C1
(2 V/div)
OUTA
C1
(2 V/div)
C3
(2 V/div)
C3
(2 V/div)
VDD
VDD
Time (100 µs/div)
Time (100 µs/div)
G013
G014
VDD = 5 V
V(INA+) = 390 mV
V(INB–) = 410 mV
VDD = 5 V
V(INA+) = 410 mV
V(INB–) = 390 mV
Figure 20. Start-Up Delay
(Outputs Pulled Up to VDD
Figure 21. Start-Up Delay
(Outputs Pulled Up to VDD
)
)
9.3 Do's and Don'ts
It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND.
If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND.
Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the
input current of the comparators without also accounting for the effect to the accuracy.
Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
Copyright © 2018–2019, Texas Instruments Incorporated
17
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
10 Power Supply Recommendations
The TLV6700-Q1 has a 20 V absolute maximum rating on the VDD pin, with a recommended operating condition
of 18V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may
exceed 20 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions.
Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A
100-Ω resistor and 0.01-µF capacitor is required in these cases, as shown in Figure 22.
100 Ω
0.01 ꢀF
+
œ
VPULLUP
R1
VDD
INA
INB
OUTA
OUTB
R2
R3
GND
Figure 22. Using an RC Filter to Remove High-Frequency Disturbances on VDD
11 Layout
11.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (as shown in
Figure 23) or both resistors can be tied to a single pullup resistor if a logical AND function is desired.
18
版权 © 2018–2019, Texas Instruments Incorporated
TLV6700
www.ti.com.cn
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
11.2 Layout Example
Figure 23. TLV6700-Q1 Layout Schematic
版权 © 2018–2019, Texas Instruments Incorporated
19
TLV6700
ZHCSHH1B –JANUARY 2018–REVISED NOVEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
DIP 适配器评估模块可以将 SOT-23-6 封装转换为标准 DIP-6 引脚排列以便轻松构建原型和进行工作台评估。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV6700DDCR
TLV6700DDCT
TLV6700DSER
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DSE
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
1I51
1I51
HD
NIPDAU
NIPDAU
ACTIVE
WSON
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6700DDCR
TLV6700DDCT
TLV6700DSER
SOT-23-
THIN
DDC
DDC
DSE
6
6
6
3000
250
180.0
180.0
178.0
8.4
8.4
8.4
3.2
3.2
1.7
3.2
3.2
1.7
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q2
SOT-23-
THIN
1.4
WSON
3000
0.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV6700DDCR
TLV6700DDCT
TLV6700DSER
SOT-23-THIN
SOT-23-THIN
WSON
DDC
DDC
DSE
6
6
6
3000
250
213.0
213.0
205.0
191.0
191.0
200.0
35.0
35.0
33.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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TLV6703
具有集成基准电压的 18V 比较器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6703-Q1
具有集成基准的汽车类 18V 比较器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6703DDCR
具有集成基准电压的 18V 比较器 | DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6703DDCT
具有集成基准电压的 18V 比较器 | DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6703DSER
具有集成基准电压的 18V 比较器 | DSE | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TLV6703QDSERQ1
具有集成基准的汽车类 18V 比较器 | DSE | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6710
采用集成基准的低功耗高电压窗口比较器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6710DDCR
采用集成基准的低功耗高电压窗口比较器
| DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLV6710DDCT
采用集成基准的低功耗高电压窗口比较器
| DDC | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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