TLV5620CDR [TI]

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS; 翻两番8位数字 - 模拟转换器


型号：	TLV5620CDR
厂家：	TEXAS INSTRUMENTS
描述：	QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS 翻两番8位数字 - 模拟转换器转换器数模转换器光电二极管 CD PC
文件：	总16页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

D OR N PACKAGE

(TOP VIEW)

Four 8-Bit Voltage Output DACs

3-V Single-Supply Operation

Serial Interface

GND

REFA

REFB

REFC

REFD

DATA

CLK

High-Impedance Reference Inputs

LDAC

DACA

DACB

DACC

DACD

LOAD

Programmable for 1 or 2 Times Output

Range

Simultaneous Update Facility

Internal Power-On Reset

Low-Power Consumption

Half-Buffered Output

applications

Programmable Voltage Sources

Digitally Controlled Amplifiers/Attenuators

Mobile Communications

Automatic Test Equipment

Process Monitoring and Control

Signal Synthesis

description

The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with

buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either

one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,

because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure

repeatable start-up conditions.

Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible

and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word

comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times

1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be

written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs

feature Schmitt triggers for high noise immunity.

The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical

applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized

for operation from –40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

0°C to 70°C

TLV5620CD

TLV5620ID

TLV5620CN

TLV5620IN

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

functional block diagram

REFA

–

DAC

–

DACA

DACB

DACC

DACD

× 2

Latch

REFB

–

REFC

REFD

–

CLK

DATA

LOAD

Power-On

Reset

Serial

Interface

LDAC

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

CLK

NO.

Serialinterface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock

applied to the CLK terminal.

DACA

DACB

DACC

DACD

DATA

DAC A analog output

DAC B analog output

DAC C analog output

DAC D analog output

Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.

Each data bit is clocked into the register on the falling edge of the clock signal.

GND

Ground return and reference terminal

LDAC

Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial

interface. The DAC outputs are only updated when LDAC is taken from high to low.

LOAD

Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital

data into the output latch and immediately produces the analog voltage at the DAC output terminal.

REFA

REFB

REFC

REFD

Reference voltage input to DAC A. This voltage defines the output analog range.

Reference voltage input to DAC B. This voltage defines the analog output range.

Reference voltage input to DAC C. This voltage defines the analog output range.

Reference voltage input to DAC D. This voltage defines the analog output range.

Positive supply voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

detailed description

The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with

256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected

to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use

of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance

of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the

reference source.

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or

times 2 gain.

On power up, the DACs are reset to CODE 0.

Each output voltage is given by:

CODE

V (DACA|B|C|D)

REF

(1 RNG bit value)

256

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer

•

OUTPUT VOLTAGE

GND

(1/256) × REF (1+RNG)

•

(127/256) × REF (1+RNG)

(128/256) × REF (1+RNG)

•

(255/256) × REF (1+RNG)

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have

been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as

shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When

LDAC is high during serial programming, the new value is stored within the device and can be transferred to

the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data

transfers using two 8-clock-cycle periods are shown in Figures 3 and 4.

Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output

range. When RNG = low, the output range is between the applied reference voltage and GND, and when

RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

DAC UPDATED

DACA

DACB

DACC

DACD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

CLK

su(DATA-CLK)

su(LOAD-CLK)

D2 D1

su(CLK-LOAD)

v(DATA-CLK)

DATA

LOAD

A0 RNG

w(LOAD)

DAC Update

Figure 1. LOAD-Controlled Update (LDAC = Low)

CLK

su(DATA-CLK)

v(DATA-CLK)

DATA

A0 RNG

su(LOAD-LDAC)

LOAD

LDAC

w(LDAC)

DAC Update

Figure 2. LDAC-Controlled Update

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLK Low

CLK

RNG

DATA

LOAD

LDAC

Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)

CLK Low

CLK

RNG

DATA

LOAD

LDAC

Figure 4. LDAC Controlled Update Using 8-Bit Serial Word

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

linearity, offset, and gain error using single-end supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output

voltage may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most

negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage remains at zero until the input code value produces a sufficient positive output voltage to

overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 5. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below ground.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage. The code is

calculated from the maximum specification for the negative offset.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

equivalent inputs and outputs

INPUT CIRCUIT

OUTPUT CIRCUIT

Input from

Decoded DAC

DAC

Voltage Output

Input

ref

× 1

× 2

84 kΩ

Output

Range

Select

To DAC

Resistor

String

SINK

60 µA

Typical

GND

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Reference input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Operating free-air temperature range, T : TLV5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

+ 0.3 V

TLV5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, V

2.7

3.3

5.25

High-level input voltage, V

0.8 V

Low-level input voltage, V

0.8

Reference voltage, V [A|B|C|D], x1 gain

–1.5

ref

Load resistance, R

kΩ

Setup time, data input, t

(see Figures 1 and 2)

su(DATA-CLK)

Valid time, data input valid after CLK↓, t

(see Figures 1 and 2)

v(DATA-CLK)

Setup time, CLK eleventh falling edge to LOAD, t

(see Figure 1)

su(CLK-LOAD)

(see Figure 1)

Setup time, LOAD↑ to CLK↓, t

su(LOAD-CLK)

Pulse duration, LOAD, t

Pulse duration, LDAC, t

(see Figure 1)

(see Figure 2)

250

w(LOAD)

w(LDAC)

Setup time, LOAD↑ to LDAC↓, t

(see Figure 2)

su(LOAD-LDAC)

CLK frequency

MHz

TLV5620C

TLV5620I

Operating free-air temperature, T

°C

–40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

electrical characteristics over recommended operating free-air temperature range,

= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)

ref

PARAMETER

High-level input current

Low-level input current

Output sink current

TEST CONDITIONS

MIN

TYP

MAX

±10

UNIT

µA

V = V

V = 0 V

µA

O(sink)

O(source)

Each DAC output

Output source current

Input capacitance

Reference input capacitance

Supply current

= 3.3 V

= 3.3 V,

±10

±1

µA

Reference input current

Linearity error (end point corrected)

Differential linearity error

Zero-scale error

ref

= 1.5 V

ref

= 1.25 V, × 2 gain, See Note 1

= 1.25 V, × 2 gain, See Note 2

= 1.25 V, × 2 gain, See Note 3

= 1.25 V, × 2 gain, See Note 4

= 1.25 V, × 2 gain, See Note 5

= 1.25 V, × 2 gain, See Note 6

LSB

ref

±0.9

ref

Zero-scale error temperature coefficient

Full-scale error

ref

µV/°C

ref

±60

Full-scale error temperature coefficient

Power-supply sensitivity

±25

µV/°C

mV/V

ref

See Notes 7 and 8

PSRR

0.5

NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full-scale errors).

2. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.

Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T

) – ZSE(T

)]/V × 10 /(T

– T

min

max

min ref max

5. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.

ref

6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T

7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the V

of this signal on the zero-code output voltage.

) – FSE (T

)]/V × 10 /(T

ref max

– T

min

max

min

voltage from 4.5 V to 5.5 V dc and measuring the effect

8. Full-scale error rejection ratio (FSE-RR) is measured by varing the V

this signal on the full-scale output voltage.

voltage from 3 V to 3.6 V dc and measuring the effect of

operating characteristics over recommended operating free-air temperature range,

= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)

ref

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V/µs

µs

Output slew rate

= 100 pF

= 10 kΩ

Output settling time

To ±0.5 LSB,

= 100 pF,

= 10 kΩ, See Note 9

Large-signal bandwidth

Digital crosstalk

Measured at –3 dB point

100

–50

–60

100

kHz

CLK = 1-MHz square wave measured at DACA-DACD

Reference feedthrough

Channel-to-channel isolation

Reference input bandwidth

See Note 10

See Note 11

See Note 12

kHz

NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ± 0.5 LSB starting from

an initial output voltage equal to zero.

10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V

ref PP

at 10 kHz.

11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex

with V input = 1 V dc + 1 V at 10 kHz.

ref

12. Reference bandwidth is the –3 dB bandwidth with an input at V = 1.25 V dc + 2 V

and with a digital input code of full-scale.

ref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

PARAMETER MEASUREMENT INFORMATION

TLV5620

DACA

DACB

DACC

DACD

10 kΩ

= 100 pF

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS

POSITIVE RISE TIME AND SETTLING TIME

NEGATIVE FALL TIME AND SETTLING TIME

2.5

= 3 V

= 25°C

Code FF to

00 Hex

Range = ×2

1.5

= 1.25 V

ref

= 3 V

= 25°C

(see Note A)

0.5

Code 00 to

FF Hex

Range = ×2

ref

= 1.25 V

(see Note A)

–0.5

–1

10 12 14 16 18 20

Time – µs

NOTE A: Fall time = 4.25 µs, negative slew rate = 0.46 V/µs, settling

time = 8.5 µs.

NOTE A: Risetime=2.05µs, positiveslewrate=0.96V/µs,settling

time = 4.5 µs.

Figure 7

Figure 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

TYPICAL CHARACTERISTICS

DAC OUTPUT VOLTAGE

OUTPUT LOAD

1.6

2.8

2.6

2.4

2.2

1.4

1.2

0.8

0.6

0.4

1.8

1.6

= 3 V,

= 1.5 V,

ref

= 3 V,

= 1.5 V,

1.4

1.2

Range = 2x

ref

0.2

Range = 1x

10 20 30 40 50 60 70 80 90 100

– Output Load – kΩ

Figure 9

Figure 10

SUPPLY CURRENT

TEMPERATURE

1.2

1.15

1.1

Range = ×2

Input Code = 255

= 3 V

= 1.25 V

ref

1.05

0.95

0.9

0.85

0.8

–50

100

t – Temperature – °C

Figure 11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5620C, TLV5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS110B – JANUARY 1995 – REVISED APRIL 1997

APPLICATION INFORMATION

TLV5620

DACA

DACB

DACC

DACD

NOTE A: Resistor R

10 kΩ

Figure 12. Output Buffering Scheme

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TLV5620CD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

TLV5620C

TLV5620CDG4

TLV5620CDR

TLV5620CDRG4

TLV5620CN

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

TLV5620C

TLV5620CN

TLV5620I

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Pb-Free

(RoHS)

0 to 70

TLV5620CNE4

TLV5620ID

Pb-Free

(RoHS)

N / A for Pkg Type

0 to 70

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

TLV5620IDG4

TLV5620IDR

TLV5620IDRG4

TLV5620IN

Green (RoHS

& no Sb/Br)

TLV5620I

2500

Green (RoHS

& no Sb/Br)

TLV5620I

Green (RoHS

& no Sb/Br)

TLV5620I

Pb-Free

(RoHS)

TLV5620IN

TLV5620INE4

Pb-Free

(RoHS)

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV5620IDR

SOIC

2500

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC 14

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TLV5620IDR

2500

Pack Materials-Page 2

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regulatory requirements in connection with such use.

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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV5620CDR [TI]

相关型号：

TLV5620CDRG4

TLV5620CN

TLV5620CNE4

TLV5620I

TLV5620ID

TLV5620IDG4

TLV5620IDR

TLV5620IDRG4

TLV5620IN

TLV5620INE4

TLV5621

TLV5621ED