TLV5614IYE_技术文档

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

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FEATURES

APPLICATIONS

D

Four 12-Bit D/A Converters

D

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Controls

Machine and Motion Control Devices

Communications

D

Programmable Settling Time of Either 3 µs or

9 µs Typ

TMS320 DSP Family, (Q)SPI, and

Microwire Compatible Serial Interface

D

Internal Power-On Reset

Arbitrary Waveform Generation

D

Low Power Consumption:

−

8 mW, Slow Mode − 5-V Supply

3.6 mW, Slow Mode − 3-V Supply

WCS PACKAGE

(BOTTOM VIEW)

OUTA OUTB OUTC OUTD

D

Reference Input Buffer

Voltage Output Range . . . 2× the Reference

Input Voltage

14 13

15

12

11

10

REFINAB

REFINCD

D

Monotonic Over Temperature

AV

16

1

DD

AGND

DGND

FS

9

D

Dual 2.7-V to 5.5-V Supply (Separate Digital

and Analog Supplies)

DV

8

7

2

PD

3

4

5

6

D

Hardware Power Down (10 nA)

Software Power Down (10 nA)

Simultaneous Update

LDAC DIN

SCLK CS

DESCRIPTION

The TLV5614IYE is a quadruple 12-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial

interface. The serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5614IYE

is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 12-bit DAC value.

The device has provision for two supplies: one digital supply for the serial interface (via pins DV and DGND), and one

DD

for the DACs, reference buffers, and output buffers (via pins AV and AGND). Each supply is independent of the other,

DD

and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC is controlled

via a microprocessor operating on a 3 V supply (also used on pins DV and DGND), with the DACs operating on a 5 V

DD

supply. Of course, the digital and analog supplies can be tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output

stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for

single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize

speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A

high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source

impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then

DACs C and D.

The TLV5614IYE is implemented with a CMOS process and is available in a 16-terminal WCS package. The TLV5614IYE

is characterized for operation from −40°C to 85°C in a wire-bonded small outline (SOIC) package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 DSP is a trademark of Texas Instruments.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

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ꢛꢣ ꢢ ꢮꢩꢨ ꢦ ꢟꢢ ꢠ ꢫꢣ ꢢ ꢨ ꢪ ꢧ ꢧ ꢟꢠ ꢳ ꢮꢢ ꢪ ꢧ ꢠꢢꢦ ꢠꢪ ꢨꢪ ꢧꢧ ꢥꢣ ꢟꢭ ꢲ ꢟꢠꢨ ꢭꢩꢮ ꢪ ꢦꢪ ꢧꢦꢟ ꢠꢳ ꢢꢡ ꢥꢭ ꢭ ꢫꢥ ꢣ ꢥꢤ ꢪꢦꢪ ꢣ ꢧꢋ

Copyright  2003, Texas Instruments Incorporated

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These devices have limited built-in ESD protection. The device should be placed in conductive foam during storage or handling to

prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

T

A

WCS(1)

(YE)

−40°C to 85°C

TLV5614IYE

(1)

Wafer chip scale package. See Figure 17.

FUNCTIONAL BLOCK DIAGRAM

AV

16

DV

1

DD

15

REFINAB

DAC A

+

_

Power-On

Reset

+

_

14

OUTA

10

12

12-Bit

DAC

Latch

14-Bit

Data

and

2

Control

Register

2-Bit

Control

Data

2

14

Serial

Input

Register

4

Power-Down/

Speed Control

DIN

Latch

2

7

DAC Select/

Control

FS

SCLK

CS

5

6

13

12

11

OUTB

OUTC

OUTD

DAC B

Logic

DAC C

DAC D

10

REFINCD

3

2

9

8

PD

AGND

DGND

LDAC

2

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TERMINAL

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

Terminal Functions

I/O

DESCRIPTION

NAME

AGND

AV

NO.

9

16

6

Analog ground

Analog supply

DD

CS

I

Chip select. This terminal is active low.

Digital ground

DGND

DIN

8

4

Serial data input

DV

1

Digital supply

DD

7

I

Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the

TLV5614IYE.

FS

2

3

Power down pin. Powers down all DACs (overriding their individual power down settings), and all output stages. This

terminal is active low.

PD

Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the

serial interface. The DAC outputs are only updated when LDAC is low.

LDAC

REFINAB

REFINCD

SCLK

15

10

5

I

Voltage reference input for DACs A and B.

Voltage reference input for DACs C and D.

Serial clock input

I

OUTA

14

13

12

11

O

DACA output

OUTB

DACB output

OUTC

DACC output

OUTD

DACD output

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

7 V

Supply voltage, (DV , AV

DD DD

to GND)

to DV

Supply voltage difference, (AV

)

DD

−2.8 V to 2.8 V

DD

Digital input voltage range

−0.3 V to DV

+ 0.3 V

DD

Reference input voltage range

−0.3 V to AV

+ 0.3 V

DD

Operating free-air temperature range, T

−40°C to 85°C

A

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

5.5

UNIT

5-V supply

3-V supply

4.5

2.7

2

5

3

Supply voltage, AV , DV

DD DD

V

3.3

DV

= 2.7 V

= 5.5 V

= 2.7 V

= 5.5 V

DD

High-level digital input voltage, V

IH

V

2.4

0.6

1

Low-level digital input voltage, V

IL

(1)

5-V supply

3-V supply

0

2

2.048

1.024

10

V

−1.5

DD

Reference voltage, V to REFINAB, REFINCD terminal

ref

(1)

−1.5

DD

Load resistance, R

kΩ

pF

L

Load capacitance, C

100

20

L

Serial clock rate, SCLK

MHz

Operating free-air temperature

TLV5614IYE

−40

85

°C

(1)

Voltages greater than AV /2 cause output saturation for large DAC codes.

DD

3

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ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

STATIC DAC SPECIFICATIONS

PARAMETER

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

12

Integral nonlinearity (INL), end point adjusted

Differential nonlinearity (DNL)

See Note 1

1.5

0.5

4

1

LSB

See Note 2

See Note 3

See Note 4

LSB

E

Zero scale error (offset error at zero scale)

Zero scale error temperature coefficient

12

mV

ZS

10

ppm/°C

% of FS

voltage

Gain error

See Note 5

See Note 6

0.6

G

Gain error temperature coefficient

Zero scale

10

−80

ppm/°C

dB

PSRR

Power supply rejection ratio

See Notes 7 and 8

Full scale

dB

INDIVIDUAL DAC OUTPUT SPECIFICATIONS

V

Voltage output range

R

= 10 kΩ

0

AV −0.4

DD

V

O

L

% of FS

voltage

Output load regulation accuracy

= 2 kΩ vs 10 kΩ

0.1

0.25

L

REFERENCE INPUTS (REFINAB, REFINCD)

V

I

Input voltage range

Input resistance

See Note 9

AV −1.5

DD

V

R

10

5

MΩ

pF

I

C

Input capacitance

REFIN = 1 V at 1 kHz + 1.024 V dc

pp

Reference feed through

−75

dB

(see Note 10)

Slow

0.5

1

REFIN = 0.2 V + 1.024 V dc

pp

Reference input bandwidth

MHz

large signal

Fast

DIGITAL INPUTS (DIN, CS, LDAC, PD

I

High-level digital input current

Low-level digital input current

Input capacitance

V = V

DD

1

µA

pF

IH

I

V = 0 V

I

IL

C

3

I

POWER SUPPLY

5-V supply, No load,

Clock running,

Slow

Fast

Slow

Fast

1.6

3.8

1.2

3.2

10

2.4

5.6

1.8

4.8

mA

All inputs 0 V or V

DD

I

Power supply current

DD

3-V supply, No load,

Clock running,

mA

nA

All inputs 0 V or DV

DD

Power down supply current (see Figure 12)

(1)

(2)

The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line

between zero and full scale excluding the effects of zero code and full-scale errors.

The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal

1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)

as a change in the digital input code.

(3)

(4)

(5)

(6)

(7)

Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

6

Zero-scale-error temperature coefficient is given by: E

TC = [E

(T

) − E (T )]/V × 10 /(T

ZS min ref max

− T ).

min

ZS

ZS max

Gain error is the deviation from the ideal output (2 V − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

ref

G

6

Gain temperature coefficient is given by: E TC = [E (T

) − E (T

)]/V × 10 /(T

DD

− T ).

G

max

G

min ref

max

min

Zero-scale-error rejection ratio (EZS−RR) is measured by varying the AV

this signal imposed on the zero-code output voltage.

from 5 0.5 V and 3 0.3 V dc, and measuring the proportion of

(8)

Full-scale rejection ratio (EG-RR) is measured by varying the AV

from 5 0.5 V and 3 0.3 V dc and measuring the proportion of this signal

imposed on the full-scale output voltage after subtracting the zero scale change.

DD

(9)

(10)

Reference input voltages greater than V /2 cause output saturation for large DAC codes

DD

Referencefeedthrough is measured at the DAC output with an input code = 000 hex and a V

at 1 kHz.

input = 1.024 Vdc + 1 V

pp

ref (REFINABor REFINCD)

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER

TEST CONDITIONS

MIN

TYP

5

MAX

UNIT

V/µs

Fast

Slow

Fast

Slow

Fast

Slow

C

V

= 100 pF, R = 10 kΩ,

L

O

L

SR

Output slew rate

= 10% to 90%, V = 2.048 V, 1024 V

1

ref

3

5.5

20

To 0.5 LSB, C = 100 pF,

L

t

Output settling time

µs

s

R

L

= 10 kΩ, See Notes 1 and 3

9

1

Output settling time, code to To 0.5 LSB, C = 100 pF, R = 10 kΩ,

code

L

µs

s(c)

See Note 2

2

Glitch energy

Code transition from 7FF to 800

10

74

66

−68

nV-sec

SNR

Signal-to-noise ratio

Signal to noise + distortion

Total harmonic distortion

Sinewave generated by DAC,

Reference voltage = 1.024 at 3 V and 2.048 at 5 V,

S/(N+D)

THD

dB

f = 400 KSPS, f

= 1.1 kHz sinewave, C = 100 pF,

s

OUT

L

Spurious free dynamic

range

R

L

= 10 kΩ, BW = 20 kHz

SFDR

70

DIGITAL INPUT TIMING REQUIREMENTS

t

Setup time, CS low before FS↓

Setup time, FS low before first negative SCLK edge

10

8

ns

su(CS−FS)

su(FS−CK)

Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before

rising edge of FS

t

10

ns

su(C16−FS)

Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS

is used instead of the SCLK positive edge to update the DAC, then the setup time is

between the FS rising edge and CS rising edge.

su(C16−CS)

t

Pulse duration, SCLK high

25

8

ns

wH

Pulse duration, SCLK low

wL

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

Pulse duration, FS high

su(D)

h(D)

wH(FS)

5

20

(1)

Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change ofFFF hex to

080 hex for 080 hex to FFF hex.

(2)

(3)

Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count.

Limits are ensured by design and characterization, but are not production tested.

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PARAMETER MEASUREMENT INFORMATION

t

wH

wL

SCLK

DIN

1

2

3

4

5

15

16

t

su(D)

h(D)

D14

D15

D13

D12

D1

D0

t

su(FS-CK)

t

su(C16-CS)

t

su(CS-FS)

CS

FS

t

wH(FS)

t

su(C16-FS)

Figure 1. Timing Diagram

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TYPICAL CHARACTERISTICS

LOAD REGULATION

0.2

0.35

0.30

0.25

V

= 3 V,

= 1 V,

= Full Scale

V

= 5 V,

= 2 V,

DD

0.18

0.16

0.14

0.12

0.10

0.08

ref

V = Full Scale

O

V

O

3 V Slow Mode, Sink

3 V Fast Mode, Sink

5 V Slow Mode, Sink

5 V Fast Mode, Sink

0.20

0.15

0.10

0.06

0.04

0.02

0

0.05

0

0.01 0.02 0.05 0.1 0.2 0.5 0.8

Load Current − mA

1

2

0

0.02 0.04 0.1 0.2 0.4 0.8

Load Current − mA

1

2

4

Figure 2

Figure 3

LOAD REGULATION

3 V Slow Mode, Source

4.01

2.0015

2.001

5 V Slow Mode, Source

5 V Fast Mode, Source

4.005

2.0005

2.000

3 V Fast Mode, Source

4

1.9995

1.999

3.995

1.9985

1.998

3.99

V

= 5 V,

= 2 V,

= Full Scale

1.9975

V

= 3 V,

= 1 V,

= Full Scale

DD

V

ref

1.997

V

O

V

O

3.985

1.9965

0

0.02 0.04 0.1 0.2 0.4 0.8

Load Current − mA

1

2

4

0

0.01 0.02 0.05 0.1 0.2 0.5 0.8

Load Current − mA

1

2

Figure 4

Figure 5

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SUPPLY CURRENT

vs

SUPPLY CURRENT

vs

TEMPERATURE

4

V

= 3 V,

= 1.024 V,

Full Scale

DD

ref

3.5

3

3.5

V

O

Fast Mode

(Worst Case For I

)

DD

Fast Mode

3

V

= 5 V,

= 1.024 V,

Full Scale

2.5

DD

2.5

ref

V

O

2

(Worst Case For I )

DD

1.5

1

Slow Mode

20

Slow Mode

0.5

−40

0.5

−40

−20

0

40

60

80

100

−20

0

20

40

60

80

100

T − Temperature − °C

Figure 6

Figure 7

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

V

= 1 V dc + 1 V p/p Sinewave,

ref

V

= 1 V dc + 1 V p/p Sinewave,

ref

−10

Output Full Scale

−10

Output Full Scale

−20

−30

−20

−30

−−40

−50

−60

−50

−60

Fast Mode

Slow Mode

20

−70

−80

−70

−80

0

5

10

20

30

50

100

0

5

10

30

50

100

f − Frequency − kHz

Figure 8

Figure 9

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TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

0

−10

V

= 1 V dc + 1 V p/p Sinewave,

V

= 1 V dc + 1 V p/p Sinewave,

ref

Output Full Scale

−10

Output Full Scale

−20

−30

−20

−30

−−40

−50

−60

Fast Mode

Slow Mode

−60

−70

−80

−70

−80

0

5

10

20

30

50

100

0

5

10

20

30

50

100

f − Frequency − kHz

Figure 10

Figure 11

SUPPLY CURRENT

vs

TIME

(WHEN ENTERING POWER-DOWN MODE)

4000

3500

3000

2500

2000

1500

1000

500

0

200

400

600

800

1000

t − Time − ns

Figure 12

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DIFFERENTIAL NONLINEARITY

0.3

V

CC

= 5 V, V = 2 V, SCLK = 1 MHz)

ref

0.25

0.2

0.15

0.1

0.05

0

−0.05

−0.1

−0.15

−0.2

−0.25

−0.3

0

256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096

Digital Code

Figure 13

INTEGRAL NONLINEARITY

1

V

= 5 V, V = 2 V,

ref

CC

SCLK = 1 MHz

0.5

0

−0.5

−1

−1.5

0

256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096

Digital Code

Figure 14

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APPLICATION INFORMATION

GENERAL FUNCTION

The TLV5614IYE is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial

interface, speed and power down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by external reference) is given by:

CODE

2

2 REF

[V]

n

where REF is the reference voltage and CODE is the digital input value within the range of 0 to 2 −1, where n=12

10

(bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section.

A power-on reset initially resets the internal latches to a defined state (all bits zero).

SERIAL INTERFACE

Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts

shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits

have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the

voltage output to the new level.

The serial interface of the TLV5614IYE can be used in two basic modes:

D

Four wire (with chip select)

Three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the

data source (DSP or microcontroller). The interface is compatible with the TMS320 DSP family. Figure 15 shows

an example with two TLV5614IYEs connected directly to a TMS320 DSP.

TLV5614IYE

CS FS DIN SCLK

TMS320

DSP

XF0

XF1

FSX

DX

CLKX

Figure 15. TMS320 Interface

TMS320 is a trademark of Texas Instruments.

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If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an

example of how to connect the TLV5614IYE to a TMS320, SPI, or Microwire port using only three pins.

TMS320

DSP

TLV5614IYE

SPI

TLV5614IYE

Microwire

TLV5614I

YE

FSX

FS

SS

FS

I/O

FS

DIN

DX

MOSI

SCLK

SO

SK

CLKX

SCLK

CS

Figure 16. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge

on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed

to program the TLV5614IYE. After the write operation(s), the DAC output is updated automatically on the next positive

clock edge following the sixteenth falling clock edge.

SERIAL CLOCK FREQUENCY AND UPDATE RATE

The maximum serial clock frequency is given by:

1

f

+

+ 20 MHz

SCLKmax

t

) t

wH(min)

wL(min)

The maximum update rate is:

1

f

+

+ 1.25 MHz

UPDATEmax

₁₆ǒ_t

Ǔ

) t

wH(min)

wL(min)

Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the

TLV5614IYE has to be considered also.

DATA FORMAT

The 16-bit data word for the TLV5614IYE consists of two parts:

D

Control bits

(D15 . . . D12)

(D11 . . . D0)

New DAC value

D15

A1

D14

A0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PWR

SPD

New DAC value (12 bits)

X: don’t care

SPD: Speed control bit.

PWR: Power control bit.

1 → fast mode

1 → power down

0 → slow mode

0 → normal operation

In power-down mode, all amplifiers within the TLV5614IYE are disabled. A particular DAC (A, B, C, D) of the

TLV5614IYE is selected by A1 and A0 within the input word.

A1

0

A0

0

DAC

A

0

1

B

1

0

C

1

D

12

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

USING TLV5614IYE, WAFER CHIP SCALE PACKAGE (WCSP)

D

TLV5614 DIE qualification was done using a wire-bonded small outline (SOIC) package and includes: steady

state life, thermal shock, ESD, latch-up, and characterization. This qualified device is orderable as TLV5614ID.

The wafer chip-scale package (WCS), TLV5614IYE, uses the same DIE as TLV5614ID, but is not qualified. WCS

qualification, including board level reliability (BLR), is the responsibility of the customer.

It is recommended that underfill be used for increased reliability. BLR is application dependent, but may include

test such as: temperature cycling, drop test, key push, bend, vibration, and package shear.

The following WCSP information provides the user of the TLV5614IYE with some general guidelines for board

assembly.

D

Melting point of eutectic solder is 183°C.

Recommended peak reflow temperatures are in the 220°C to 230°C range.

The use of underfill is required. The use of underfill greatly reduces the risk of thermal mismatch fails.

Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board level/system

level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The epoxy adheres to

the body of the device and to the printed-circuit board. It reduces stress placed upon the solder joints due to the

thermal coefficient of expansion (TCE) mismatch between the board and the component. Underfill material is highly

filled with silica or other fillers to increase an epoxy’s modulus, reduce creep sensitivity, and decrease the material’s

TCE.

The recommendation for peak flow temperatures of 220°C to 230°C is based on general empirical results that indicate

that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or circuit board

pad. Lower peak temperatures may cause nonwets (cold solder joints).

Bottom View

Top View

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

Figure 17. TLV5614IYE Wafer Chip Scale Package

13

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

TLV5614IYE INTERFACED TO TMS320C203 DSP

Hardware Interfacing

Figure 18 shows an example of how to connect the TLV5614IYE to a TMS320C203 DSP. The serial port is configured

in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the TLV5614IYE.

Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose input/output port

bits IO0 and IO1 are used to generate the chip select (CS) and DAC latch update (LDAC) inputs to the TLV5614IYE.

The active low power down (PD) is pulled high all the time to ensure the DACs are enabled.

TMS320C203

TLV5614IYE

SDIN

V

DX

DD

PD

SCLK

FS

CLKX

FSX

I/O 0

I/O 1

CS

VOUTA

VOUTB

VOUTC

VOUTD

LDAC

REFINAB

REFINCD

REF

V

SS

Figure 18. TLV5614IYE Interfaced With TMS320C203

Software

The application example outputs a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and its

quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses

LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The samples

are stored in a look-up table, which describes two full periods of a sine wave.

The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS pulse

preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the tsu(C16−FS)

timing requirement occurs. To avoid this, the program waits until the transmission of the previous word has been

completed.

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Processor: TMS320C203 runnning at 40 MHz

;

; Description:

;

; This program generates a differential in−phase (sine) on (OUTA−OUTB) and it’s quadrature

(cosine) as a differential signal on (OUTC−OUTD).

;

; The DAC codes for the signal samples are stored as a table of 64 12−bit values, describing

; 2 periods of a sine function. A rolling pointer is used to address the table location in

; the first period of this waveform, from which the DAC A samples are read. The samples for

; the other 3 DACs are read at an offset to this rolling pointer

;

DAC

A

Function

sine

Offset from rolling pointer

0

B

inverse sine 16

C

D

cosine

inverse cosine24

8

; The on−chip timer is used to generate interrupts at a fixed rate. The interrupt service

; routine first pulses LDAC low to update all DACs simultaneously with the values which

; were written to them in the previous interrupt. Then all 4 DAC values are fetched and

; written out through the synchronous serial interface. Finally, the rolling pointer is

; incremented to address the next sample, ready for the next interrupt.

;  1998, Texas Instruments Inc.

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

14

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ

SLAS391A − JULY 2003 − REVISED AUGUST 2003

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−I/O and memory mapped regs −−−−−−−−−−−−−−−−−−−−−−−−−−−−−

.include ”regs.asm”

;−−−−−−−jump vectors −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

.ps

b

0h

start

int1

int23

timer_isr;

b

−−−−−−−−−−− variables −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

temp

.equ

0060h

0061h

0062h

0063h

0064h

0065h

0066h

r_ptr

iosr_stat

DACa_ptr

DACb_ptr

DACc_ptr

DACd_ptr

;−−−−−−−−−−−constants−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; DAC control bits to be OR’ed onto data

; all fast mode

DACa_control .equ

DACb_control .equ

DACc_control .equ

DACd_control .equ

01000h

05000h

09000h

0d000h

;−−−−−−−−−−− tables −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

.ds

sinevals

02000h

.word 00800h

.word 0097Ch

.word 00AE9h

.word 00C3Ah

.word 00D61h

.word 00E53h

.word 00F07h

.word 00F76h

.word 00F9Ch

.word 00F76h

.word 00F07h

.word 00E53h

.word 00D61h

.word 00C3Ah

.word 00AE9h

.word 0097Ch

.word 00800h

.word 00684h

.word 00517h

.word 003C6h

.word 0029Fh

.word 001ADh

.word 000F9h

.word 0008Ah

.word 00064h

.word 0008Ah

.word 000F9h

.word 001ADh

.word 0029Fh

.word 003C6h

.word 00517h

.word 00684h

.word 00800h

.word 0097Ch

.word 00AE9h

.word 00C3Ah

.word 00D61h

.word 00E53h

.word 00F07h

.word 00F76h

.word 00F9Ch

.word 00F76h

.word 00F07h

.word 00E53h

.word 00D61h

.word 00C3Ah

.word 00AE9h

15

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

.word 0097Ch

.word 00800h

.word 00684h

.word 00517h

.word 003C6h

.word 0029Fh

.word 001ADh

.word 000F9h

.word 0008Ah

.word 00064h

.word 0008Ah

.word 000F9h

.word 001ADh

.word 0029Fh

.word 003C6h

.word 00517h

.word 00684h

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Main Program

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

.ps

.entry

1000h

start

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; disable interrupts

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

setc

splk

INTM

; disable maskable interrupts

#0ffffh, IFR; clear all interrupts

#0004h, IMR; timer interrupts unmasked

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; set up the timer

; timer period set by values in PRD and TDDR

; period = (CLKOUT1 period) x (1+PRD) x (1+TDDR)

; examples for TMS320C203 with 40MHz main clock

; Timer rate

TDDR

9

PRD

24 (18h)

39 (27h)

;

80 kHz

50 kHz

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

prd_val.equ

tcr_val.equ

splk

0018h

0029h

#0000h, temp; clear timer

out

temp, TIM

splk

#prd_val, temp; set PRD

out

temp, PRD

splk

#tcr_val, temp; set TDDR, and TRB=1 for auto−reload

temp, TCR

out

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Configure IO0/1 as outputs to be :

; IO0 CS − and set high

; IO1 LDAC

− and set high

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

in

lacl

or

sacl

out

in

lacl

or

sacl

out

temp, ASPCR; configure as output

temp

#0003h

temp

temp, ASPCR

temp, IOSR; set them high

temp

#0003h

temp

temp, IOSR

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; set up serial port for

; SSPCR.TXM=1

; SSPCR.MCM=1

; SSPCR.FSM=1

Transmit mode − generate FSX

Clock mode − internal clock source

Burst mode

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

splk

out

splk

out

#0000Eh, temp

temp, SSPCR; reset transmitter

#0002Eh, temp

temp,SSPCR

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

16

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ

SLAS391A − JULY 2003 − REVISED AUGUST 2003

; reset the rolling pointer

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

lacl

sacl

#000h

r_ptr

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; enable interrupts

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

clrc

INTM

; enable maskable interrupts

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; loop forever!

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

b

;wait for interrupt

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

;all else fails stop here

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

done

b

done

;hang there

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Interrupt Service Routines

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

int1

ret

; do nothing and return

int23 ret

timer_isr:

in

iosr_stat, IOSR; store IOSR value into variable space

lacl

and

sacl

out

or

sacl

out

and

sacl

out

lacl

add

sacl

add

iosr_stat

#0FFFDh

temp

temp, IOSR;

#0002h

; load acc with iosr status

; reset IO1 − LDAC low

;

; set IO1 − LDAC high

;

temp

temp, IOSR;

#0FFFEh

temp

temp, IOSR;

r_ptr

#sinevals

DACa_ptr

#08h

; reset IO0 − CS low

;

; load rolling pointer to accumulator

; add pointer to table start

; to get a pointer for next DAC a sample

; add 8 to get to DAC C pointer

sacl

add

sacl

add

sacl

mar

DACc_ptr

#08h

DACb_ptr

#08h

DACd_ptr

*,ar0

; add 8 to get to DAC B pointer

; add 8 to get to DAC D pointer

; set ar0 as current AR

; DAC A

lar

ar0, DACa_ptr; ar0 points to DAC a sample

; get DAC a sample into accumulator

#DACa_control; OR in DAC A control bits

temp

temp, SDTR; send data

lacl

or

*

sacl

out

;

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−;

We must wait for transmission to complete before writing next word to the SDTR.;

TLV5614/04 interface does not allow the use of burst mode with the full packet; rate, as

we need a CLKX −ve edge to clock in last bit before FS goes high again,; to allow SPI

compatibility.

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

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SLAS391A − JULY 2003 − REVISED AUGUST 2003

rpt

nop

#016h

; wait long enough for this configuration

; of MCLK/CLKOUT1 rate

; DAC B

lar

ar0, dacb_ptr; ar0 points to DAC a sample

; get DAC a sample into accumulator

#DACb_control; OR in DAC B control bits

temp

temp, SDTR; send data

#016h ; wait long enough for this configuration

; of MCLK/CLKOUT1 rate

lacl

or

*

sacl

out

rpt

nop

;

; DAC C

lar

ar0, dacc_ptr; ar0 points to dac a sample

; get DAC a sample into accumulator

#DACc_control; OR in DAC C control bits

temp

temp, SDTR; send data

#016h ; wait long enough for this configuration

; of MCLK/CLKOUT1 rate

lacl

or

sacl

out

rpt

nop

*

;

; DAC D

lar

ar0, dacd_ptr; ar0 points to DAC a sample

; get DAC a sample into accumulator

lacl

or

*

#dacd_control; OR in DAC D control bits

temp

temp, SDTR; send data

sacl

out

;

lacl

add

r_ptr

#1h

#001Fh

r_ptr

#016h

; load rolling pointer to accumulator

; increment rolling pointer

; count 0−31 then wrap back round

; store rolling pointer

and

sacl

rpt

nop

; wait long enough for this configuration

; of MCLK/CLKOUT1 rate

; now take CS high again

lacl

or

iosr_stat

#0001h

; load acc with iosr status

; set IO0 − CS high

;

sacl

out

clrc

ret

temp

temp, IOSR;

intm

; re-enable interrupts

; return from interrupt

.end

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SLAS391A − JULY 2003 − REVISED AUGUST 2003



TLV5614IYE INTERFACED TO MCS 51 MICROCONTROLLER

Hardware Interfacing



Figure 19 shows an example of how to connect the TLV5614IYE to an MCS 51 Microcontroller. The serial DAC input

data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with

the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the DAC latch update

(LDAC), chip select (CS) and frame sync (FS) signals for the TLV5614IYE. The active low power down pin (PD) of

the TLV5614IYE is pulled high to ensure that the DACs are enabled.

MCS 51

TLV5614IYE

SDIN

V

RxD

DD

PD

SCLK

LDAC

CS

TxD

P3.3

P3.4

VOUTA

VOUTB

VOUTC

VOUTD

FS

REFINAB

REFINCD

REF

V

SS



Figure 19. TLV5614IYE Interfaced With MCS 51

Software



The example is the same as for the TMS320C203 in this data sheet, but adapted for a MCS 51 controller. It

generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and its quadrature (cosine)

signal is the differential signal between VOUTC and VOUTD.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses

LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The samples

are stored as a look-up table, which describes one full period of a sine wave.

The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a

synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the

TLV5614IYE. The CS and FS signals are provided in the required fashion through control of IO port 3, which has

bit addressable outputs.

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Processor: 80C51

;

; Description:

;

; This program generates a differential in-phase

(sine) on (OUTA−OUTB) ; and it’s quadrature (cosine)

as a differential signal on (OUTC−OUTD).

;

;  1998, Texas Instruments Inc.

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

NAME

MAIN

ISR

SINTBL SEGMENT

VAR1 SEGMENT

STACK SEGMENT

GENIQ

SEGMENT

CODE

DATA

IDATA

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Code start at address 0, jump to start

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

CSEG AT

LJMP start

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

0

; Execution starts at address 0 on power−up.

19

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ꢃ

ꢄ

ꢅꢆ

ꢇ

ꢈ

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www.ti.com

SLAS391A − JULY 2003 − REVISED AUGUST 2003

; Code in the timer0 interrupt vector

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

CSEG AT

0BH

LJMP timer0isr

; Jump vector for timer 0 interrupt is 000Bh

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Global variables need space allocated

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

RSEG

VAR1

DS

temp_ptr:

1

rolling_ptr: DS

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Interrupt service routine for timer 0 interrupts

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

RSEG

timer0isr:

PUSH

ISR

PSW

ACC

INT1

PUSH

CLR

SETB

; pulse LDAC low

; to latch all 4 previous values at the same time

; 1st thing done in timer isr => fixed period

; set CS low

CLR

T0

; The signal to be output on each DAC is a sine function. One cycle of a sine wave is

; held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes).

; We have ; one pointer which rolls round this table, rolling_ptr incrementing by

; 2 bytes (1 sample) on each interrupt (at the end of this routine).

; The DAC samples are read at an offset to this rolling pointer:

; DAC Function Offset from rolling_ptr

;

MOV

MOVC

A

B

C

D

sine

0

inverse sine 32

cosine

inverse cosine48

16

DPTR,#sinevals; set DPTR to the start of the table of sine signal values

R7,rolling_ptr; R7 holds the pointer into the sine table

A,R7

A,@A+DPTR

; get DAC A msb

; msb of DAC A is in the ACC

CLR

MOV

T1

SBUF,A

; transmit it − set FS low

; send it out the serial port

INC

R7

; increment the pointer in R7

; to get the next byte from the table

; which is the lsb of this sample, now in ACC

MOV

A,R7

MOVC

A_MSB_TX:

JNB

CLR

MOV

A,@A+DPTR

TI,A_MSB_TX ; wait for transmit to complete

TI

SBUF,A

; clear for new transmit

; and send out the lsb of DAC A

; DAC C next

; DAC C codes should be taken from 16 bytes (8 samples) further on

; in the sine table − this gives a cosine function

MOV

ADD

ANL

MOV

A,R7

; pointer in R7

A,#0FH

; add 15 − already done one INC

; wrap back round to 0 if > 64

; pointer back in R7

A,#03FH

R7,A

MOVC

ORL

A,@A+DPTR

A,#01H

; get DAC C msb from the table

; set control bits to DAC C address

A_LSB_TX:

JNB

TI,A_LSB_TX ; wait for DAC A lsb transmit to complete

SETB

CLRT1

CLR

T1

; toggle FS

TI

; clear for new transmit

; and send out the msb of DAC C

; increment the pointer in R7

; to get the next byte from the table

; which is the lsb of this sample, now in ACC

MOV

SBUF,A

R7

INC

MOV

A,R7

MOVC

C_MSB_TX:

JNB

A,@A+DPTR

TI,C_MSB_TX ; wait for transmit to complete

CLR

MOV

TI

SBUF,A

; clear for new transmit

; and send out the lsb of DAC C

20

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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ

SLAS391A − JULY 2003 − REVISED AUGUST 2003

; DAC B next

; DAC B codes should be taken from 16 bytes (8 samples) further on

; in the sine table − this gives an inverted sine function

MOV

ADD

ANL

MOV

A,R7

; pointer in R7

A,#0FH

; add 15 − already done one INC

; wrap back round to 0 if > 64

; pointer back in R7

A,#03FH

R7,A

MOVC

ORL

A,@A+DPTR

A,#02H

; get DAC B msb from the table

; set control bits to DAC B address

C_LSB_TX:

JNB

TI,C_LSB_TX ; wait for DAC C lsb transmit to complete

SETB

CLR

T1

; toggle FS

T1

CLR

MOV

TI

SBUF,A

; clear for new transmit

; and send out the msb of DAC B

; get DAC B LSB

INC

R7

; increment the pointer in R7

; to get the next byte from the table

; which is the lsb of this sample, now in ACC

MOV

A,R7

A,@A+DPTR

MOVC

B_MSB_TX:

JNB

TI,B_MSB_TX ; wait for transmit to complete

CLR

TI

; clear for new transmit

MOV

SBUF,A

; and send out the lsb of DAC B

; DAC D next

; DAC D codes should be taken from 16 bytes (8 samples) further on

; in the sine table − this gives an inverted cosine function

MOV

ADD

ANL

MOV

MOVC

ORL

A,R7

; pointer in R7

A,#0FH

; add 15 − already done one INC

; wrap back round to 0 if > 64

; pointer back in R7

A,#03FH

R7,A

A,@A+DPTR

A,#03H

; get DAC D msb from the table

; set control bits to DAC D address

B_LSB_TX:

JNB

TI,B_LSB_TX ; wait for DAC B lsb transmit to complete

SETB

CLR

T1

; toggle FS

CLR

TI ; clear for new transmit

MOV

SBUF,A

; and send out the msb of DAC D

INC

R7

; increment the pointer in R7

; to get the next byte from the table

; which is the lsb of this sample, now in ACC

MOV

A,R7

MOVC

A,@A+DPTR

D_MSB_TX:

JNB

TI,D_MSB_TX ; wait for transmit to complete

CLR

TI

; clear for new transmit

MOV

SBUF,A

; and send out the lsb of DAC D

; increment the rolling pointer to point to the next sample

; ready for the next interrupt

MOV

ADD

A,rolling_ptr

A,#02H

; add 2 to the rolling pointer

; wrap back round to 0 if > 64

ANL

A,#03FH

MOV

rolling_ptr,A; store in memory again

D_LSB_TX:

JNB

TI,D_LSB_TX ; wait for DAC D lsb transmit to complete

CLR

TI

; clear for next transmit

; FS high

SETB

POP

RETI

T1

T0

; CS high

ACC

PSW

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Stack needs definition

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

RSEG STACK

DS

10h

; 16 Byte Stack!

21

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www.ti.com

SLAS391A − JULY 2003 − REVISED AUGUST 2003

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Main program code

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

RSEG

start:

MAIN

MOV

CLRA

MOV

SETB

MOV

SP,#STACK−1 ; first set Stack Pointer

SCON,A

TMOD,#02H

TH0,#038H

INT1

; set serial port 0 to mode 0

; set timer 0 to mode 2 − auto−reload

; set TH0 for 5kHs interrupts

; set LDAC = 1

T1

; set FS = 1

T0

; set CS = 1

; enable timer 0 interrupts

; enable all interrupts

ET0

EA

rolling_ptr,A; set rolling pointer to 0

SETB

always:

SJMP

RET

TR0

; start timer 0

; while(1) !

always

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

; Table of 32 sine wave samples used as DAC data

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

RSEG

SINTBL

sinevals:

DW

01000H

0903EH

05097H

0305CH

0B086H

070CAH

0F0E0H

0F06EH

0F039H

0F06EH

0F0E0H

070CAH

0B086H

0305CH

05097H

0903EH

01000H

06021H

0A0E8H

0C063H

040F9H

080B5H

0009FH

00051H

00026H

00051H

0009FH

080B5H

040F9H

0C063H

0A0E8H

DW 06021H

END

22

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型号：	TLV5614IYE
厂家：	TEXAS INSTRUMENTS
描述：	2.7-V TO 5.5-V, 12-BIT QUAD DAC IN WAFER CHIP SCALE PACKAGE 2.7 V至5.5 V， 12位四DAC晶圆芯片级封装转换器数模转换器
文件：	总24页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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