TLV5614IYZ [TI]
12-Bit, Quad Channel, 2.7V to 5.5V, DAC in Bumped Die (Wafer Chip Scale) PackageâPb-Free/Green; 12位，四通道， 2.7V至5.5V ， DAC的凸点芯片（晶圆级芯片）包 - ????无铅/绿色
| 型号： | TLV5614IYZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, Quad Channel, 2.7V to 5.5V, DAC in Bumped Die (Wafer Chip Scale) PackageâPb-Free/Green |
| 文件： | 总25页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
12-Bit, Quad Channel, 2.7V to 5.5V, DAC in
Bumped Die (Wafer Chip Scale) Package—Pb-Free/Green
FEATURES
APPLICATIONS
•
•
•
•
•
•
Battery-Powered Test Instruments
Digital Offset and Gain Adjustment
Industrial Process Controls
Machine and Motion Control Devices
Communications
•
Four 12-Bit D/A Converters
•
Programmable Settling Time of Either 3µs or
9µs Typ
•
TMS320™DSP Family, (Q)SPI™, and
Microwire™ Compatible Serial Interface
Arbitrary Waveform Generation
•
•
Internal Power-On Reset
Low Power Consumption:
BUMPED DIE
(BOTTOM VIEW)
–
–
8mW, Slow Mode; 5V Supply
3.6mW, Slow Mode; 3V Supply
OUTA OUTB OUTC OUTD
•
•
Reference Input Buffer
14 13
15
12
11
10
Voltage Output Range . . . 2x Reference Input
Voltage
REFINAB
REFINCD
AV
16
1
AGND
DGND
FS
9
DD
•
•
Monotonic Over Temperature
DVDD
PD
8
7
Dual 2.7V to 5.5V Supply (Separate Digital and
Analog Supplies)
2
34
5
6
•
•
•
Hardware Power-Down (10nA)
Software Power-Down (10nA)
Simultaneous Update
LDAC DIN
SCLK CS
DESCRIPTION
The TLV5614IYZ is a quadruple, 12-bit, voltage output digital-to-analog converter (DAC) with a flexible 4-wire
serial interface. The serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports.
The TLV5614IYZ is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control
bits, and a 12-bit DAC value. The device has provision for two supplies: one digital supply for the serial interface
(via pins DVDD and DGND), and one for the DACs, reference buffers, and output buffers (via pins AVDD and
AGND). Each supply is independent of the other, and can be any value between 2.7V and 5.5V. The dual
supplies allow a typical application where the DAC is controlled via a microprocessor operating on a 3V supply
(also used on pins DVDD and DGND) with the DACs operating on a 5V supply. Of course, the digital and analog
supplies can also be tied together.
The resistor string output voltage is buffered by a 2x gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down
mode makes it ideal for single voltage, battery-based applications. The DAC settling time is programmable,
allowing the designer to optimize speed versus power dissipation. Settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage than DACs C and D.
The TLV5614IYZ is built with a CMOS process and is available in a 16-terminal bumped die (wafer chip scale)
package. It is characterized for operation from –40°C to +85°C in a wire-bonded, small outline (SOIC) package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320 is a trademark of Texas Instruments, Inc.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
MCS is a registered trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Supply voltage, (DVDD, AVDD to GND)
Supply voltage difference, (AVDD to DVDD
Digital input voltage range
7V
)
–2.8V to 2.8V
–0.3V to DVDD + 0.3V
–0.3V to AVDD + 0.3V
–40°C to +85°C
Reference input voltage range
Operating free-air temperature range, TA
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
MIN
4.5
2.7
2
NOM
MAX
5.5
UNIT
5V supply
5
3
Supply voltage, AVDD, DVDD
3V supply
3.3
V
V
V
DVDD = 2.7V
DVDD = 5.5V
DVDD = 2.7V
DVDD = 5.5V
5V supply(1)
3V supply(1)
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
2.4
0.6
1
0
0
2
2.048
1.024
10
VDD – 1.5
VDD – 1.5
Reference voltage, VREF to REFINAB, REFINCD
terminal
V
kΩ
Load resistance, RL
Load capacitance, CL
100
20
pF
Serial clock rate, SCLK
Operating free-air temperature
MHz
°C
TLV5614IYZ
–40
+85
(1) Voltages greater than AVDD/2 cause output saturation for upper DAC codes.
2
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted).
PARAMETER
STATIC DAC SPECIFICATIONS
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
bits
Integral nonlinearity (INL), end point
adjusted
See(1)
See(2)
See(3)
See(4)
±1.5
±0.5
±4
±1
LSB
LSB
Differential nonlinearity (DNL)
Zero-scale error (offset error at zero scale)
Zero-scale error temperature coefficient
EZS
±12
mV
10
ppm/°C
% of FS
voltage
EG
Gain error
See(5)
See(6)
±0.6
Gain error temperature coefficient
10
ppm/°C
dB
Zero scale
Power supply rejection ratio
Full scale
–80
–80
PSRR
See(7)(8)
dB
INDIVIDUAL DAC OUTPUT SPECIFICATIONS
VO
Voltage output range
RL = 10kΩ
0
0
AVDD – 0.4
0.25
V
% of FS
voltage
Output load regulation accuracy
RL = 2kΩ vs 10kΩ
0.1
REFERENCE INPUTS (REFINAB, REFINCD)
VI
RI
CI
Input voltage range
Input resistance
See(9)
AVDD – 1.5
V
10
5
MΩ
pF
dB
Input capacitance
Reference feedthrough
REFIN = 1VPP at 1kHz + 1.024VDC (see(10)
)
–75
0.5
1
Slow
Fast
Reference input bandwidth
REFIN = 0.2VPP + 1.024VDC large signal
MHz
DIGITAL INPUTS (DIN, CS, LDAC, PD)
IIH
IIL
CI
High-level digital input current
Low-level digital input current
Input capacitance
VI = VDD
VI = 0V
±1
±1
µA
µA
pF
3
POWER SUPPLY
Slow
Fast
Slow
Fast
1.6
3.8
1.2
3.2
10
2.4
5.6
1.8
4.8
5V supply, no load, clock running.
All inputs 0V or VDD
mA
IDD
Power supply current
3V supply, no load, clock running.
All inputs 0V or DVDD
mA
nA
Power down supply current (see Figure 12)
(1) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full-scale excluding the effects of zero code and full-scale errors.
(2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code.
(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
(4) Zero-scale error temperature coefficient is given by: EZS TC = [EZS (TMAX) – EZS (TMIN)]/VREF × 106/(TMAX – TMIN).
(5) Gain error is the deviation from the ideal output (2VREF – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero error.
(6) Gain temperature coefficient is given by: EG TC = [EG(TMAX) – EG (TMIN)]/VREF × 106/(TMAX – TMIN).
(7) Zero-scale error rejection ratio (EZS–RR) is measured by varying the AVDD from 5V ± 0.5V and 3V ± 0.3VDC, and measuring the
proportion of this signal imposed on the zero-code output voltage.
(8) Full-scale rejection ratio (EG–RR) is measured by varying the AVDD from 5V ± 0.5V and 3V ± 0.3VDC and measuring the proportion of
this signal imposed on the full-scale output voltage after subtracting the zero scale change.
(9) Reference input voltages greater than VDD/2 cause output saturation for upper DAC codes.
(10) Reference feedthrough is measured at the DAC output with an input code = 000hex and VREF (REFINAB or REFINCD) input =
1.024VDC + 1VPP at 1kHz.
3
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT DYNAMIC PERFORMANCE
Fast
Slow
Fast
Slow
Fast
Slow
5
1
V/µs
V/µs
CL = 100pF, RL = 10kΩ, VO = 10% to 90%,
VREF = 2.048V, 1024V
SR
ts
Output slew rate
3
5.5
20
To ± 0.5 LSB, CL = 100pF, RL = 10kΩ, see
Output settling time
µs
(11)(12)
9
1
To ± 0.5 LSB, CL = 100pF, RL = 10kΩ, see
ts(c)
Output settling time, code to code
µs
(13)
2
Glitch energy
Code transition from 7FF to 800
10
74
66
–68
70
nV–s
SNR
Signal-to-noise ratio
Sinewave generated by DAC, Reference voltage =
SINAD
THD
Signal to noise + distortion
Total harmonic distortion
Spurious-free dynamic range
1.024 at 3V and 2.048 at 5V, fS = 400KSPS, fOUT
1.1kHz sinewave, CL = 100pF, RL = 10kΩ, BW =
20kHz
=
dB
SFDR
DIGITAL INPUT TIMING REQUIREMENTS
tsu(CS–FS)
tsu(FS–CK)
tsu(C16–FS)
Setup time, CS low before FS↓
10
8
ns
ns
ns
Setup time, FS low before first negative
SCLK edge
Setup time. 16th negative SCLK edge after FS low on which bit D0 is sampled before rising edge
of FS
10
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used
instead of the SCLK positive edge to update the DAC, then the setup time is between the FS rising
edge and CS rising edge.
tsu(C16–CS)
twH
10
25
25
8
ns
ns
ns
ns
ns
ns
Pulse duration, SCLK high
twL
Pulse duration, SCLK low
tsu(D)
th(D)
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
5
twH(FS)
20
(11) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
FFFhex to 080hex for 080hex to FFFhex.
(12) Limits are ensured by design and characterization, but are not production tested.
(13) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one
count.
t
t
wH
wL
SCLK
DIN
1
2
3
4
5
15
16
t
th(D)
su(D)
D15
D14
D13
D12
D1
D0
tsu(FS-CK)
tsu(C16-CS)
tsu(CS-FS)
CS
FS
twH(FS)
tsu(C16-FS)
Figure 1. Timing Diagram
4
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
1
DD
15
16
REFINAB
DAC A
+
_
Power-On
Reset
+
_
14
OUTA
10
12
12-Bit
DAC
Latch
14-Bit
Data
and
2
Control
Register
2-Bit
Control
Data
2
2
14
Serial
Input
Register
4
7
Power-Down/
Speed Control
DIN
Latch
2
DAC Select/
Control
Logic
FS
SCLK
CS
5
6
13
12
11
OUTB
OUTC
OUTD
DAC B
DAC C
10
REFINCD
DAC D
3
2
9
8
PD
AGND
DGND
LDAC
5
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
AGND
NO.
9
I/O
—
—
I
DESCRIPTION
Analog ground
AVDD
CS
16
6
Analog supply
Chip select. This terminal is active low.
Digital ground
DGND
DIN
8
—
I
4
Serial data input
DVDD
1
—
Digital supply
Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial
data frame shifted out to the TLV5614IYZ.
I
I
FS
PD
7
2
Power-down pin. Powers down all DACs (overriding the individual power down settings), and
all output stages. This terminal is active low.
Load DAC. When the LDAC signal is high, no DAC output updates occur when the input
digital data is read into the serial interface. The DAC outputs are only updated when LDAC
is low.
I
LDAC
3
REFINAB
REFINCD
SCLK
15
10
5
I
Voltage reference input for DACs A and B.
Voltage reference input for DACs C and D.
Serial clock inputinput
DACA output
I
I
OUTA
14
13
12
11
O
O
O
O
OUTB
DACB output
OUTC
DACC output
OUTD
DACD output
6
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
TYPICAL CHARACTERISTICS
LOAD REGULATION
LOAD REGULATION
0.20
V
0.35
= 3V
= 1V
= Full Scale
V
V
V
= 5V
DD
DD
0.18
0.16
0.14
0.12
0.10
0.08
V
= 2V
= Full Scale
REF
REF
0.30
0.25
0.20
V
O
O
3V Slow Mode, Sink
3V Fast Mode, Sink
5V Slow Mode, Sink
5V Fast Mode, Sink
0.15
0.10
0.06
0.04
0.02
0
0.05
0
0
0.01 0.02 0.05 0.1 0.2 0.5 0.8
Load Current (mA)
1
2
0
0.02 0.04 0.1 0.2 0.4 0.8
Load Current (mA)
1
2
4
LOAD REGULATION
LOAD REGULATION
2.0015
2.0010
4.010
4.005
3V Slow Mode, Source
5V Slow Mode, Source
2.0005
2.0000
1.9995
1.9990
1.9985
3V Fast Mode, Source
4.000
3.995
5V Fast Mode, Source
1.9980
1.9975
V
= 3V
= 1V
3.990
3.985
DD
V
V
V
= 5V
V
DD
REF
1.9970
1.9965
= 2V
= Full Scale
REF
V
= Full Scale
O
O
0
0.01 0.02 0.05 0.1 0.2 0.5 0.8
Load Current (mA)
1
2
0
0.02 0.04 0.1 0.2 0.4 0.8
Load Current (mA)
1
2
4
7
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
4.0
3.5
4.0
3.5
V
V
V
= 3V
DD
= 1.024V
REF
Full Scale
O
Fast Mode
(Worst Case For I
DD
)
Fast Mode
3.0
2.5
3.0
2.5
V
V
V
= 5V
DD
= 1.024V
Full Scale
REF
O
2.0
(Worst Case For I
)
2.0
1.5
DD
1.5
1.0
0.5
1.0
0.5
Slow Mode
Slow Mode
20
-40
-20
0
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
-10
-20
-30
-40
0
V
= 1V + 1V Sinewave,
V
= 1V + 1V Sinewave,
REF DC
Output Full Scale
PP
REF
DC
PP
-10
Output Full Scale
-20
-30
-40
-50
-60
-50
-60
Fast Mode
Slow Mode
-70
-80
-70
-80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
Frequency (kHz)
Frequency (Hz)
8
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION AND NOISE
TOTAL HARMONIC DISTORTION AND NOISE
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1V + 1V Sinewave,
REF DC
Output Full Scale
PP
V
= 1V + 1V Sinewave,
REF DC
Output Full Scale
PP
-10
-10
-20
-30
-40
-20
-30
-40
-50
-60
-50
-60
Slow Mode
Fast Mode
-70
-80
-70
-80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
Frequency (kHz)
Frequency (kHz)
SUPPLY CURRENT
vs
TIME (Entering Power-Down Mode)
4000
3500
3000
2500
2000
1500
1000
500
0
0
200
400
600
800
1000
Time (ns)
9
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY
CODE
0.30
V
= 5V, V
= 2V, SCLK = 1MHz
0.25
0.20
0.15
0.10
0.05
0
CC
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
0
256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096
Code
Figure 13.
INTEGRAL NONLINEARITY
CODE
1.0
0.5
V
= 5V, V
= 2V,
CC
SCLK = 1MHz
REF
0
-0.5
-1.0
-1.5
3840
4096
0
256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584
Code
Figure 14.
10
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5614IYZ is a 12-bit, single-supply DAC based on a resistor string architecture. The device consists of a
serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail
output buffer.
The output voltage (full-scale determined by external reference) is given by:
CODE
2 REF
[V]
n
2
where REF is the reference voltage and CODE is the digital input value within the range of 010 to (2n – 1), where
n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is described in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits '0').
SERIAL INTERFACE
Data transfer occurs in this manner: First, the device must be enabled with CS set low. Then, a falling edge of
FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which
then updates the voltage output to the new level.
The serial interface of the TLV5614IYZ can be used in two basic modes:
•
•
Four-wire (with chip-select)
Three-wire (without chip-select)
Using chip-select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (a DSP or microcontroller). The interface is compatible with the TMS320 DSP family. Figure 15
shows an example with two TLV5614IYZs connected directly to a TMS320 DSP.
TLV5614IYZ-1
TLV5614IYZ-2
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an
example of how to connect the TLV5614IYZ to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5614IYZ
SPI
TLV5614IYZ
Microwire
TLV5614IYZ
FSX
FS
SS
FS
I/O
FS
DIN
SCLK
DIN
SCLK
DIN
SCLK
DX
MOSI
SCLK
SO
SK
CLKX
CS
CS
CS
Figure 16. Three-Wire Interface
11
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
APPLICATION INFORMATION (continued)
Notes on SPI and Microwire connections: Before the controller starts the data transfer, the software must
generate a falling edge on the I/O pin connected to FS. If the word width is eight bits (SPI and Microwire), two
write operations must be performed to program the TLV5614IYZ. After the write operation(s), the DAC output is
updated automatically on the next positive clock edge following the 16th falling clock edge.
SERIAL CLOCK FREQUENCY AND UPDATE RATE
The maximum serial clock frequency is given by:
1
fSCLKmax
=
= 20 MHz
twH(min) + twL(min)
The maximum update rate is:
1
fUPDATEmax
=
= 1.25 MHz
16 (twH(min) + twL(min)
)
Note that the maximum update rate is a theoretical value for the serial interface, because the settling time of the
TLV5614IYZ must also be considered.
DATA FORMAT
The 16-bit data word for the TLV5614IYZ consists of two parts:
•
•
Control bits (D15 . . . D12)
New DAC value (D11 . . . D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
New DAC value (12 bits)
X: don't care
SPD: Speed control bit. 1→fast mode, 0→slow mode
PWR: Power control bit. 1→power down, 0→normal operation
In power-down mode, all amplifiers within the TLV5614IYZ are disabled. A particular DAC (A, B, C, D) of the
TLV5614IYZ is selected by A1 and A0 within the input word.
A1
0
A0
0
DAC
A
0
1
B
1
0
C
1
1
D
12
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
TLV5614IYZ INTERFACED TO TMS320C203 DSP
Hardware Interfacing
Figure 17 shows an example of how to connect the TLV5614IYZ to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the
TLV5614IYZ. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The
general-purpose input/output port bits IO0 and IO1 are used to generate the chip select (CS) and DAC latch
update (LDAC) inputs to the TLV5614IYZ. The active low power-down (PD) is pulled high all the time to ensure
the DACs are enabled.
TMS320C203
TLV5614IYZ
SDIN
VDD
PD
DX
SCLK
FS
CLKX
FSX
I/O 0
I/O 1
CS
VOUTA
VOUTB
VOUTC
VOUTD
LDAC
REFINAB
REFINCD
REF
VSS
Figure 17. TLV5614IYZ Interfaced With TMS320C203
Software
The application example outputs a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and
its quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all four DACs simultaneously, then fetches and writes the next sample to all four DACs. The
samples are stored in a look-up table that describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16–FS) timing requirement occurs. To avoid this violation, the program waits until the transmission of the
previous word has been completed.
;.......................................................................................
; Processor: TMS320C203 runnning at 40 MHz
;
; Description:
;
; This program generates a differential in-phase (sine) on (OUTA-OUTB) and its quadrature
(cosine) as a differential signal on (OUTC-OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12-bit values, describing
; 2 periods of a sine function. A rolling pointer is used to address the table location in
; the first period of this waveform, from which the DAC A samples are read. The samples for
; the other 3 DACs are read at an offset to this rolling pointer
; DAC Function Offset from rolling pointer
; A sine 0
; B inverse sine 16
; C cosine 8
; D inverse cosine24
;
; The on-chip timer is used to generate interrupts at a fixed rate. The interrupt service
; routine first pulses LDAC low to update all DACs simultaneously with the values which
; were written to them in the previous interrupt. Then all 4 DAC values are fetched and
; written out through the synchronous serial interface. Finally, the rolling pointer is
; incremented to address the next sample, ready for the next interrupt.
13
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
; © 1998, Texas Instruments Inc.
;.......................................................................................
;------------------------------ I/O and memory mapped regs -----------------------------
.include "regs.asm"
;-------jump vectors -------------------------------------------------------------------
.ps 0h
b start
b int1
b int23
b timer_isr;
----------- variables ------------------------------------------------------------------
temp .equ 0060h
r_ptr .equ 0061h
iosr_stat .equ 0062h
DACa_ptr .equ 0063h
DACb_ptr .equ 0064h
DACc_ptr .equ 0065h
DACd_ptr .equ 0066h
;-----------constants------------------------------------------------------------------
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control .equ 01000h
DACb_control .equ 05000h
DACc_control .equ 09000h
DACd_control .equ 0d000h
;----------- tables --------------------------------
.ds 02000h
sinevals
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
14
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
.word 00E53h
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main Program
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps 1000h
.entry
start
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; disable interrupts
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
setc INTM ; disable maskable interrupts
splk #0ffffh, IFR; clear all interrupts
splk #0004h, IMR; timer interrupts unmasked
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) × (1+PRD) × (1+TDDR)
; examples for TMS320C203 with 40MHz main clock
; Timer rate TDDR PRD
; 80 kHz 9 24 (18h)
; 50 kHz 9 39 (27h)
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ 0018h
tcr_val.equ 0029h
splk #0000h, temp; clear timer
out temp, TIM
splk #prd_val, temp; set PRD
out temp, PRD
splk #tcr_val, temp; set TDDR, and TRB=1 for auto-reload
out temp, TCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0 CS - and set high
; IO1 LDAC - and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
in temp, ASPCR; configure as output
lacl temp
or #0003h
sacl temp
out temp, ASPCR
in temp, IOSR; set them high
lacl temp
or #0003h
sacl temp
out temp, IOSR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1 Transmit mode - generate FSX
; SSPCR.MCM=1 Clock mode - internal clock source
; SSPCR.FSM=1 Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
splk #0000Eh, temp
15
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
out temp, SSPCR; reset transmitter
splk #0002Eh, temp
out temp,SSPCR
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
lacl #000h
sacl r_ptr
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
clrc INTM ; enable maskable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
next idle ;wait for interrupt
b next
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;all else fails stop here
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done b done ;hang there
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int1 ret ; do nothing and return
int23 ret ; do nothing and return
timer_isr:
in iosr_stat, IOSR; store IOSR value into variable space
lacl iosr_stat ; load acc with iosr status
and #0FFFDh ; reset IO1 - LDAC low
sacl temp ;
out temp, IOSR;
or #0002h ; set IO1 - LDAC high
sacl temp ;
out temp, IOSR;
and #0FFFEh ; reset IO0 - CS low
sacl temp ;
out temp, IOSR;
lacl r_ptr ; load rolling pointer to accumulator
add #sinevals ; add pointer to table start
sacl DACa_ptr ; to get a pointer for next DAC a sample
add #08h ; add 8 to get to DAC C pointer
sacl DACc_ptr
add #08h ; add 8 to get to DAC B pointer
sacl DACb_ptr
add #08h ; add 8 to get to DAC D pointer
sacl DACd_ptr
mar *,ar0 ; set ar0 as current AR
; DAC A
lar ar0, DACa_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACa_control ; OR in DAC A control bits
sacl temp ;
out temp, SDTR; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
We must wait for transmission to complete before writing next word to the SDTR.;
TLV5614/04 interface does not allow the use of burst mode with the full packet; rate, as
we need a CLKX -ve edge to clock in last bit before FS goes high again,; to allow SPI
compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC B
lar ar0, dacb_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACb_control ; OR in DAC B control bits
sacl temp ;
out temp, SDTR; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC C
lar ar0, dacc_ptr ; ar0 points to dac a sample
16
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
lacl * ; get DAC a sample into accumulator
or #DACc_control ; OR in DAC C control bits
sacl temp ;
out temp, SDTR; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC D
lar ar0, dacd_ptr; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #dacd_control ; OR in DAC D control bits
sacl temp ;
out temp, SDTR; send data
lacl r_ptr ; load rolling pointer to accumulator
add #1h ; increment rolling pointer
and #001Fh ; count 0-31 then wrap back round
sacl r_ptr ; store rolling pointer
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; now take CS high again
lacl iosr_stat ; load acc with iosr status
or #0001h ; set IO0 - CS high
sacl temp ;
out temp, IOSR;
clrc intm ; re-enable interrupts
ret ; return from interrupt
.end
TLV5614IYZ INTERFACED TO MCS®51 MICROCONTROLLER
Hardware Interfacing
Figure 18 shows an example of how to connect the TLV5614IYZ to an MCS51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5614IYZ. The active low
power-down pin (PD) of the TLV5614IYZ is pulled high to ensure that the DACs are enabled.
®
MCS 51
TLV5614IYZ
SDIN
VDD
PD
RxD
SCLK
LDAC
CS
TxD
P3.3
P3.4
P3.4
VOUTA
VOUTB
VOUTC
VOUTD
FS
REFINAB
REFINCD
REF
VSS
Figure 18. TLV5614IYZ Interfaced With MCS51
Software
The example is the same as for the TMS320C203 in this data sheet, but adapted for a MCS51 controller. It
generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and its quadrature (cosine)
signal is the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all four DACs simultaneously, then fetches and writes the next sample to all four DACs. The
samples are stored as a look-up table, that describes one full period of a sine wave.
17
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
The serial port of the controller is used in Mode 0, which transmits eight bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TLV5614IYZ. The CS and FS signals are provided in the required fashion through control of IO port 3, which has
bit-addressable outputs.
Processor: 80C51
;
; Description:
;
; This program generates a differential in-phase
(sine) on (OUTA-OUTB) ; and its quadrature (cosine)
as a differential signal on (OUTC-OUTD).
;
; © 1998, Texas Instruments Inc.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME GENIQ
MAIN SEGMENT CODE
ISR SEGMENT CODE
SINTBL SEGMENT CODE
VAR1 SEGMENT DATA
STACK SEGMENT IDATA
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0
LJMP start ; Execution starts at address 0 on power-up.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code in the timer0 interrupt vector
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Global variables need space allocated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG VAR1
temp_ptr: DS 1
rolling_ptr: DS 1
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt service routine for timer 0 interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG ISR
timer0isr:
PUSH PSW
PUSH ACC
CLR INT1 ; pulse LDAC low
SETB INT1 ; to latch all 4 previous values at the same time
; 1st thing done in timer isr => fixed period
CLR T0 ; set CS low
; The signal to be output on each DAC is a sine function. One cycle of a sine wave is
; held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes).
; We have ; one pointer which rolls round this table, rolling_ptr incrementing by
; 2 bytes (1 sample) on each interrupt (at the end of this routine).
; The DAC samples are read at an offset to this rolling pointer:
; DAC Function Offset from rolling_ptr
; A sine 0
; B inverse sine 32
; C cosine 16
; D inverse cosine48
MOV DPTR,#sinevals; set DPTR to the start of the table of sine signal values
MOV R7,rolling_ptr; R7 holds the pointer into the sine table
MOV A,R7 ; get DAC A msb
MOVC A,@A+DPTR ; msb of DAC A is in the ACC
CLR T1 ; transmit it - set FS low
MOV SBUF,A ; send it out the serial port
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
A_MSB_TX:
JNB TI,A_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
18
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
MOV SBUF,A ; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on
; in the sine table - this gives a cosine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 - already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC C msb from the table
ORL A,#01H ; set control bits to DAC C address
A_LSB_TX:
JNB TI,A_LSB_TX ; wait for DAC A lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC C
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
C_MSB_TX:
JNB TI,C_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC C
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table - this gives an inverted sine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 - already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC B msb from the table
ORL A,#02H ; set control bits to DAC B address
C_LSB_TX:
JNB TI,C_LSB_TX ; wait for DAC C lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC B
; get DAC B LSB
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
B_MSB_TX:
JNB TI,B_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC B
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on
; in the sine table - this gives an inverted cosine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 - already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC D msb from the table
ORL A,#03H ; set control bits to DAC D address
B_LSB_TX:
JNB TI,B_LSB_TX ; wait for DAC B lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC D
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
D_MSB_TX:
JNB TI,D_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV A,rolling_ptr
ADD A,#02H ; add 2 to the rolling pointer
19
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
ANL A,#03FH ; wrap back round to 0 if > 64
MOV rolling_ptr,A ; store in memory again
D_LSB_TX:
JNB TI,D_LSB_TX ; wait for DAC D lsb transmit to complete
CLR TI ; clear for next transmit
SETB T1 ; FS high
SETB T0 ; CS high
POP ACC
POP PSW
RETI
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Stack needs definition
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG STACK
DS 10h ; 16 Byte Stack!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main program code
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG MAIN
start:
MOV SP,#STACK–1 ; first set Stack Pointer
CLR A
MOV SCON,A ; set serial port 0 to mode 0
MOV TMOD,#02H ; set timer 0 to mode 2 - auto-reload
MOV TH0,#038H ; set TH0 for 5kHs interrupts
SETB INT1 ; set LDAC = 1
SETB T1 ; set FS = 1
SETB T0 ; set CS = 1
SETB ET0 ; enable timer 0 interrupts
SETB EA ; enable all interrupts
MOV rolling_ptr,A ; set rolling pointer to 0
SETB TR0 ; start timer 0
always:
SJMP always ; while(1) !
RET
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Table of 32 sine wave samples used as DAC data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG SINTBL
sinevals:
DW 01000H
DW 0903EH
DW 05097H
DW 0305CH
DW 0B086H
DW 070CAH
DW 0F0E0H
DW 0F06EH
DW 0F039H
DW 0F06EH
DW 0F0E0H
DW 070CAH
DW 0B086H
DW 0305CH
DW 05097H
DW 0903EH
DW 01000H
DW 06021H
DW 0A0E8H
DW 0C063H
DW 040F9H
DW 080B5H
DW 0009FH
DW 00051H
DW 00026H
DW 00051H
DW 0009FH
DW 080B5H
DW 040F9H
DW 0C063H
DW 0A0E8H
DW 06021H
20
Submit Documentation Feedback
TLV5614IYZ
www.ti.com
SBAS401–DECEMBER 2006
USING THE TLV5614IYZ WAFER CHIP-SCALE PACKAGE (WCSP)
TLV5614 qualifications are done using a wire-bonded small outline (SO) package. The qualifications include:
steady state life, thermal shock, ESD, latch-up, biased HAST, autoclave, and characterization. These qualified
devices are orderable as TLV5614IDW.
NOTE: The wafer chip-scale package (WCSP) for the TLV5614IYZ uses the same die as TLV5614IDW, but is
not qualified. WCSP qualification, including board level reliability (BLR), is the responsibility of the customer.
It is recommended that underfill be used for increased reliability. BLR is application-dependent, but may include
tests such as: temperature cycling, drop test, key push, bend, vibration, and package shear.
For general guidelines on board assembly of the WCSP, the following documentation provides more details:
•
•
Application Report NanoStar™ & NanoFree™ 300µm Solder Bump WCSP Application—SBVA017
Design Summary WCSP Little Logic—SCET007B
NOTE: The use of underfill is required and greatly reduces the risk of thermal mismatch fails.
Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board
level/system level reliability. The process of underfilling is to dispense the epoxy under the device after die
attach reflow. The epoxy adheres to the body of the device and to the printed circuit board (PCB). It reduces
stress placed upon the solder joints as a result of the thermal coefficient of expansion (TCE) mismatch between
the board and the component. Underfill material typically consists of silica or other fillers to increase modulus of
an epoxy, reduce creep sensitivity, and decrease the material TCE.
The recommendation for peak flow temperatures of +220°C to +230°C is based on general empirical results that
indicate that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or
PCB. Lower peak temperatures may cause nonwets (cold solder joints).
Bottom View
Top View
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 19. TLV5614IYZ Bumped Die Package
21
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV5614IYZR
TLV5614IYZT
ACTIVE
ACTIVE
DSBGA
DSBGA
YZ
YZ
16
16
3000
250
Green (RoHS
& no Sb/Br)
SNAGCU Level-NC-NC-UNLIM
Green (RoHS
& no Sb/Br)
SNAGCU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV5614IYZR
TLV5614IYZT
DSBGA
DSBGA
YZ
YZ
16
16
3000
250
180.0
180.0
8.4
8.4
2.15
2.15
3.1
3.1
0.95
0.95
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV5614IYZR
TLV5614IYZT
DSBGA
DSBGA
YZ
YZ
16
16
3000
250
220.0
220.0
220.0
220.0
34.0
34.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
TLV5614IYZR
12-Bit, Quad Channel, 2.7V to 5.5V, DAC in Bumped Die (Wafer Chip Scale) PackageâPb-Free/Green
TI
TLV5614IYZT
12-Bit, Quad Channel, 2.7V to 5.5V, DAC in Bumped Die (Wafer Chip Scale) PackageâPb-Free/Green
TI
©2020 ICPDF网 联系我们和版权申明