TLV2544IDRG4 [TI]
4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, GREEN, PLASTIC, SOIC-16;![TLV2544IDRG4](http://pdffile.icpdf.com/pdf2/p00277/img/icpdf/TLV2544IDRG4_1657233_icpdf.jpg)
型号: | TLV2544IDRG4 |
厂家: | ![]() |
描述: | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, GREEN, PLASTIC, SOIC-16 光电二极管 转换器 |
文件: | 总48页 (文件大小:1463K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
D
D
Maximum Throughput 200-KSPS
D
D
D
D
D
Single Wide Range Supply 2.7 Vdc to
5.5 Vdc
Built-In Reference, Conversion Clock and
8× FIFO
Differential/Integral Nonlinearity Error:
1 LSB
Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
D
D
D
D
Hardware Controlled and Programmable
Sampling Period
Signal-to-Noise and Distortion Ratio:
70 dB, f = 12-kHz
Low Operating Current (1.0-mA at 3.3-V,
1.1-mA at 5.5-V With External Ref
i
Spurious Free Dynamic Range: 75 dB,
f = 12- kHz
Power Down: Software/Hardware
Power-Down Mode (1 µA Max, Ext Ref),
Autopower-Down Mode (1 µA, Ext Ref)
i
SPI (CPOL = 0, CPHA = 0)/DSP-Compatible
Serial Interfaces With SCLK up to 20-MHz
D
Programmable Auto-Channel Sweep
TLV2548
DW OR PW PACKAGE
(TOP VIEW)
TLV2544
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20 CS
SDO
CS
SDO
SDI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
19
18
17
16
15
14
13
12
11
SDI
REFP
REFM
FS
REFP
REFM
FS
SCLK
SCLK
EOC/(INT)
EOC/(INT)
V
PWDN
GND
V
PWDN
GND
CC
CC
A0
A1
A2
A0
A1
A2
A3
A4
10 CSTART
A3
CSTART
A7
9
A6
A5
description
The TLV2548 and TLV2544 are a family of high performance, 12-bit low power, 3.86 µs, CMOS analog-to-digital
converters (ADC) which operate from a single 2.7-V to 5.5-V power supply. These devices have three digital
inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial
data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors
(SPI interface). When interfaced with a TI DSP, a frame sync (FS) signal is used to indicate the start of a serial
data frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular
among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low
power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down
modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The
converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when
a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional
external reference can also be used to achieve maximum flexibility.
The TLV2544C and the TLV2548C are characterized for operation from 0°C to 70°C. The TLV2544I and the
TLV2548I are characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1999 − 2003, Texas Instruments Incorporated
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
functional block diagram
V
CC
4/2 V
Reference
REFP
REFM
FIFO
12 Bit × 8
2548 2544
A0
A1
A2
A3
A4
A5
A6
A7
A0
Low Power
12-BIT
SAR ADC
X
A1
X
A2
X
S/H
OSC
INT
Command
Decode
A3
X
Conversion
Clock
M
U
X
EXT
SDO
CFR
SDI
CMR (4 MSBs)
DIV
SCLK
CS
FS
Control Logic
EOC/(INT)
CSTART
PWDN
GND
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
20-TSSOP
20-SOIC
(DW)
16-SOIC
(D)
16-TSSOP
20-CDIP
(J)
20-LCCC
(FK)
(PW)
(PW)
0°C to 70°C
TLV2548CPW
TLV2548CDW
TLV2548IDW
TLV2544CD
TLV2544ID
TLV2544CPW
TLV2544IPW
—
—
—
−40°C to 85°C TLV2548IPW
—
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
Terminal Functions
TERMINAL
NO.
TLV2544 TLV2548
I/O
DESCRIPTION
NAME
A0
A0
A1
A2
A3
A4
A5
A6
A7
6
7
8
9
6
7
8
I
Analog signal inputs. The analog inputs are applied to these terminals and are internally
multiplexed. The driving source impedance should be less than or equal to 1 kΩ.
A1
A2
A3
For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal CSTART
(CSTART low time controls the sampling period) or program long sampling period to increase the
sampling time.
9
10
11
12
13
CS
16
10
4
20
14
4
I
I
Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever
happens first.
NOTE: CS falling and rising edges need to happen when SCLK is low for a microprocessor interface
such as SPI.
CSTART
This terminal controls the start of sampling of the analog input from a selected multiplex channel.
Sampling time starts with the falling edge of CSTART and ends with the rising edge of CSTART as
long as CS is held high. In mode 01, select cycle, CSTART can be issued as soon as CHANNEL
is selected which means the fifth SCLK during the select cycle, but the effective sampling time is
not started until CS goes to high. The rising edge of CSTART (when CS = 1) also starts the
conversion. Tie this terminal to V
CC
if not used.
EOC/(INT)
O
End of conversion or interrupt to host processor.
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the
sampling period and remains low until the conversion is complete and data are ready for transfer.
EOC is used in conversion mode 00 only.
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to the host
processor. The falling edge of INT indicates data are ready for output. The following CS↓ or FS
clears INT.
FS
13
17
I
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS
remains low after the falling edge of CS, SDI is not enabled until an active FS is presented. A
high-to-low transition on the FS input resets the internal 4-bit counter and enables SDI within a
maximum setup time. SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock
edges) or a low-to-high transition of CS whichever happens first.
Tie this terminal to V
CC
if not used. See the date code information section, item (1).
GND
11
12
3
15
16
3
I
I
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with
respect to GND.
PWDN
SCLK
Both analog and reference circuits are powered down when this pin is at logic zero. The device can
be restarted by active CS, FS or CSTART after this pin is pulled back to logic one.
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used to
clock the input SDI to the input register. When programmed, it may also be used as the source of
the conversion clock.
NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when idling
for SPI compatible interface.
SDI
2
2
I
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,
D(15−12) are decoded as one of the 16 commands (12 only for the TLV2544). The configure write
commands require an additional 12 bits of data.
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is
latched in on the rising edges of SCLK (after CS↓).
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the
falling edge of FS and is latched in on the falling edges of SCLK.
SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high
transition of CS whichever happens first.
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
Terminal Functions (Continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
SDO
TLV2544 TLV2548
1
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state
when CS is high and after the CS falling edge and until the MSB is presented. The output format
is MSB first.
When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after
the CS falling edge, and successive data are available at the rising edge of SCLK and changed on
the falling edge.
When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the falling
edge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK and
changed on the rising edge. (This is typically used with an active FS from a DSP.)
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)
followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should be ignored.
The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit. See the date code
information section, item (2).
REFM
REFP
14
15
18
19
I
I
External reference input or internal reference decoupling. Tie this pin to analog ground if internal
reference is used.
External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µF
between REFP and REFM.) The maximum input voltage range is determined by the difference
between the voltage applied to this terminal and the REFM terminal when an external reference is
used.
V
CC
5
5
I
Positive supply voltage
detailed description
analog inputs and internal test voltages
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection
resulting from channel switching.
converter
The TLV2544/48 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1
shows a simplified version of the ADC.
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
4
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
detailed description (continued)
Charge
Redistribution
DAC
_
+
Ain
Control
Logic
ADC Code
REFM
Figure 1. Simplified Model of the Successive-Approximation System
serial interface
INPUT DATA FORMAT
MSB
LSB
D15−D12
Command ID[15:12]
D11−D0
Configuration data field ID[11:0]
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR/FIFO READ
MSB
LSB
D15−D12
D11−D0
Register content or FIFO content OD[11:0]
Don’t care
OUTPUT DATA FORMAT CONVERSION
MSB
LSB
D15−D4
D3−D0
Don’t care
Conversion result OD[11:0]
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = VREFM
Full scale code = FFFh, Vcode = VREFP − 1 LSB
5
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
control and timing
power up and initialization requirements
D
D
Determine processor type by writing A000h to the TLV2544/48 (CS must be toggled)
Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e.,
active FS.)
The first conversion after power up or resuming from power down is not valid.
start of the cycle:
D
When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.
When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.
D
first 4-MSBs: the command register (CMR)
The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of
the commands require only the first 4 MSBs, i.e., without the 12-bit data field.
The valid commands are listed in Table 1.
Table 1. TLV2544/TLV2548 Command Set
SDI D(15−12) BINARY
TLV2548 COMMAND
Select analog input channel 0
Select analog input channel 1
Select analog input channel 2
Select analog input channel 3
Select analog input channel 4
Select analog input channel 5
Select analog input channel 6
Select analog input channel 7
SW power down (analog + reference)
TLV2544 COMMAND
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Select analog input channel 0
N/A
Select analog input channel 1
N/A
Select analog input channel 2
N/A
Select analog input channel 3
N/A
Read CFR register data shown as SDO D(11−0)
Write CFR followed by 12-bit data, e.g., 0A100h means external reference,
short sampling, SCLK/4, single shot, INT
1010b
Ah plus data
1011b
1100b
1101b
1110b
1111b
Bh
Ch
Dh
Eh
Select test, voltage = (REFP+REFM)/2
Select test, voltage = REFM
Select test, voltage = REFP
FIFO read, FIFO contents shown as SDO D(15−4), D(3−0) = 0000
Fh plus data Reserved
NOTE: The status of the CFR can be read with a read CFR command when the device is programmed
for one-shot conversion mode (CFR D[6,5] = 00).
6
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
control and timing (continued)
configuration
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once
configured after first power up, the information is retained in the H/W or S/W power down state. When the device
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed.
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions
BIT
D11
DEFINITION
Reference select
0: External
1: Internal (Tie REFM to analog ground if the Internal reference is selected.)
D10
D9
Internal reference voltage select
0: Internal ref = 4 V
1: internal ref = 2 V
Sample period select
0: Short sampling 12 SCLKs (1x sampling time)
1: Long sampling 24 SCLKs (2x sampling time)
D(8,7)
Conversion clock source select
00: Conversion clock = internal OSC
01: Conversion clock = SCLK
10: Conversion clock = SCLK/4
11: Conversion clock = SCLK/2
D(6,5)
D(4,3)
Conversion mode select
00: Single shot mode [FIFO not used, D(1,0) has no effect.]
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
†
TLV2548
TLV2544
Sweep auto sequence select
00: 0−1−2−3−4−5−6−7
01: 0−2−4−6−0−2−4−6
10: 0−0−2−2−4−4−6−6
11: 0−2−0−2−0−2−0−2
Sweep auto sequence select
00: N/A
01: 0−1−2−3−0−1−2−3
10: 0−0−1−1−2−2−3−3
11: 0−1−0−1−0−1−0−1
D2
EOC/INT − pin function select
0: Pin used as INT
1: Pin used as EOC
D(1,0)
FIFO trigger level (sweep sequence length)
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
†
These bits only take effect in conversion modes 10 and 11.
sampling
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).
7
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
normal sampling
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short
sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input
source resistance is high.
extended sampling
CSTART − An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order
to have total control of the sampling period and the start of a conversion. This extended sampling is user-defined
and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling
period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal
to the minimum t
. In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon
(SAMPLE)
as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has
become inactive. Therefore the nonoverlapped CSTART low time must meet the minimum sampling time
requirement. The low-to-high transition of CSTART terminates the sampling period and starts the conversion
period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function
is useful for an application that requires:
D
D
The use of an extended sampling period to accommodate different input source impedance
The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed
number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance
at lower supply voltage.
Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command
to read the conversion result or by simply selecting the next channel number for conversion. Since the device
has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data
output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low
transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of
the ADC qualifies this condition and successfully puts the ADC back to its normal sampling mode. This can be
viewed in Figure 9.
Table 3. Sample and Convert Conditions
CONDITIONS SAMPLE
No sampling clock (SCLK) required. Sampling
CONVERT
period is totally controlled by the low time of CSTART.
The high-to-low transition of CSTART (when CS=1)
starts the sampling of the analog input signal. The low
time of CSTART dictates the sampling period. The
low-to-high transition of CSTART ends sampling
period and begins the conversion cycle. (Note: this
trigger only works when internal reference is selected
for conversion modes 01, 10, and 11.)
CS = 1
CSTART (see Figures
11 and 18)
1) If the internal clock OSC is selected a maximum
conversion time of 3.86 µs can be achieved.
SCLK is required. Sampling period is programmable
under normal sampling. When programmed to sample
under short sampling, 12 SCLKs are generated to
complete sampling period. 24 SCLKs are generated
when programmed for long sampling. A command set
to configure the device requires 4 SCLKs thereby ex-
tending to 16 or 28 SCLKs respectively before conver-
sion takes place. (Note: Because the ADC only
bypasses a valid channel select command, the user
can use select channel 0, 0000b, as the SDI input
when either CS or FS is used as trigger for conversion.
The ADC responds to commands such as SW power-
down, 1000b.)
2) If external SCLK is selected, conversion time is
CSTART = 1
FS = 1
t
= 14 × DIV/f , where DIV can be 1, 2, or
(SCLK)
conv
4.
CS
CSTART = 1
CS = 0
FS
8
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TLV2544/TLV2548 conversion modes
The TLV2544 and TLV2548 have four different conversion modes (mode 00, 01, 10, 11). The operation of each
mode is slightly different, depending on how the converter performs the sampling and which host interface is
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held
active, i.e. CS does not need to be toggled through the trigger sequence. SDI can be one of the channel select
commands, such as SELECT CHANNEL 0. Different types of triggers should not be mixed throughout the repeat
and sweep operations. When CSTART is used as the trigger, the conversion starts on the rising edge of
CSTART. The minimum low time for CSTART is equal to t
. If an active CS or FS is used as the trigger,
(SAMPLE)
the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should be allowed
between consecutive triggers so that no conversion is terminated prematurely.
one shot mode (mode 00)
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress
(or INT is generated after the conversion is done).
repeat mode (mode 01)
Repeat mode(mode 01) uses the FIFO. This mode setup requires configuration cycle and channel select cycle.
Once the programmed FIFO threshold is reached, the FIFO must be read, or the data is lost when the sequence
starts over again with the SELECT cycle and series of triggers. No configuration is required except for
reselecting the channel unless the operation mode is changed. This allows the host to set up the converter and
continue monitoring a fixed input and come back to get a set of samples when preferred.
Triggered by CSTART: The first conversion can be started with a select cycle or CSTART. To do so, the user
can issue CSTART during the select cycle, immediately after the four-bit channel select command. The first
sample started as soon as the select cycle is finished (i.e., CS returns to 1). If there is enough time (2 µs) left
between the SELECT cycle and the following CSTART, a conversion is carried out. In this case, you need one
less trigger to fill the FIFO. Succeeding samples are triggered by CSTART.
sweep mode (mode 10)
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed
threshold, an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFO
before the next sweep can start.
repeat sweep mode (mode 11)
Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue
even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)
is generated. Then two things may happen:
1. The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of
the data stored in the FIFO is retained until it has been read in order.
2. If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the
FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.
9
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TLV2544/TLV2548 conversion modes (continued)
Table 4. TLV2544/TLV2548 Conversion Mode
CONVERSION
MODE
CFR
D(6,5)
SAMPLING
TYPE
OPERATION
One shot
00
Normal
•
•
•
•
Single conversion from a selected channel
CS or FS to start select/sampling/conversion/read
One INT or EOC generated after each conversion
Host must serve INT by selecting channel, and converting and reading the previous output.
Extended
•
•
•
•
•
Single conversion from a selected channel
CS to select/read
CSTART to start sampling and conversion
One INT or EOC generated after each conversion
Host must serve INT by selecting next channel and reading the previous output.
Repeat
01
Normal
•
•
•
•
Repeated conversions from a selected channel
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served, it is
cleared.
Extended
Normal
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Sweep
10
11
•
•
•
•
One conversion per channel from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by (FIFO read) reading out all of the FIFO contents up to the threshold, then
write another command(s) to change the conversion mode.
Extended
Normal
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
Repeat sweep
•
•
•
•
Repeated conversions from a sequence of channels
CS or FS to start sampling/conversion
One INT generated after FIFO is filled up to the threshold
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the
threshold, then repeat conversions from the same selected channel or 2) writing another
command(s) to change the conversion mode. If the FIFO is not read when INT is served it is
cleared.
Extended
•
Same as normal sampling except CSTART starts each sampling and conversion when CS is
high.
NOTES: 1. Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT
signal irrespective of how EOC/INT is programmed.
2. Extended. Sampling mode using CSTART as the trigger only works when internal reference is selected for conversion modes 01,
10, and 11.
3. When using CSTART to sample in extended mode, the falling edge of the next CSTART trigger should occur no more than 2.5 µs
after the falling CS edge (or falling FS edge if FS is active) of the channel select cycle. This is to prevent an ongoing conversion from
being canceled.
10
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
timing diagrams
The timing diagrams can be categorized into two major groups: nonconversion and conversion. The
nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion
cycles are those four modes of conversion.
read cycle (read FIFO or read CFR)
read CFR cycle:
The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.
This command works only when the device is programmed in the single shot mode (mode 00).
16
7
12 13
14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
EOC
SDO
OD11 OD10 OD9
OD4 OD3 OD2 OD1 OD0
Figure 2. TLV2544/TLV2548 Read CFR Cycle (FS active)
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID15
ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
OD11 OD10 OD9
OD4 OD3 OD2 OD1 OD0
Figure 3. TLV2544/TLV2548 Read CFR Cycle (FS = 1)
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
read cycle (read FIFO or read CFR) (continued)
FIFO read cycle
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read
command. The first FIFO content is output immediately before the command is decoded. If this command is
not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is
because the read cycle does not generate EOC or INT, nor does it carry out any conversion.
16
7
12 13 14 15
1
2
3
4
5
6
1
2
SCLK
CS
FS
ID15 ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
OD11 OD10 OD9 OD8 OD7 OD6 OD5
OD0
OD11 OD10
These devices can perform continuous FIFO read cycles (FS = 1) controlled by SCLK; SCLK can stop between each 16 SCLKs.
Figure 4. TLV2544/TLV2548 FIFO Read Cycle (FS = 1)
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
write cycle (write CFR)
The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle
does not generate an EOC or INT, nor does it carry out any conversion (see power up and initialization
requirements).
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID11 ID10
ID9
ID4
ID3
ID2
ID1
ID0
ID15 ID14 ID13 ID12
ID15
SDI
INT
EOC
SDO
Figure 5. TLV2544/TLV2548 Write Cycle (FS Active)
16
7
12 13 14 15
1
2
3
4
5
6
1
SCLK
CS
FS
ID11 ID10
ID9
ID4
ID3
ID2
ID1
ID0
ID15 ID14 ID13 ID12
ID15 ID14
SDI
INT
EOC
SDO
Figure 6. TLV2544/TLV2548 Write Cycle (FS = 1)
13
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ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
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ꢁ
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ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
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ꢙ
ꢎ
ꢀ
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ꢖ
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
conversion cycles
DSP/normal sampling
16 − Short Sampling
28 − Long Sampling
30 − Short Sampling
42 − Long Sampling
(If CONV
CLK = SCLK0
1
2
3
4
5
6
7
12
SCLK
CS
t
c
(30 or 42 SCLKs)
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
t
(12 or 24 SCLKs)
(sample)
EOC
SDO
(SDOZ on SCLK16L Regardless
of Sampling Time)
t
(conv)
MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6
LSB
MSB
MSB
Figure 7. Mode 00 Single Shot/Normal Sampling (FS Signal Used)
16 − Short Sampling
28 − Long Sampling
30 − Short Sampling
42 − Long Sampling
(If CONV
CLK = SCLK0
1
1
2
3
4
5
6
7
12
13
SCLK
t
c
(30 or 42 SCLKs)
CS
FS
ID15 ID14 ID13 ID12
ID15
SDI
INT
t
(12 or 24 SCLKs)
(sample)
EOC
SDO
(SDOZ on SCLK16L Regardless
of Sampling Time)
t
(conv)
MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6
LSB
MSB
MSB
Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS Signal not Used)
14
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ꢃ ꢈ ꢉ ꢊꢂ ꢀ ꢋ ꢄ ꢈꢄ ꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏ ꢊꢐꢑꢒ ꢑꢆ ꢅ ꢊꢓꢇ ꢊꢔꢕ ꢖꢗꢗꢘ ꢁꢆ ꢁ ꢋꢙꢊ ꢒꢋ ꢙꢘ ꢚ
ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
conversion cycles (continued)
Device Get Out
Extended Sampling
Mode
Read
Device Going Into
Extended Sampling Mode
Select/Read
Cycle
Select/Read
Cycle
Cycle
CS
t
(sample )
Normal
Cycle
CSTART
FS
t
(conv)
†
†
SDI
INT
EOC
Previous Conversion
Result
Previous Conversion
Result
Hi-Z
Hi-Z
Hi-Z
SDO
†
This is one of the single shot commands. Conversion starts on next rising edge of CSTART.
Figure 9. Mode 00 Single Shot/Extended Sampling (FS Signal Used, FS Pin Connected to TMS320 DSP)
modes using the FIFO: modes 01, 10, 11 timing
Conversion #1
Configure Select From Channel 2
Conversion #4
From Channel 2
Select
CS
FS
CSTART
§
¶
¶
¶
¶
†
‡
‡
‡
‡
§
SDI
INT
Hi-Z
Hi-Z
SDO
Read FIFO
#1
#2
#3
#4
Top of FIFO
†
Command = Configure write for mode 01, FIFO threshold = 1/2
Command = Read FIFO, first FIFO read
Command = Select ch2.
‡
§
¶
Use any channel select command to trigger SDI input.
Figure 10. TLV2544/TLV2548 Mode 01 DSP Serial Interface (Conversions Triggered by FS)
15
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ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
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ꢁ
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ꢗ
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ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion #1 From Channel 2
Configure Select
Conversion #4 From Channel 2
Select
CS
¶
FS
(DSP)
t
t
(sample)
(sample)
t
(sample)
t
(sample)
CSTART
§
‡
‡
‡
‡
§
†
SDI
INT
Hi-Z
Hi-Z
SDO
Read FIFO
#1
#2
#3
#4
Sample Times ≥ MIN t
(sample)
(See Operating Characteristics)
First FIFO Read
†
Command = Configure write for mode 01, FIFO threshold = 1/2
Command = Read FIFO, first FIFO read
Command = Select ch2.
Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channel decoding.
The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 18).
‡
§
¶
Figure 11. TLV2544/TLV2548 Mode 01 µp/DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
Conversion
Conversion
Conversion
From Channel 3
From Channel 0
From Channel 3
Configure
From Channel 0
CS
FS
(DSP)
CSTART
SDI
‡
‡
‡
‡
†
§
§
§
§
§
§
§
§
‡
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO #1
Repeat
Repeat
Top of FIFO
First FIFO Read
Second FIFO Read
†
‡
§
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
Command = Read FIFO
Use any channel select command to trigger SDI input.
Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)
16
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ꢑ
ꢘꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚ
ꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀ
ꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
modes using the FIFO: modes 01, 10, 11 timing (continued)
Conversion
Conversion
Conversion
Conversion
From Channel 0
From Channel 3
From Channel 3
From Channel 0
Configure
CS
FS
(DSP)
CSTART
t
(sample)
t
(sample)
t
(sample)
t
(sample)
‡
‡
‡
‡
†
‡
SDI
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO
#1
Repeat
Repeat
Top of FIFO
Second FIFO Read
First FIFO Read
†
‡
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
Command = Read FIFO
Figure 13. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by CSTART)
Conversion
Conversion
Conversion
Conversion
From Channel 0
From Channel 0
From Channel 3
From Channel 3
Configure
CS
CSTART
SDI
§
‡
‡
‡
‡
§
§
§
§
§
§
§
†
‡
INT
SDO
Read FIFO #1
#2
#3
#4
Read FIFO
#1
Repeat
Repeat
Top of FIFO
First FIFO Read
Second FIFO Read
†
‡
§
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0−1−2−3.
Command = Read FIFO
Use any channel select command to trigger SDI input.
Figure 14. TLV2544/TLV2548 Mode 10/11 µp Serial Interface (Conversions Triggered by CS)
17
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ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀ
ꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
FIFO operation
Serial
0
SDO
12-BIT×8
FIFO
ADC
7
6
5
4
3
2
1
FIFO Full
FIFO 1/2 Full
FIFO 3/4 Full
FIFO 1/4 Full
FIFO Threshold Pointer
Figure 15. TLV2544/TLV2548 FIFO
The device has an 8-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel
or a series of channels based on a preprogrammed sweep sequence. For example, an application may require
eight measurements from channel 3. In this case, the FIFO is filled with eight data sequentially taken from
channel 3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an
orderly manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0−2−4−6−0−2−4−6 is chosen.
An interrupt is sent to the host as soon as all four data are in the FIFO.
In single shot mode, the FIFO automatically uses a 1/8 FIFO depth. Therefore the CFR bits (D1,0) controlling
FIFO depth are don’t care.
SCLK and conversion speed
There are two ways to adjust the conversion speed.
D
The SCLK can be used as the source of the conversion clock to get the highest throughput of the device.
The minimum onboard OSC is 3.6 MHz and 14 conversion clocks are required to complete a conversion.
(Corresponding 3.86 µs conversion time) The devices can operate with an SCLK up to 20 MHz for the
supply voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as
the source of the conversion clock. The clock divider provides speed options appropriate for an application
where a high speed SCLK is used for faster I/O. The total conversion time is 14 ×(DIV/f
) where DIV is 1,
SCLK
2, or 4. For example a 20 MHz SCLK with the divide by 4 option produces a {14 × (4/20 M)} = 2.8 µs
conversion time. When an external serial clock (SCLK) is used as the source of the conversion clock, the
maximum equivalent conversion clock (f
/DIV) should not exceed 6 MHz.
SCLK
D
Autopower down can be used to slow down the device at a reduced power consumption level. This mode
is always used by the converter. If the device is not accessed (by CS or CSTART), the converter is powered
down to save power. The built-in reference is left on in order to quickly resume operation within one half
SCLK period. This provides unlimited choices to trade speed with power savings.
reference voltage
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,
REFP is set to 2 V or 4 V and REFM should be connected to the analog ground of the converter. An external
reference can also be used through two reference input pins, REFP and REFM, if the reference source is
programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the
analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the
analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute
maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REFP and
at zero when the input signal is equal to or lower than REFM.
18
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
reference block equivalent circuit
INTERNAL
REF
Close = Int Ref Used
Open = Ext Ref Used
REFP
Sample
Convert
10 µF
Internal
Reference
Compensation
Cap
0.1 µF
Decoupling
Cap
~50 pF
CDAC
REFM (See Note A)
External to the Device
NOTES: A. If internal reference is used, tie REFM to analog ground and install a 10 µF (or 4.7 µF) internal reference compensation capacitor
between REFP and REFM to store the charge as shown in the figure above.
B. If external reference is used, the 10 µF (internal reference compensation) capacitor is optional. REFM can be connected to external
REFM or AGND.
C. Internal reference voltage drift, due to temperature variations, is approximately 10 mV about the nominal 2 V (typically) from −10°C
to 100°C. The nominal value also varies approximately 50 mV across devices.
D. Internal reference leakage during low ON time: Leakage resistance is on the order of 100 MΩ or more. This means the time constant
is about 1000 s with 10 µF compensation capacitance. Since the REF voltage does not vary much, the reference comes up quickly
after resuming from auto power down. At power up and power down the internal reference sees a glitch of about 500 µV when 2 V
internal reference is used (1 mV when 4 V internal reference is used). This glitch settles out after about 50 µs.
power down
The device has three power-down modes.
autopower-down mode
The device enters the autopower-down state at the end of a conversion.
In autopower-down, the power consumption reduces to about 1 mA when an internal reference is selected. The
built-in reference is still on to allow the device to resume quickly. The resumption is fast enough (within 0.5
SCLK) for use between cycles. An active CS, FS, or CSTART resumes the device from power-down state. The
power current is 1 µA when an external reference is programmed and SCLK stops.
hardware/software power-down mode
Writing 8000h to the device puts the device into a software power down state, and the entire chip (including the
built-in reference) is powered down. For a hardware power-down, the dedicated PWDN pin provides another
way to power down the device asynchronously. These two power-down modes power down the entire device
including the built-in reference to save power. The power down current is reduced to about 1 µA is the SCLK
is stopped.
An active CS, FS, or CSTART restores the device. There is no time delay when an external reference is selected.
However, if an internal reference is used, it takes about 20 ms to warm up. Deselect PWDN pin to remove the
device from the hardware power-down state. This requires about 20 ms to warm up if an internal reference is
also selected.
The configuration register is not affected by any of the power down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.
19
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ꢁ
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ꢃ
ꢄ
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ꢇ
ꢑ
ꢘ
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ꢎ
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ꢁ
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ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, GND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
CC
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.3 V
CC
CC
CC
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
J
Operating free-air temperature range, T : TLV2544/48C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV2544/48I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
‡
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
1110 mW
8.9 mW/°C
10.4 mW/°C
6.7 mW/°C
7.8 mW/°C
710 mW
577 mW
222 mW
259 mW
—
DW
1294 mW
828 mW
673 mW
16 PW
20 PW
839 mW
537 mW
437 mW
977 mW
625 mW
508 mW
—
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (R
given are for informational purposes only.
). Thermal resistance is not production tested and the values
ΘJA
recommended operating conditions
MIN
2.7
0
NOM
MAX
UNIT
Supply voltage, V
CC
3.3
5.5
V
V
V
V
Analog input voltage (see Note 4)
High level control input voltage, V
V
CC
2.1
IH
IL
Low-level control input voltage, V
0.6
Delay time, delay from CS falling edge to FS rising edge, t
(See Figure 16)
d(CSL-FSH)
0.5
0.5
20
SCLKs
SCLKs
ns
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS = 1), or
17th rising edge (FS is active) t (See Figures 16, and 19)
d(SCLK-CSH)
Setup time, FS rising edge before SCLK falling edge, t
(See Figure 16)
su(FSH-SCLKL
Hold time, FS hold high after SCLK falling edge, t
h(FSH-SCLKL)
(See Figure 16)
30
100
0.75
75
ns
ns
Pulse width, CS high time, t
wH(CS)
(See Figures 16 and 19)
Pulse width, FS high time, t (FS) (See Figure 16)
wH
1
SCLKs
V
V
= 2.7 V to 3.6 V
= 4.5 V to 5.5V
10000
10000
CC
SCLK cycle time, t
c(SCLK)
(See Figures 16, and 19)
ns
50
CC
NOTE 4: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while
input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to
1 V. (VREFP − VREFM − 1); however, the electrical specifications are no longer applicable.
20
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
recommended operating conditions (continued)
MIN
NOM
MAX
0.6
UNIT
SCLKs
SCLKs
Pulse width, SCLK low time, t
wL(SCLK)
(See Figures 16 and 19)
(See Figures 16 and 19)
0.4
0.4
Pulse width, SCLK high time, t
wH(SCLK)
0.6
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of
SCLK (FS=1), t (See Figures 16 and 19)
25
5
ns
ns
su(DI-SCLK
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge
of SCLK (FS=1), t (See Figure 16)
h(DI-SCLK)
Delay time, delay from CS falling edge to SDO valid, t
(See Figures 16 and 19)
d(CSL-DOV)
25
25
ns
ns
Delay time, delay from FS falling edge to SDO valid, t
(See Figure 16)
SDO = 5 pF
d(FSL-DOV)
0.5 SCLK
+ 9
0.5 SCLK
0.5 SCLK
0.5 SCLK
0.5 SCLK
V
= 4.5 V
= 2.7 V
CC
Delay time, delay from SCLK falling edge (FS is
active) or SCLK rising edge (FS=1) to SDO valid,
0.5 SCLK
+ 10
SDO = 25 pF
SDO = 5 pF
SDO = 25 pF
t
. (See Figures 16 and 19).
ns
d(SCLK-DOV)
0.5 SCLK
+ 18
For a date code later than xxx, see the date code
information item (3).
V
CC
0.5 SCLK
+ 19
Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge
(FS=1) to EOC falling edge, t (See Figures 16 and 19)
45
ns
d(SCLK-EOCL)
Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from
the 17th rising edge SCLK to INT falling edge (when FS active), t
(See Figure 19)
Min t
µs
d(SCLK-INTL)
(conv)
Delay time, delay from CS falling edge or FS rising edge to INT rising edge,
. See Figures 16, 17, 18 and 19)
1
50
50
ns
ns
t
t
d(CSL-INTH) or d(FSH-INTH)
Delay time, delay from CS rising edge to CSTART falling edge, t
(See Figures 17 and 18)
d(CSH-CSTARTL)
100
Delay time, delay from CSTART rising edge to EOC falling edge, t
(See Figures 17 and 18)
d(CSTARTH-EOCL)
1
ns
µs
µs
Pulse width, CSTART low time, t (CSTART) (See Figures 17 and 18)
wL
Min t
(sample)
Delay time, delay from CSTART rising edge to CSTART falling edge,
Max t
(conv)
t
(See Figure 18)
d(CSTARTH-CSTARTL)
Delay time, delay from CSTART rising edge to INT falling edge, t
(See Figures 17 and 18)
d(CSTARTH-INTL)
Max t
(conv)
µs
°C
TLV2544C/TLV2548C
TLV2544I/TLV2548I
0
70
85
Operating free-air temperature, T
A
−40
21
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ꢁ
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ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
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ꢗ
ꢖ
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ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range, V
= V
= 2.7 V to
CC
REFP
5.5 V, V
= 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)
REFM
†
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX
UNIT
V
V
V
V
= 5.5 V, I = −0.2 mA at 25 pF load
OH
CC
CC
CC
CC
V
High-level output voltage
V
OH
OL
= 2.7 V, I = -20 µA at 25 pF load
V
−0.2
CC
OH
= 5.5 V, I = 0.8 mA at 25 pF load
OL
0.4
0.1
V
I
Low-level output voltage
V
= 2.7 V, I = 20 µA at 25 pF load
OL
Off-state output current
(high-impedance-state)
V
V
= V
CC
1
2.5
µA
µA
CS = V
OZ
O
CC
CC
Off-state output current
(high-impedance-state)
I
= 0
O
−2.5
−1
CS = V
OZ
I
I
High-level input current
Low-level input current
V = V
CC
0.005
2.5
2.5
1.1
1
µA
µA
IH
IL
I
V = 0 V
I
−0.005
V
V
V
V
V
V
V
V
= 4.5 V to 5.5 V
= 2.7 V to 3.3 V
= 4.5 V to 5.5 V
= 2.7 V to 3.3 V
= 4.5 V to 5.5 V
= 2.7 V to 3.3 V
= 4.5 V to 5.5 V
= 2.7 V to 3.3 V
CC
CC
CC
CC
CC
CC
CC
CC
CS at 0 V, Ext ref
CS at 0 V, Int ref
CS at 0 V, Ext ref
CS at 0 V, Int ref
mA
mA
mA
mA
Operating supply current, normal
short sampling
2.1
1.6
I
CC
1.1
1
Operating supply current, extended
sampling
2.1
1.6
Power down supply current
for all digital inputs,
V
V
= 4.5 V to 5.5 V, Ext clock
= 2.7 V to 3.3 V, Ext clock
0.1
0.1
1
1
CC
CC
I
I
µA
CC(PD)
0 ≤ V ≤ 0.3 V or
I
V ≥ V − 0.3 V, SCLK = 0
I
CC
‡
Auto power-down current for all
V
V
= 4.5 V to 5.5 V, Ext clock, Ext ref
= 2.7 V to 3.3 V, Ext ref, Ext clock
1
CC
CC
digital inputs, 0 ≤ V ≤ 0.3 V or
µA
µA
µA
I
CC(AUTOPWDN)
§
1.0
V ≥ V − 0.3 V, SCLK = 0
I
CC
Selected channel at V
1
1
CC
Selected channel leakage current
Selected channel at 0 V
= V = 5.5 V, V = GND
REFM
Maximum static analog reference
current into REFP (use external
reference)
V
1
REFP
CC
Analog inputs
Control Inputs
45
5
50
25
C
Z
Input capacitance
pF
i
V
V
= 4.5 V
= 2.7 V
500
600
CC
CC
Input MUX ON resistance
Ω
i
†
‡
§
All typical values are at V
CC
1.2 mA if internal reference is used, 165 µA if internal clock is used.
0.8 mA if internal reference is used, 116 µA if internal clock is used.
= 5 V, T = 25°C.
A
22
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ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range, V
= V
= 2.7 V to
CC
REFP
5.5 V, V
= 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted) (continued)
REFM
ac specifications
PARAMETER
TEST CONDITIONS
f = 12 kHz at 200 KSPS C and I suffix
MIN
TYP
70
MAX
−76
UNIT
dB
SINAD
THD
Signal-to-noise ratio +distortion
Total harmonic distortion
69
I
f = 12 kHz at 200 KSPS
I
−82
11.6
−84
dB
ENOB
SFDR
Effective number of bits
f = 12 kHz at 200 KSPS
I
Bits
dB
Spurious free dynamic range
f = 12 kHz at 200 KSPS
I
−75
Analog input
Full power-bandwidth, −3 dB
Full-power bandwidth, −1 dB
1
MHz
kHz
500
reference specifications† (0.1 µF and 10 µF between REFP and REFM pins)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Positive reference input voltage, REFP
Negative reference input voltage, REFM
V
V
= 2.7 V to 5.5 V
2
V
V
V
CC
CC
2
= 2.7 V to 5.5 V
= 5.5 V
0
CC
CS = 1, SCLK = 0, (off)
100
20
MΩ
kΩ
MΩ
kΩ
V
V
CC
CC
CS = 0, SCLK = 20 MHz (on)
CS = 1, SCLK = 0 (off)
25
25
Reference Input impedance
100
20
V
= 2.7 V
CS = 0, SCLK = 15 MHz (on)
Reference Input voltage difference, REFP−REFM
Internal reference voltage, REFP−REFM
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 5.5 V
= 5.5 V
2
V
CC
VREF SELECT = 4 V
VREF SELECT = 2 V
VREF SELECT = 2 V
3.85
1.925
1.925
4
2
4.15
2.075
2.075
V
= 5.5 V
V
= 2.7 V
2
V
Internal reference start-up time
= 5.5 V, 2.7 V with 10 µF compensation cap
20
16
ms
PPM/°C
†
Internal reference temperature coefficient
= 2.7 V to 5.5 V
40
†
Specified by design
23
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ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
operating characteristics over recommended operating free-air temperature range, V
= V
= 2.7 V to
CC
REFP
5.5 V, V
= 0 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)
REFM
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
LSB
LSB
LSB
LSB
E
E
E
E
Integral linearity error (INL) (see Note 6)
Differential linearity error (DNL)
Offset error (see Note 7)
1
1
L
See Note 5
D
See Note 5
See Note 5
2.5
+3.5
O
FS
Full scale error (see Note 7)
−1.6
800h
SDI = B000h
SDI = C000h
SDI = D000h
(2048D)
Self-test output code (see Table 1 and
Note 8)
000h (0D)
FFFh
(4095D)
Internal OSC
2.33
600
3.5
3.86
(14 DIV)
t
t
Conversion time
External SCLK
µs
(conv)
f
SCLK
With a maximum of 1-kΩ input source
Sampling time
ns
(sample)
impedance
†
All typical values are at T = 25°C.
A
NOTES: 5. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that
applied to REFM convert as all zeros (000000000000).
6. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference
between 111111111111 and the converted output for full-scale input voltage.
8. Both the input data and the output codes are expressed in positive logic.
24
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ꢑ ꢘꢚ ꢎ ꢖꢁꢶꢖꢗ ꢖꢁ ꢋ ꢛꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁꢶꢔ ꢋꢗ ꢂꢘꢚꢀ ꢘ ꢚꢑꢶ ꢙꢎ ꢀ ꢕꢶꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘꢚ ꢊꢜ ꢋ ꢙꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
•
25
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ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
SELECT CYCLE
V
V
IH
CS
IL
t
d(CSH-CSTARTL)
t
wL(CSTART)
V
V
IH
CSTART
IL
†
t
d(CSTARTH-INTL)
t
(CONV)
V
OH
EOC
INT
V
OL
t
d(CSTARTH-EOCL)
t
d(CSL-INTH)
V
OH
V
OL
†
CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE.
Figure 17. Critical Timing (Extended Sampling, Single Shot)
SELECT CYCLE
V
IH
CS
t
V
wL(CSTART)
IL
t
t
d(CSTARTH−CSTARTL)
d(CSH-CSTARTL)
CSTART
V
V
IH
IL
†
V
OH
EOC
INT
t
V
d(CSL-INTH)
OL
t
d(CSTARTH-EOCL)
t
d(CSTARTH-INTL)
V
OH
V
OL
†
CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE. In this case, the actual
sampling time is measured from the rising edge CS to the rising edge of CSTART.
Figure 18. Critical Timing (Extended Sampling, Repeat/Sweep/Repeat Sweep)
26
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ꢑ ꢘꢚ ꢎ ꢖꢁꢶꢖꢗ ꢖꢁ ꢋ ꢛꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁꢶꢔ ꢋꢗ ꢂꢘꢚꢀ ꢘ ꢚꢑꢶ ꢙꢎ ꢀ ꢕꢶꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘꢚ ꢊꢜ ꢋ ꢙꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
•
27
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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ꢁ
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ꢃ
ꢄ
ꢅ
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ꢎ
ꢖ
ꢁ
ꢖ
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ꢖ
ꢁ
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ꢀ
ꢋ
ꢊ
ꢜ
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ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
vs
TEMPERATURE
TEMPERATURE
0.53
0.52
0.51
0.6
0.595
0.59
0.585
0.5
0.58
0.575
0.49
V
= 2.7 V, Internal Reference = 2 V,
CC
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
0.57
0.565
0.56
V
= 5.5 V, Internal Reference = 2 V,
CC
0.48
0.47
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
−23.75
25
90
−40
−7.5 8.75
41.25 57.5 73.75
−23.75
25
− Temperature − °C
90
−40
−7.5 8.75
41.25 57.5 73.75
T
A
− Temperature − °C
T
A
Figure 21
Figure 20
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
vs
vs
TEMPERATURE
TEMPERATURE
0.496
0.494
0.492
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.488
0.486
0.484
0.482
V
= 5.5 V, Internal Reference = 2 V,
CC
V
= 2.7 V, Internal Reference = 2 V,
CC
Internal Oscillator, Single Shot,
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
Short Sample, Mode 00 µP Mode
0.48
0.478
−23.75
25
90
−40
−7.5 8.75
41.25 57.5 73.75
−23.75
25
− Temperature − °C
90
−40
−7.5 8.75
41.25 57.5 73.75
T
A
− Temperature − °C
T
A
Figure 22
Figure 23
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢅꢇ
ꢃ ꢈ ꢉ ꢊꢂ ꢀ ꢋ ꢄ ꢈꢄ ꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏ ꢊꢐꢑꢒ ꢑꢆ ꢅ ꢊꢓꢇ ꢊꢔꢕ ꢖꢗꢗꢘ ꢁꢆ ꢁ ꢋꢙꢊ ꢒꢋ ꢙꢘ ꢚ
ꢑ ꢘꢚ ꢎ ꢖꢁ ꢖꢗ ꢖꢁ ꢋꢛ ꢊꢀꢋ ꢊꢜꢎꢛ ꢎ ꢀꢖꢁ ꢔꢋ ꢗꢂꢘ ꢚꢀ ꢘꢚꢑ ꢙ ꢎꢀ ꢕ ꢖꢝꢀꢋ ꢒꢋ ꢙ ꢘ ꢚꢊ ꢜꢋ ꢙ ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
OFFSET ERROR
vs
GAIN ERROR
vs
TEMPERATURE
TEMPERATURE
1.2
1
0.5
0
0.8
−0.5
0.6
0.4
−1
−1.5
V
CC
= 5 V, Internal Reference = 4 V,
V
CC
= 5 V, Internal Reference = 4 V,
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
External Oscillator = SCLK/4,
Single Shot, Long Sample,
Mode 00 µP Mode
0.2
0
−2
−2.5
−23.75
25
90
−23.75
25
T − Temperature − °C
A
90
−40
−7.5 8.75
41.25 57.5 73.75
−40
−7.5 8.75
41.25 57.5 73.75
T
A
− Temperature − °C
Figure 24
Figure 25
SUPPLY CURRENT
vs
POWER DOWN CURRENT
vs
TEMPERATURE
TEMPERATURE
1.4
0.4
0.2
External Reference = 4 V, Internal Oscillator,
Single Shot, Short Sample, Mode 00 µP Mode
Long Sample
V
CC
= 5 V
1.2
1
0
−0.2
Short Sample
−0.4
−0.6
V
CC
= 2.7 V
0.8
0.6
V
CC
= 5.5 V
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator, Single Shot,
Short Sample, Mode 00 µP Mode
−0.8
−1
−23.75
25
90
−40
−7.5 8.75
41.25 57.5 73.75
−23.75
25
− Temperature − °C
90
−40
−7.5 8.75
41.25 57.5 73.75
T
A
− Temperature − °C
T
A
Figure 26
Figure 27
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢆ
ꢀ
ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀ
ꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.5
0.0
−0.5
−1.0
0
0
0
4097
4097
4097
Samples
Figure 28
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
−0.5
−1.0
Samples
Figure 29
INTEGRAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
−0.5
−1.0
Samples
Figure 30
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢅꢇ
ꢃ ꢈ ꢉ ꢊꢂ ꢀ ꢋ ꢄ ꢈꢄ ꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏ ꢊꢐꢑꢒ ꢑꢆ ꢅ ꢊꢓꢇ ꢊꢔꢕ ꢖꢗꢗꢘ ꢁꢆ ꢁ ꢋꢙꢊ ꢒꢋ ꢙꢘ ꢚ
ꢑ
ꢘꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚ
ꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀ
ꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
1.0
0.5
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,
CC
Single Shot, Short Sample, Mode 00 µP Mode
0.0
−0.5
−1.0
0
4097
Samples
Figure 31
100%
160
150
140
130
120
110
100
90
V
= 5 V, External Reference = 4 V,
CC
Internal Oscillator , Single Shot, Long Sample, Mode 00 µP
Mode @ 200 KSPS
80
70
60
50
40
30
20
10
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
f − Frequency − kHz
Figure 32
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢆ
ꢀ
ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE + DISTORTION
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
11.50
11.40
−67
−67.50
−68
11.30
11.20
−68.50
−69
11.10
11
−69.50
−70
V
= 5 V,
CC
V
= 5 V,
CC
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
10.90
10.80
−70.50
−71
0
50
100
150
0
50
100
150
f − Frequency − kHz
f − Frequency − kHz
Figure 33
Figure 34
TOTAL HARMONIC DISTORTION
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
−69
−70
−71
−72
−73
−74
−75
−76
−77
−73
−74
−75
−76
−77
−78
−79
−80
V = 5 V,
CC
External Reference = 4 V,
Internal Oscillator,
V
= 5 V,
CC
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
Single Shot, Long Sample,
Mode 00 µP Mode
−81
−82
−78
−79
0
50
100
150
0
50
100
150
f − Frequency − kHz
f − Frequency − kHz
Figure 35
Figure 36
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢅꢇ
ꢃ ꢈ ꢉ ꢊꢂ ꢀ ꢋ ꢄ ꢈꢄ ꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏ ꢊꢐꢑꢒ ꢑꢆ ꢅ ꢊꢓꢇ ꢊꢔꢕ ꢖꢗꢗꢘ ꢁꢆ ꢁ ꢋꢙꢊ ꢒꢋ ꢙꢘ ꢚ
ꢑ
ꢘꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚ
ꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀ
ꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
−70.2
−70.4
−70.6
V
= 5 V,
CC
External Reference = 4 V,
Internal Oscillator,
Single Shot, Long Sample,
Mode 00 µP Mode
−70.8
−71
−71.2
−71.4
0
50
100
150
f − Frequency − kHz
Figure 37
PRINCIPLES OF OPERATION
v
cc
10 kΩ
V
DD
XF
CS
TXD
RXD
SDI
SDO
A
IN
CLKR
CLKX
SCLK
TLV2544/
TLV2548
TMS320 DSP
BIO
INT
FSR
FSX
FS
GND
Figure 38. Typical Interface to a TMS320 DSP
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢅ
ꢆ
ꢀ
ꢃꢈ ꢉꢊ ꢂ ꢀꢋ ꢄ ꢈ ꢄꢊꢂꢆ ꢌ ꢃ ꢊꢍꢎ ꢀꢆ ꢃ ꢏ ꢏꢊ ꢐꢑ ꢒꢑ ꢆ ꢅ ꢊꢓ ꢇ ꢊꢔꢕꢖꢗ ꢗꢘꢁ ꢆ ꢁ ꢋꢙꢊꢒꢋ ꢙ ꢘꢚ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢇ
ꢑ
ꢘ
ꢚ
ꢎ
ꢖ
ꢁ
ꢖ
ꢗ
ꢖ
ꢁ
ꢋ
ꢛ
ꢊ
ꢀ
ꢋ
ꢊ
ꢜ
ꢎ
ꢛ
ꢎ
ꢀ
ꢖ
ꢁ
ꢔ
ꢋ
ꢗ
ꢂ
ꢘ
ꢚꢀ
ꢘ
ꢚ
ꢑ
ꢙ
ꢎ
ꢀ
ꢕ
ꢖ
ꢝ
ꢀꢋ
ꢒ
ꢋ
ꢙ
ꢘ
ꢚ
ꢊ
ꢜ
ꢋ
ꢙ
ꢗ
SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
DATA CODE INFORMATION
Parts with a date code earlier than 31xxxxx have the following discrepancies:
1. Earlier devices react to FS input irrespective of the state of the CS signal
2. The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller
mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when
FS is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for
processor input data, but may reduce the hold time for processor input data. It is recommended that a
100 pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that
requires longer input data hold time.
3. For earlier silicon, the delay time is specified as:
MIN
16
NOM
MAX
UNIT
SDO = 0 pF
V
V
= 4.5 V
= 2.7 V
CC
SDO = 100 pF
SDO = 0 pF
20
Delay time, delay from SCLK falling edge (FS is active) or
ns
SCLK rising edge (FS=1) to next SDO valid, t
.
24
d(SCLK-DOV)
CC
SDO = 100 pF
30
This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time
required by the external digital host processor, therefore, a minimum value is specified. The newer silicon
has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK
exists as the hold time for the external host processor, the specified maximum value helps with the
calculation of the setup time requirement of the external digital host processor.
For an explanation of the DSP mode, reverse the rising/falling edges in item (2) above.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TLV2544CD
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
16
16
16
16
16
16
16
16
16
16
20
20
20
20
20
20
20
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2544C
TLV2544CDR
TLV2544CPW
TLV2544CPWR
TLV2544ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
2500
90
Green (RoHS
& no Sb/Br)
0 to 70
2544C
TV2544
TV2544
2544I
TSSOP
TSSOP
SOIC
PW
PW
D
Green (RoHS
& no Sb/Br)
0 to 70
2000
40
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
TLV2544IDG4
TLV2544IDR
SOIC
D
40
Green (RoHS
& no Sb/Br)
2544I
SOIC
D
2500
90
Green (RoHS
& no Sb/Br)
2544I
TLV2544IPW
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
DW
DW
DW
DW
PW
PW
PW
Green (RoHS
& no Sb/Br)
TY2544
TY2544
TY2544
2548C
2548C
2548C
2548C
TV2548
TV2548
TV2548
TLV2544IPWG4
TLV2544IPWR
TLV2548CDW
TLV2548CDWG4
TLV2548CDWR
TLV2548CDWRG4
TLV2548CPW
TLV2548CPWG4
TLV2548CPWR
90
Green (RoHS
& no Sb/Br)
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
2000
2000
70
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
0 to 70
70
Green (RoHS
& no Sb/Br)
0 to 70
2000
Green (RoHS
& no Sb/Br)
0 to 70
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2548CPWRG4
TLV2548IDW
ACTIVE
TSSOP
SOIC
PW
20
20
20
20
20
20
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TV2548
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
PW
PW
PW
PW
25
25
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2548I
TLV2548IDWG4
TLV2548IDWR
TLV2548IPW
SOIC
Green (RoHS
& no Sb/Br)
2548I
SOIC
2000
70
Green (RoHS
& no Sb/Br)
2548I
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
TY2548
TY2548
TY2548
TY2548
TLV2548IPWG4
TLV2548IPWR
TLV2548IPWRG4
70
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2548 :
Enhanced Product: TLV2548-EP
•
Military: TLV2548M
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2544CDR
TLV2544CPWR
TLV2544IDR
SOIC
TSSOP
SOIC
D
16
16
16
16
20
20
20
20
2500
2000
2500
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
24.4
16.4
24.4
16.4
6.5
6.9
10.3
5.6
2.1
1.6
2.1
1.6
2.7
1.6
2.7
1.6
8.0
8.0
16.0
12.0
16.0
12.0
24.0
16.0
24.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
PW
D
6.5
10.3
5.6
8.0
TLV2544IPWR
TLV2548CDWR
TLV2548CPWR
TLV2548IDWR
TLV2548IPWR
TSSOP
SOIC
PW
DW
PW
DW
PW
6.9
8.0
10.8
6.95
10.8
6.95
13.3
7.1
12.0
8.0
TSSOP
SOIC
13.3
7.1
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2544CDR
TLV2544CPWR
TLV2544IDR
SOIC
TSSOP
SOIC
D
16
16
16
16
20
20
20
20
2500
2000
2500
2000
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
35.0
45.0
38.0
45.0
38.0
PW
D
TLV2544IPWR
TLV2548CDWR
TLV2548CPWR
TLV2548IDWR
TLV2548IPWR
TSSOP
SOIC
PW
DW
PW
DW
PW
TSSOP
SOIC
TSSOP
Pack Materials-Page 2
IMPORTANT NOTICE
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