TLV2543INE4 [TI]
12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS; 12位模拟数字转换器带串行控制和11个模拟输入
| 型号： | TLV2543INE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 文件： | 总28页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
12-Bit-Resolution A/D Converter
DB, DW, OR N PACKAGE
(TOP VIEW)
10-µs Conversion Time Over Operating
Temperature Range
11 Analog Input Channels
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
V
CC
EOC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
3 Built-In Self-Test Modes
I/O CLOCK
DATA INPUT
DATA OUT
CS
Inherent Sample and Hold Function
Linearity Error . . . ±1 LSB Max
On-Chip System Clock
End-of-Conversion (EOC) Output
14 REF+
13
12
11
REF–
AIN10
AIN9
Unipolar or Bipolar Output Operation
(Signed Binary With Respect to Half of the
Applied Referenced Voltage)
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology
description
The TLV2543C and TLV2543I are 12-bit, switched-capacitor, successive-approximation, analog-to-digital
converters (ADCs). Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK),
and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor
or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The
sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
The TLV2543 is available in the DW, DB, and N packages. The TLV2543C is characterized for operation from
0°C to 70°C, and the TLV2543I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
†
PLASTIC DIP
N
T
A
†
DB
DW
0°C to 70°C
TLV2543CDW
TLV2543IDW
TLV2543CDB
TLV2543IDB
TLV2543CN
TLV2543IN
–40°C to 85°C
†
Available in tape and reel and ordered as the TLV2543CDWR, TLV2543CDBLE, TLV2543IDBR, or
TLV2543IDWR.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
functional block diagram
REF+
14
REF–
13
12-Bit
Analog-to-Digital
Converter
1
2
3
4
5
6
7
8
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Sample and
Hold
(switched capacitors)
14-Channel
Analog
Multiplexer
12
12
Output
Data
Register
12-to-1 Data
Selector and
Driver
9
11
12
16
DATA
OUT
4
Input Address
Register
4
3
Control Logic
and I/O
Counters
Self-Test
Reference
19
EOC
17
DATA
INPUT
18
15
I/O CLOCK
CS
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
AIN0 – AIN10
1–9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input
voltage into a capacitance of 60 pF.
CS
15
17
16
I
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup
time.
DATA INPUT
DATA OUT
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The
serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After
the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
O
Serial data output. This is the 3-state serial output for the A/D conversion result. DATA OUT is in the
high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed
from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the
previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level
corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC
19
10
18
O
I
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and data are ready for transfer.
GND
Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK
Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
REF+
REF–
14
I
I
Reference+. The upper reference voltage value (nominally V ) is applied to REF+. The maximum input
CC
voltage range is determined by the difference between the voltage applied to this terminal and the voltage
applied to the REF– terminal.
13
20
Reference–. The lower reference voltage value (nominally ground) is applied to REF–.
Positive supply voltage.
V
CC
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS, going low, begins the conversion sequence by enabling I/O CLOCK and DATA
INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7–D4), a 2-bit data length
select (D3–D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are
applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the
input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the
data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle, and 2) the
actual conversion cycle. The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16
clock periods depending on the selected output data length.
1. I/O cycle
During the I/O cycle, two operations take place simultaneously.
a. An8-bitdatastreamconsistingofaddressandcontrolinformationisprovidedtoDATAINPUT. Thisdata
is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after
the first eight clocks during 12- or 16-clock I/O transfers.
b. The data output with a length of 8, 12, or 16 bits is provided serially on DATA OUT. When CS is held low,
thefirstoutputdatabitoccursontherisingedgeofEOC. WhenCSisnegatedbetweenconversions, the
first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion
period, and after the first output data bit each succeeding bit is clocked out on the falling edge of each
succeeding I/O CLOCK.
2. Conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to the
I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on
the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversioniscompleteandtheoutputdataregisterislatched. AconversioncycleisstartedonlyaftertheI/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the
conversion.
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeros. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle.
The first conversion after the device has returned from the power-down state may not read accurately due to
internal device settling.
operational terminology
Previous (N–1) conversion cycle The conversion cycle prior to the current I/O cycle.
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion cycle from DATA OUT. The last falling edge of the clock in
the I/O CLOCK sequence signifies the end of the current I/O cycle.
Current (N) conversion cycle
Immediately after the current I/O cycle, the current conversion cycle starts. When the current conversion
cycle is complete, the current conversion result is loaded into the output register.
Current (N) conversion result
Next (N+1) I/O cycle
The result of the current conversion cycle that is serially shifted out during the next I/O cycle.
The I/O cycle after the current conversion cycle.
Example: Inthe12-bitmode, theresultofthecurrentconversioncycleisa12-bitserial-datastreamclockedoutduring
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion begins
immediately after the twelfth falling edge of the current I/O cycle.
data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data register
format).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
data input (continued)
Table 1. Input-Register Format
INPUT DATA BYTE
ADDRESS BITS
L1
D3
L0
D2
LSBF
D1
BIP
FUNCTION SELECT
D7
D6
D5
D4
D0
(MSB)
(LSB)
Select input channel
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Select test voltage
(V
ref+
– V )/2
ref–
1
1
1
0
1
1
1
0
0
1
0
1
V
ref–
V
ref+
Software power down
1
1
1
0
Output data length
8 bits
0
X
1
1
0
1
12 bits
16 bits
Output data format
MSB first
0
1
LSB first
Unipolar (binary)
0
1
Bipolar (BIP, 2s complement)
data input address bits
The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage,
or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current I/O cycle. The reference voltage is nominally equal to V
– V
.
ref+
ref–
data output length
The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is
valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, which is valid for
the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits
can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial-data stream during the next I/O cycle. The current I/O cycle must be
exactly12bitslongforpropersynchronization, evenwhenthismeanscorruptingtheoutputdatafromaprevious
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit
serial-data stream during the next I/O cycle with the four LSBs always set to 0 (pad bits). The current I/O cycle
must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from
the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the
current I/O cycle.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
data output length (continued)
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial-data stream
during the next I/O cycle. The current I/O cycle must be exactly 8 bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is immediately started after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
Inactualoperation, whendifferentdatalengthsarerequiredwithinanapplicationandthedatalengthischanged
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB first format.
sampling period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
data register, LSB first
D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is set
to 0, the conversion result shifts out MSB first. When set to 1, the data shifts out LSB first. Selection of MSB
first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data
direction to another, the current I/O cycle is never disrupted.
data register, bipolar format
D0 in the input data register controls the binary data format used to represent the conversion result. When D0
is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion
result of an input voltage equal to V
is a code of all zeros (000 . . . 0), the conversion result of an input voltage
ref–
equal to V
is a code of all ones (111 . . . 1), and the conversion result of (V
+ V
)/2 is a code of a one
ref+
ref +
ref–
followed by zeros (100 . . . 0).
When D0 is set to 1, the conversion result is represented as bipolar data (signed binary). Nominally, conversion
of an input voltage equal to V is a code of a 1 followed by zeros (100 . . . 0), conversion of an input voltage
ref–
equal to V
is a code of a 0 followed by all ones (011 . . . 1), and the conversion of (V
+ V
)/2 is a code
ref+
ref+
ref–
of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar
format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
EOC output
TheEOCsignalindicatesthebeginningandtheendofconversion. Intheresetstate, EOCisalwayshigh. During
the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high
until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs
after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input
data register. After the EOC signal goes low, the analog input signal can be changed without affecting the
conversion result.
The EOC signal goes high again after the conversion completes and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the
falling edge of CS.
data format and pad bits
D3 and D2 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines
the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.
When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on
the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes
low and the serial output is forced to a logic zero until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.
On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next
bit in the serial conversion result until the required number of bits has been output.
chip-select input (CS)
The chip-select input (CS) enables and disables the device. During normal operation, CS should be low.
Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between
conversions to coordinate the data transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, the I/O
CLOCK is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can be used to interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low
long enough before the end of the current conversion cycle, the previous conversion result is saved in the
internal output buffer and then shifted out during the next I/O cycle.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
power-down features
When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles,
the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.
During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,
and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs
are held above V
– 0.3 V or below 0.3 V. The I/O logic remains active so the current I/O cycle must be
CC
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the power-down mode until a
valid (other than 1110) input address clocks in. Upon completion of that I/O cycle, a normal conversion is
performed with the results being shifted out during the next I/O cycle.
analog input, test, and power-down mode
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held
on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer,
sampled, and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
Table 2. Analog-Channel-Select Address
VALUE SHIFTED INTO
ANALOG INPUT
DATA INPUT
SELECTED
BINARY
0000
0001
0010
0011
0100
0101
0110
0111
HEX
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
1
2
3
4
5
6
7
1000
1001
1010
8
9
A
Table 3. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
VALUE SHIFTED INTO
UNIPOLAR OUTPUT
RESULT (HEX)
DATA INPUT
‡
†
BINARY HEX
SELECTED
V
ref+
– V
2
ref–
1011
B
200
V
1100
1101
C
D
000
3FF
ref–
V
ref+
†
‡
V
is the voltage applied to REF+, and V
is the voltage applied to REF–.
ref+
ref–
The output results shown are the ideal values and may vary with the reference stability
and with internal offsets.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
analog input, test, and power-down mode (continued)
Table 4. Power-Down-Select Address
VALUE SHIFTED INTO
DATA INPUT
INPUT COMMAND
RESULT
BINARY
HEX
Power down
1110
E
I
≤ 25 µA
CC
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S switch and all S switches simultaneously.
C
T
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S and S switches are opened and the threshold detector
T
C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. When the voltage at the
summing node is greater than the trip point of the threshold detector (approximately one-half V ), a bit 0 is
CC
placed in the output register and the 4096-weight capacitor is switched to REF–. When the voltage at the
summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the
4096-weight capacitor remains connected to REF+ through the remainder of the successive-approximation
process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down
the line until all bits are determined. With each step of the successive-approximation process, the initial charge
is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the
bits from MSB to LSB.
S
C
Threshold
Detector
To Output
Latches
4096
Node 4096
2048
1024
16
8
4
2
1
1
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
T
S
S
S
S
S
S
S
S
S
T
T
T
T
T
T
T
T
V
I
Figure 1. Simplified Model of the Successive-Approximation System
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
reference voltage inputs
There are two reference voltage inputs on the device, REF+ and REF–. The voltage values on these terminals
establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading
respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower than REF–
terminal voltage.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.1 V
I
CC
CC
CC
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Positive reference voltage, V
Negative reference voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
ref+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V
ref–
Peak input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, T : TLV2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
3.3
3.6
Positive reference voltage, V
ref+
(see Note 2)
(see Note 2)
– V (see Note 2)
V
V
V
CC
0
Negative reference voltage, V
ref–
V
Differential reference voltage, V
ref+
2.5
0
V +0.1
CC
V
ref–
CC
Analog input voltage (see Note 2)
High-level control input voltage, V
V
CC
V
V
V
= 3 V to 3.6 V
= 3 V to 3.6 V
2.1
V
IH
CC
Low-level control input voltage, V
Clock frequency at I/O CLOCK
0.6
4.1
V
IL
CC
0
100
0
3
MHz
ns
ns
ns
µs
ns
ns
µs
µs
Setup time, address bits at DATA INPUT before I/O CLOCK↑, t
(see Figure 5)
su(A)
(see Figure 5)
Hold time, address bits at DATA INPUT after I/O CLOCK↑, t
h(A)
(see Figure 6)
Hold time, CS low after last I/O CLOCK↓, t
h(CS)
Setup time, CS low before clocking in first address bit, t
0
(see Note 3 and Figure 6)
1.425
190
190
su(CS)
Pulse duration, I/O CLOCK high, t
wH(I/O)
Pulse duration, I/O CLOCK low, t
wL(I/O)
Transition time, I/O CLOCK, t
t(I/O)
Transition time, DATA INPUT and CS, t
(see Note 4 and Figure 7)
t(CS)
1
10
70
85
TLV2543C
TLV2543I
0
Operating free-air temperature, T
°C
A
–40
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control
input signals. No attempt should be made to clock in an address until the minimum CS setup time elapses.
4. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity of
IH
IL
IL
IH
normalroomtemperature, thedevicesfunctionwithinputclocktransitiontimeasslowas1µsforremotedataacquisitionapplications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
11
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TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 3 V to 3.6 V (unless otherwise noted)
CC
ref+
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
V
= 3 V,
I
I
I
I
= –0.2 mA
= –20 µA
= 0.8 mA
= 20 µA
2.4
CC
CC
CC
CC
OH
OH
OL
OL
V
High-level output voltage
V
OH
= 3 V to 3.6 V,
= 3 V,
V
CC
–0.1
0.4
V
OL
Low-level output voltage
V
= 3 V to 3.6 V,
0.1
1
= V
CC
= 0,
,
CS at V
CS at V
2.5
–2.5
2.5
Off-state (high-impedance-state)
output current
O
O
CC
CC
I
µA
OZ
1
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
I CC
1
µA
µA
IH
V = 0
I
1
–2.5
2.5
IL
CS at 0 V
For all digital inputs,
0 ≤ V ≤ 0.3 V or V ≥ V – 0.3 V
CC
1
mA
CC
I
Power-down current
4
25
µA
µA
µA
pF
CC(PD)
lkg
I
I
Selected channel at V , Unselected channel at 0 V
CC
1
Selected channel leakage
current
I
Selected channel at 0 V, Unselected channel at V
CC
–1
Maximum static analog
reference current into REF+
V
ref+
= V
,
V = GND
ref–
1
2.5
CC
Analog inputs
Control inputs
30
5
60
15
Input
capacitance
C
i
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
operating characteristics over recommended operating free-air temperature range,
= V = 3 V to 3.6 V, I/O CLOCK frequency = 4.1 MHz, (unless otherwise noted)
V
CC
ref+
†
PARAMETER
Linearity error (see Note 6)
Differential linearity error
TEST CONDITIONS
See Figure 2
MIN TYP
MAX
±1
UNIT
LSB
LSB
E
L
E
D
See Figure 2
±1
E
E
E
See Note 2 and
Figure 2
O
Offset error (see Note 7)
±1.5
±1
LSB
See Note 2 and
Figure 2
G
T
Gain error (see Note 7)
LSB
LSB
Total unadjusted error (see Note 8)
±1.75
2058
10
DATA INPUT = 1011
DATA INPUT = 1100
DATA INPUT = 1101
See Figures 10–15
2038
4075
2048
0
Self-test output code (see Table 3 and Note 9)
Conversion time
4095
8
t
t
10
µs
µs
(conv)
10 + total
I/O CLOCK
periods +
See Figures 10–15
and Note 10
Total cycle time (access, sample, and conversion)
c
t
d(I/O-EOC)
I/O
CLOCK
periods
See Figures 10–15
and Note 10
t
Channel acquisition time (sample)
4
12
acq
t
t
t
t
t
t
t
t
t
t
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, last I/O CLOCK↓ to EOC↓
Delay time, EOC↑ to DATA OUT (MSB/LSB)
Enable time, CS↓ to DATA OUT (MSB/LSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
See Figure 7
See Figure 7
See Figure 8
See Figure 9
See Figure 4
See Figure 4
See Figure 9
See Figure 8
See Figure 7
See Figure 7
10
ns
ns
µs
ns
µs
ns
ns
ns
ns
ns
v
250
2.2
200
1.3
150
50
d(I/O-DATA)
d(I/O-EOC)
1.5
d(EOC-DATA)
, t
PZH PZL
0.7
70
15
15
15
15
, t
PHZ PLZ
r(EOC)
f(EOC)
r(bus)
f(bus)
Fall time, EOC
50
Rise time, data bus
50
Fall time, data bus
50
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 11)
t
5
µs
d(I/O-CS)
†
All typical values are at T = 25°C.
A
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF– convert as all zeros (000000000000).
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 7).
11. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure that a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to
whether the conversion is aborted or the conversion results are valid.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
15 V
50 Ω
C1
10 µF
C2
0.1 µF
C3
470 pF
TLV2543
_
U1
+
10 Ω
AIN0–AIN10
V
I
C1
10 µF
C3
470 pF
C2
0.1 µF
50 Ω
–15 V
LOCATION
DESCRIPTION
PART NUMBER
U1
C1
C2
C3
OP27
—
—
10-µF 35-V tantalum capacitor
0.1-µF ceramic NPO SMD capacitor
AVX 12105C104KA105 or equivalent
470-pF porcelain high-Q SMD capacitor
Johanson 201S420471JG4L or equivalent
Figure 2. Analog Input Buffer to Analog Inputs AIN0–AIN10
I
source
0.8 mA
Test Point
See Note A
Output
Under Test
V
cp
= 2 V
C
= 100 pF
L
I
sink
–0.2 mA
NOTE A: Equivalent load circuit of the Teradyne A580 tester for timing
parameter measurement.
Figure 3. Timing Load Circuits
Data
Valid
2 V
2 V
0.8 V
CS
DATA INPUT
I/O CLOCK
0.8 V
t
, t
PZH PZL
t
h(A)
t
, t
PHZ PLZ
t
su(A)
2.4 V
0.4 V
90%
10%
DATA
OUT
0.8 V
Figure 5. DATA INPUT and I/O CLOCK
Voltage Waveforms
Figure 4. DATA OUT to Hi-Z Voltage Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
2 V
CS
0.8 V
t
su(CS)
0.8 V
t
h(CS)
I/O CLOCK
Last
Clock
0.8 V
†
Figure 6. CS and I/O CLOCK Voltage Waveforms
†
To ensure full conversion accuracy, it is recommended that no input signal change occurs while
a conversion is ongoing.
t
t(I/O)
t
t(I/O)
2 V
2 V
0.8 V
I/O CLOCK
0.8 V
0.8 V
I/O CLOCK Period
t
d(I/O-DATA)
t
v
2.4 V
0.4 V
2.4 V
0.4 V
DATA OUT
t
, t
r(bus) f(bus)
Figure 7. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last
0.8 V
Clock
t
d(I/O-EOC)
2.4 V
EOC
0.4 V
t
f(EOC)
Figure 8. I/O CLOCK and EOC Voltage Waveforms
t
r(EOC)
EOC
2.4 V
0.4 V
t
d(EOC-DATA)
2.4 V
0.4 V
DATA OUT
Valid MSB
Figure 9. EOC and DATA OUT Voltage Waveforms
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
Sample Cycle B
Hi-Z State
DATA
OUT
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
B11
Previous Conversion Data
MSB
LSB
DATA
INPUT
C7
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
(conv)
A/D Conversion
Interval
Initialize
Initialize
Figure 10. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
Sample Cycle B
DATA
OUT
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
B11
Low Level
Previous Conversion Data
MSB
LSB
DATA
INPUT
B7
B6
B5
B4
C7
B3
B2
B1
B0
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
(conv)
A/D Conversion
Interval
Initialize
Initialize
Figure 11. Timing for 12-Clock Transfer Not Using CS With MSB First
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
1
2
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
Access Cycle B
Sample Cycle B
Hi-Z
A7
A6
A5
A4
A3
A2
A1
A0
B7
Previous Conversion Data
MSB
LSB
B0
DATA INPUT
B3
B2
B1
B7
B6
B5
B4
C7
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
(conv)
A/D Conversion
Interval
Initialize
Initialize
Figure 12. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
1
2
3
4
5
6
7
8
1
I/O CLOCK
Access Cycle B
Sample Cycle B
A7
A6
A5
A4
A3
A2
A1
A0
B7
Low Level
DATA OUT
Previous Conversion Data
MSB
LSB
B0
DATA INPUT
B7
B6
B5
B4
C7
B3
B2
B1
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
(conv)
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB First
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrol
input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
15
16
1
Access Cycle B
Sample Cycle B
Hi-Z State
DATA
OUT
A15
A14
A13
A12
A11
A10
A9
A8
B0
A1
A0
B15
Previous Conversion Data
MSB
LSB
DATA
INPUT
B7
B6
B5
B4
B3
B2
B1
C7
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
(conv)
A/D Conversion
Interval
Initialize
Initialize
Figure 14. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
15
16
1
Access Cycle B
Sample Cycle B
DATA
OUT
Low Level
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
B15
Previous Conversion Data
MSB
LSB
DATA
INPUT
B3
B2
B1
B0
B7
B6
B5
B4
C7
MSB
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t
(conv)
A/D Conversion
Interval
Initialize
Figure 15. Timing for 16-Clock Transfer Not Using CS With MSB First
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
4095
4094
4093
111111111111
111111111110
111111111101
V
FS
See Notes A and B
V
FSnom
V
FT
= V
– 1/2 LSB
FS
2049
2048
100000000001
100000000000
V
ZT
= V
+ 1/2 LSB
ZS
2047
011111111111
V
ZS
2
1
0
000000000010
000000000001
000000000000
0
0.0008 0.0016
1.6376 1.6384 1.6392
V – Analog Input Voltage – V
3.2752
3.2760 3.2768
I
NOTES: A. This curve is based on the assumption that V
ref+
and V have been adjusted so that the voltage at the transition from digital 0
ref–
to 1 (V ) is 0.0004 V and the transition to full scale (V ) is 3.2756 V. 1 LSB = 0.8 mV.
ZT FT
B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is
FS
ZS
the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
TLV2543
15
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
CS
18
17
2
I/O CLOCK
3
DATA INPUT
Control
Circuit
4
Processor
5
16
19
DATA OUT
EOC
6
Analog
Inputs
7
8
9
14
13
3-V DC Regulated
REF+
REF–
11
12
GND
10
To Source
Ground
Figure 17. Serial Interface
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by
–t R C
(1)
c
t
i
V
V
1–e
C
S
Where:
R = R + r
t
s
i
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /8192)
(2)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t R C
c
t
i
V
V
58192
V
1–e
(3)
(4)
S
S
S
and
t (1/2 LSB) = R × C × ln(8192)
c
t
i
Therefore, with the values given the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(8192)
(5)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLV2543
R
r
i
s
V
I
V
S
V
C
1 kΩ MAX
C
i
50 pF MAX
V
V
= Input Voltage at AIN
= External Driving Source Voltage
I
S
s
R = Source Resistance
r
= Input Resistance
i
C = Input Capacitance
i
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 18. Equivalent Input Circuit Including the Driving Source
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
A
PINS **
14
16
18
20
16
9
DIM
0.775
0.775
0.920
0.975
A MAX
(19,69) (19,69) (23.37) (24,77)
0.260 (6,60)
0.240 (6,10)
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21.59) (23,88)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
0.125 (3,18) MIN
Seating Plane
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14 Pin Only
4040049/C 7/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
TLV2543CDB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2543CDBG4
TLV2543CDBR
TLV2543CDBRG4
TLV2543CDW
TLV2543CDWG4
TLV2543CDWR
TLV2543CDWRG4
TLV2543CN
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SSOP
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DB
DB
DB
DW
DW
DW
DW
N
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2543CNE4
TLV2543IDB
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DB
DB
DB
DB
DW
DW
DW
DW
N
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2543IDBG4
TLV2543IDBR
TLV2543IDBRG4
TLV2543IDW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2543IDWG4
TLV2543IDWR
TLV2543IDWRG4
TLV2543IN
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2543INE4
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLV2543CDBR
TLV2543IDBR
SSOP
SSOP
DB
DB
20
20
2000
2000
330.0
330.0
16.4
16.4
8.2
8.2
7.5
7.5
2.5
2.5
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2543CDBR
TLV2543IDBR
SSOP
SSOP
DB
DB
20
20
2000
2000
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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