TLV2401-Q1 [TI]
汽车级、单路、16V、5.5kHz 运算放大器;
| 型号： | TLV2401-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、单路、16V、5.5kHz 运算放大器 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：1578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV2401-Q1, TLV2402-Q1
SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
TLV2401-Q1, TLV2402-Q1 16-V, Ultra-Low Power, 880-nA, RRIO Operational Amplifiers
With Reverse Battery Protection
The low supply current is coupled with extremely low
input bias currents enabling them to be used with
mega-Ω resistors making them ideal for portable, long
active-life applications. DC accuracy is ensured with a
low typical offset voltage of 390 µV, CMRR of 120 dB
and minimum open loop gain of 130 V/mV at 2.7 V.
1 Features
1
•
AEC-Q100 qualified for automotive applications
–
Device temperature grade 1:
–40°C to 125°C TA
•
•
Nano-power operation: 880 nA/channel
Input common-mode range exceeds the rails: –0.1
V to VCC + 5 V
The supply voltage extends from 2.5 V to 16 V, with
electrical characteristics specified at 2.7 V, 5 V, and
15 V. The 2.5-V operation makes it compatible with
Li-Ion battery-powered systems and many micro-
power microcontrollers including TI’s MSP430 and
MSP432.
•
•
•
•
•
Reverse battery protection up to 18 V
Rail-to-rail input or output
Gain bandwidth product: 5.5 kHz
Wide supply voltage range: 2.5 V to 16 V
Industry standard packaging
The single channel TLV2401-Q1 is available in a 5-
pin SOT-23 package, and the dual channel TLV2402-
Q1 is available in an 8-pin VSSOP. Both packages
are fully specified from –40°C to 125°C.
–
–
5-pin SOT-23 (TLV2401-Q1)
8-pin MSOP (TLV2402-Q1)
Device Information(1)
2 Applications
PART NUMBER
TLV2401-Q1
PACKAGE
SOT-23 (5)
VSSOP (8)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
•
•
•
•
•
•
Hybrid, electric, and power train systems
DC/DC converter
TLV2402-Q1
On-board charger (OBC) and wireless charger
Fuel cell and gasoline engine
Inverter and motor control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Operational Amplifier
Telematics control unit
3 Description
The TLV240x-Q1 (TLV2401-Q1 and TLV2402-Q1) is
a
family of high voltage (16-V) nano-power
operational amplifiers (op amps). The TLV240x-Q1
has an impressively low quiescent current of just 880
nA (typical) and is ideal for battery-powered or
"always-on" applications, such as electric vehicle
monitoring and protection applications. Reverse
battery protection guards the amplifier from an
overcurrent condition due to improper battery
installation. For harsh environments, the inputs can
be taken 5 V above the positive supply rail without
damage to the device.
Supply Current vs Supply Voltage
1.4
A
V
= 1
V
= V
/ 2
CC
1.2
1.0
0.8
0.6
0.4
0.2
0
IN
= 25 °C
T
A
0
2
4
6
8
10 12 14 16
Supply Voltage, V (V)
CC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV2401-Q1, TLV2402-Q1
SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information for Single Channel ................... 5
6.5 Thermal Information for Dual Channel...................... 5
6.6 Electrical Characteristics........................................... 6
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 22
11.1 Device Support...................................................... 22
11.2 Related Links ........................................................ 22
11.3 Support Resources ............................................... 22
11.4 Trademarks........................................................... 22
11.5 Electrostatic Discharge Caution............................ 22
11.6 Glossary................................................................ 22
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2011) to Revision A
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Removed TLV2404-Q1 information from the data sheet........................................................................................................ 1
Changed TLV2401-Q1 information from Preview to Active.................................................................................................... 1
•
•
2
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Product Folder Links: TLV2401-Q1 TLV2402-Q1
TLV2401-Q1, TLV2402-Q1
www.ti.com
SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
5 Pin Configuration and Functions
TLV2401-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
Vœ
1
2
3
5
V+
IN+
4
INœ
Not to scale
Table 1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN+
IN–
I
Noninverting input
4
I
Inverting input
Output
OUT
V+
1
O
—
—
5
Positive (high) supply
V–
2
Negative (low) supply or ground (for single-supply operation)
TLV2402-Q1 DGK Package
8-Pin VSSOP
Top View
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
Table 2. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN1–
IN2+
IN2–
OUT1
OUT2
V+
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Output, channel 1
2
5
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (high) supply
V–
4
Negative (low) supply or ground (for single-supply operation)
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SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
0
MAX
17
UNIT
V
Supply voltage, VS = (V+) – (V–)
Differential voltage(2)
Current(2)
–20
20
V
Input pins
–10
10
mA
Output short-circuit(3)
Continuous
–40
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
125
150
150
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic discharge Machine-model (MM)
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
±200
V
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.5
MAX
UNIT
V
Single supply
Split supply
16
±8
VS
Supply voltage, (V+) – (V–)
±1.25
V
VI
Input voltage range
(V–) – 0.1
–40
(V+) + 5
125
V
TA
Specified temperature
°C
4
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SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
6.4 Thermal Information for Single Channel
TLV2401-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
324.1
55
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
TBD
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TBD
ψJB
TBD
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for Dual Channel
TLV2402-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
259.9
54.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
TBD
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TBD
ψJB
TBD
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
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6.6 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 500 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
390
±1950
±2800
VOS
Input offset voltage
RS = 50 Ω
RS = 50 Ω
µV
TA = –40°C to 125°C
TA = –40°C to 125°C
Input offset voltage
drift
dVOS/dT
±3
µV/℃
TLV2401-Q1
±1
±1
±15
±10
±70
±10
VCC = 2.7 V to 5 V
TLV2402-Q1
TA = –40°C to 125°C
Power supply rejection
ratio
±1
PSRR
No load
μV/V
TLV2401-Q1, TA
–40°C to 125°C
=
=
±35
±14
VCC = 5 V to 15 V
TLV2402-Q1, TA
–40°C to 125°C
INPUT BIAS CURRENT
±100
±100
±25
±1000
±4000
±300
TLV2401-Q1
TLV2402-Q1
TLV2401-Q1
TLV2402-Q1
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
IB
Input bias current
RS = 50 Ω
pA
pA
±900
±1000
±1500
±250
IOS
Input offset current
RS = 50 Ω
±25
±400
NOISE
eN
f = 10 Hz
f = 100 Hz
f = 1 kHz
800
500
8
Input voltage noise
density
nV/√Hz
fA/√Hz
iN
Input current noise
INPUT VOLTAGE RANGE
Common-mode
VCM
(V–) –
0.1
(V+) + 5
V
voltage range
56
54
62
58
71
68
60
56
65
58
73
73
100
106
112
120
120
120
VS = 2.7 V, (V–) < VCM
< (V+), RS = 50 Ω
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
VS = 5 V, (V–) < VCM
<
TLV2401-Q1
(V+), RS = 50 Ω
VS = 15 V, (V–) < VCM
(V+), RS = 50 Ω
<
Common-mode
CMRR
dB
rejection ratio
VS = 2.7 V, (V–) < VCM
< (V+), RS = 50 Ω
VS = 5 V, (V–) < VCM
<
TLV2402-Q1
(V+), RS = 50 Ω
VS = 15 V, (V–) < VCM
(V+), RS = 50 Ω
<
INPUT CAPACITANCE
Differential input
resistance
RID
300
3
MΩ
Common-mode input
capacitance
CICM
pF
6
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SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 500 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
112
120
125
112
120
125
MAX
UNIT
OPEN-LOOP GAIN
91
72
VS = 2.7 V, VO(pp) = 1 V
VS = 5 V, VO(pp) = 1 V(1)
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
100
94
TLV2401-Q1
106
98
VS = 15 V, VO(pp) = 6
V(1)
Open-loop voltage
gain
AOL
dB
102
81
VS = 2.7 V, VO(pp) = 1 V
VS = 5 V, VO(pp) = 1 V
VS = 15 V, VO(pp) = 6 V
109
91
TLV2402-Q1
120
96
FREQUENCY RESPONSE
Gain-bandwidth
product
GBW
RL = 500 kΩ, CL = 100 pF
5.5
2.5
kHz
SR
Slew rate
V/ms
VS = 2.7 V or 5 V, VSTEP = 1 V, G = –1, CL = 100
pF, RL = 100 kΩ
To 0.1%
1.84
tS
Settling time
ms
To 0.1%
6.1
32
60
15
VS = 15 V, VSTEP = 1 V, G = –1, CL = 100 pF, RL
100 kΩ
=
To 0.01%
Phase margin
Gain margin
°
G = +1, RL = 10 kΩ, CL = 20 pF
dB
OUTPUT
2.65
2.63
4.95
4.93
14.95
14.93
2.62
2.6
2.68
4.98
14.98
2.65
4.95
14.95
90
VCC = 2.7 V
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
VCM = VCC / 2, IOH = –2
µA
VCC = 5 V(1)
VCC = 15 V(1)
VCC = 2.7 V
High-level output
voltage
VOH
V
4.92
4.9
VCM = VCC / 2, IOH = –50
µA
VCC = 5 V(1)
14.92
14.9
VCC = 15 V(1)
150
180
230
260
VCM = VCC / 2, IOL = 2 µA(1)
Low-level output
voltage
VOL
mV
µA
180
VCM = VCC / 2, IOL = 50 µA(1)
VO = 0.5 V from rail
ISC
Short-circuit current
±200
(1) Assured by design and characterization only. This condition applies for TLV2401-Q1 only.
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Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 500 kΩ connected to VS / 2, VCM = VS / 2, and VOUT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
880
900
880
900
MAX
UNIT
POWER SUPPLY
1050
1400
1050
1550
990
VCC = 2.7 V or 5 V, IO
0 A
=
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TLV2401-Q1
TLV2402-Q1
VCC = 15 V, IO = 0 A
Quiescent current per
amplifier
IQ
nA
nA
VCC = 2.7 V or 5 V, IO
0 A
=
1300
1050
1400
VCC = 15 V, IO = 0 A
Reverse supply
current
VCC = –18 V, VIN = 0 V, RL = ∞
50
8
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SLOS716A –APRIL 2011–REVISED FEBRUARY 2020
6.7 Typical Characteristics
100
0
1400
V
T
= 2.7 V
CC
= 25°C
1200
1000
800
600
400
200
0
A
–100
–200
–300
–400
V
T
= 5 V
CC
= 25 °C
A
–200
–0.1 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9
Common-Mode Input Voltage, V (V)
–0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
Common-Mode Input Voltage, V (V)
ICR
ICR
Figure 1. Input Offset Voltage vs Common-Mode Input
Voltage
Figure 2. Input Offset Voltage vs Common-Mode Input
Voltage
400
600
V
T
= 15 V
CC
= 25 °C
V
V
= 2.7 V
CC
= 1.35 V
300
200
500
400
300
200
100
0
A
IC
100
0
–100
–200
–300
–400
I
IO
I
IB
–100
–200
–0.1 2.0
4.2 6.4 8.6 10.8 13.0 15.2
(V)
–40 –25 –10
5
20 35 50 65 80 95 110 125
Common-Mode Input Voltage, V
Free-Air Temperature, T (°C)
A
ICR
Figure 3. Input Offset Voltage vs Common-Mode Input
Voltage
Figure 4. Input Bias and Offset Current vs Free-Air
Temperature
400
350
600
V
V
= 5 V
CC
= 2.5 V
V
T
= 2.7 V
CC
= 25 °C
500
400
300
200
100
0
IC
A
300
250
200
150
100
50
I
IO
I
IO
0
–50
–100
–150
I
IB
I
IB
–100
–200
–0.1 0.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9
Common-Mode Input Voltage, V (V)
–40 –25 –10
5
20 35 50 65 80 95 110 125
Free-Air Temperature, T (°C)
A
ICR
Figure 5. Input Bias and Offset Current vs Common-Mode
Voltage
Figure 6. Input Bias and Offset Current vs Free-Air
Temperature
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Typical Characteristics (continued)
200
700
600
500
400
300
200
100
0
V
V
= 15 V
CC
= 7.5 V
V
T
= 5 V
CC
= 25 °C
150
100
50
IC
A
I
IO
0
I
IO
–50
–100
–150
I
IB
–100
I
IB
–200
–0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
Common-Mode Input Voltage, V (V)
–40 –25 –10
5
20 35 50 65 80 95 110 125
Free-Air Temperature, T (°C)
ICR
A
Figure 7. Input Bias and Offset Current vs Common-Mode
Voltage
Figure 8. Input Bias and Offset Current vs Free-Air
Temperature
250
120
V
T
= 15 V
CC
= 25 °C
200
150
100
50
100
80
60
40
20
0
A
I
IO
0
–50
–100
–150
I
IB
–0.1
2.0
4.2
6.4
8.6 10.8 13.0 15.2
(V)
1
10
100
Frequency, f (Hz)
1k
10k
Common-Mode Input Voltage, V
ICR
Figure 9. Input Bias and Offset Current vs Common-Mode
Input Voltage
Figure 10. Common-Mode Rejection Ratio vs Frequency
2.7
1.50
V
T
= 2.7 V
CC
V
= 2.7 V
CC
1.25
1.00
0.75
0.50
0.25
0
= 25 °C
= 0 °C
A
2.4
2.1
1.8
1.5
1.2
T
A
T
A
= –40°C
T
= –40°C
A
T
= –0°C
A
T
= 25 °C
= 70 °C
= 125 °C
A
T
= 70 °C
A
T
A
T
= 125 °C
A
T
A
0
100
150
OH
200
50
0
100
150
200
50
High-Level Output Current, I
(mA)
Low-Level Output Current, I (mA)
OL
Figure 11. High-Level Output Voltage vs High-Level Output
Current
Figure 12. Low-Level Output Voltage vs Low-Level Output
Current
10
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Typical Characteristics (continued)
5.0
1.50
1.25
1.00
0.75
0.50
0.25
0
V
T
= 5 V
CC
V
= 5 V
CC
T
= –40°C
A
= 0 °C
A
4.5
4.0
3.5
3.0
T
= –40°C
A
T
= –0°C
A
T
= 25 °C
= 70 °C
= 125 °C
A
T
A
T
A
T
A
= 25 °C
= 70 °C
= 125 °C
T
A
T
A
0
100
150
200
50
0
100
150
200
50
High-Level Output Current, I
(mA)
Low-Level Output Current, I (mA)
OL
OH
Figure 13. High-Level Output Voltage vs High-Level Output
Current
Figure 14. Low-Level Output Voltage vs Low-Level Output
Current
15.0
1.50
V
= 15 V
CC
1.25
1.00
0.75
0.50
0.25
0
14.5
T
A
= –40°C
T
= –0°C
T
= –0°C
A
A
T
= 25 °C
= 70 °C
= 125 °C
T
= 25 °C
= 70 °C
= 125 °C
14.0
13.5
13
A
A
T
T
A
A
T
T
A
A
T
= –40°C
A
V
= 15 V
CC
0
100
150
200
0
100
150
OL
200
50
50
High-Level Output Current, I
(mA)
Low-Level Output Current, I (mA)
OH
Figure 15. High-Level Output Voltage vs High-Level Output
Current
Figure 16. Low-Level Output Voltage vs Low-Level Output
Current
10k
16
14
12
10
8
V
= 15 V
CC
AV = 10
1k
AV = 1
6
R
C
T
= 100 kΩ
= 100 pF
= 25°C
L
L
4
V
= 5 V
CC
100
2
A
V
= 2.7 V
CC
V
T
= 2.7, 5, & 15 V
CC
= 25°C
0
A
10
100
1k
10k
100
1k
Frequency, f (Hz)
10k
Frequency, f (Hz)
Figure 18. Output Impedance vs Frequency
Figure 17. Output Voltage Peak-to-Peak vs Frequency
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Typical Characteristics (continued)
1.4
120
110
100
90
V
T
= 2.7, 5, & 15 V
CC
1.2
1.0
0.8
0.6
= 25°C
A
80
T
= 125°C
= 70 °C
= 25 °C
= 0 °C
A
70
T
A
0.4
0.2
0
T
A
60
T
A
T
= –40°C
A
V
= 1
50
A
V
= V
/ 2
CC
IN
40
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
1
10
100
1k
10k
Supply Voltage, V (V)
CC
Frequency, f (Hz)
Figure 19. Supply Current vs Supply Voltage
Figure 20. Power Supply Rejection Ratio vs Frequency
7
60
135
T
= 25°C
A
50
R
C
= 100 kΩ
= 100 pF
L
6
5
4
3
2
1
0
L
40
30
20
10
90
f = 1 kHz
45
0
0
V
= 2.7, 5, & 15 V
= 500 kΩ
= 100 pF
= 25°C
CC
L
L
R
C
T
–10
A
–20
–45
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
100
1k
10k
10
Frequency, f (Hz)
Supply Voltage, V (V)
CC
Figure 21. Differential Voltage Gain and Phase vs Frequency
Figure 22. Gain Bandwidth Product vs Supply Voltage
3.5
80
70
60
50
40
30
3.0
2.5
2.0
1.5
1.0
0.5
0
SR+
V
= 5, 15 V
CC
V
= 2.7 V
CC
V
= 2.7, 5, & 15 V
CC
V
= 2.7, 5, & 15 V
= 500 kΩ
SR–
CC
20
10
0
R
T
L
= 25°C
A
100
1k
10k
–40 –25 –10
5
20 35 50 65 80 95 110 125
10
Free-Air Temperature, T (°C)
A
Capacitive Load, C (pF)
L
Figure 23. Slew Rate vs Free-Air Temperature
Figure 24. Phase Margin vs Capacitive Load
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Typical Characteristics (continued)
60
55
25
R
T
= 500 kΩ
= 25°C
L
T
= 25°C
A
A
50
45
40
20
15
10
5
V
= 15 V
CC
35
30
25
20
15
10
V
= 2.7 & 5 V
CC
5
0
0
–18 –16 –14 –12 –10 –8 –6 –4 –2
0
100
1k
10k
10
Reverse Voltage, V (V)
CC
Capacitive Load, C (pF)
L
Figure 26. Supply Current vs Reverse Voltage
Figure 25. Gain Margin vs Capacitive Load
4
2
V
= 5 V
CC
f = 0.1 Hz to 10 Hz
= 25°C
3
T
A
1
0
V
IN
2
1
V
A
= 2.7 V
CC
= 1
V
0
2
–1
R
= 100 kΩ
= 100 pF
= 25°C
L
L
C
T
–1
–2
–3
–4
1
A
V
O
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
Time, t (s)
Time, t (ms)
Figure 27. 0.1 Hz to 10 Hz Voltage Noise
Figure 28. Large Signal Follower Pulse Response
15
4
3
2
8
7
V
A
= 15 V
CC
V
A
= 5 V
CC
= 1
15
10
5
V
10
5
= 1
V
R
= 100 kΩ
= 100 pF
= 25°C
V
L
L
V
IN
R
= 100 kΩ
= 100 pF
= 25°C
IN
L
L
6
C
T
C
T
A
5
1
0
A
0
4
–5
3
–1
V
2
O
V
O
1
0
0
0
2
4
6
8
10 12 14 16
0
1
2
3
4
5
6
Time, t (ms)
Time, t (ms)
Figure 30. Large Signal Follower Pulse Response
Figure 29. Large Signal Follower Pulse Response
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Typical Characteristics (continued)
Time, t (ms)
Time, t (ms)
Figure 32. Large Signal Follower Pulse Response
Figure 31. Small Signal Follower Pulse Response
Time, t (ms)
Time, t (ms)
Figure 34. Large Signal Follower Pulse Response
Figure 33. Large Signal Follower Pulse Response
Time, t (ms)
Frequency, f (Hz)
Figure 35. Small Signal Follower Pulse Response
Figure 36. Crosstalk
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7 Detailed Description
7.1 Overview
The TLV240x-Q1 (TLV2401-Q1 and TLV2402-Q1) is a family of high voltage (16-V) general purpose operational
amplifiers (op amps). The TLV240x-Q1 has an impressively low quiescent current of just 880 nA (typ) and is
ideal for battery-powered or "always-on" applications, such as electric vehicle monitoring and protection
applications. Reverse battery protection guards the amplifier from an overcurrent condition due to improper
battery installation. For harsh environments, the inputs can be taken 5 V above the positive supply rail without
damage to the device.
The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-Ω
resistors making them ideal for portable, long active-life applications. DC accuracy is ensured with a low typical
offset voltage as low as 390 µV, CMRR of 120 dB and minimum open loop gain of 130 V/mV at 2.7 V.
The maximum recommended supply voltage is as high as 16 V and ensured operation down to 2.5 V, with
electrical characteristics specified at 2.7 V, 5 V and 15 V. The 2.5-V operation makes it compatible with Li-Ion
battery-powered systems and many micro-power microcontrollers including TI’s MSP430 and MSP432.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Reverse Battery Protection
The TLV240x-Q1 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery
condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This
current is determined by the leakage of 6 Schottky diodes; and therefore, increases as the ambient temperature
increases.
When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input
ESD structure turns on—this current should be limited to less than 10 mA. If the inputs or outputs are referred to
ground, rather than midrail, no extra precautions need be taken.
7.3.1.1 Common-Mode Input Range
The TLV240x-Q1 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V a PNP
differential pair provides the gain.
For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair
provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above
the rails, because as the inputs go above VCC, the NPNs switch from functioning as transistors to functioning as
diodes. This leads to an increase in input bias current. The second PNP differential pair continues to function
normally as the inputs exceed VCC
.
The TLV240x-Q1 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken
much below this, reduced open loop gain is observed with the ultimate possibility of phase inversion.
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Feature Description (continued)
7.3.2 Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
R
F
I
IB–
R
G
+
–
V
V
O
I
+
R
S
I
IB+
R
R
R
R
F
F
V
V
1
I
R
1
I
R
OO
IO
IB
S
IB–
F
G
G
Figure 37. Output Offset Voltage Model
7.4 Device Functional Modes
The TLV240x-Q1 has a single functional mode. The devices are powered on as long as the power supply voltage
is between 2.5 V (±1.25 V) and 16 V (±8 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required
to maximize accuracy. A low-pass filter using different topologies can offer circuit designers the flexibility to
design their circuit optimally.
8.2 Typical Application
The simplest way to accomplish this a low-pass filter is to place an RC filter at the non-inverting terminal of the
amplifier (see Figure 38). If even more attenuation is needed, a multiple pole filter is required. The Figure 39 can
be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter
frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
R
R
F
G
–
V
1
O
+
V
I
R1
C1
f
–3dB
2 R1C1
V
R
O
F
1
1
V
R
1
sR1C1
I
G
Figure 38. Single-Pole Low-Pass Filter
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
2 RC
R1
R2
f
–3dB
C2
R
F
R
G
=
1
R
F
2 –
)
(
R
Q
G
Figure 39. 2-Pole Low-Pass Sallen-Key Filter
8.2.1 Design Requirements
The design requirements for this circuit are:
•
•
•
•
Supply voltage: 5 V
Low quiescent current: ≤ 5-µA typical
–3-dB bandwidth: 100 Hz
Gain at 0 Hz: 2
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Typical Application (continued)
8.2.2 Detailed Design Procedure
Considering the equations shown in Figure 39, we can derive that RF = RG if the gain must equal 2 at DC. To
minimize power dissipation of the system, we can set RF = RG = 1 MΩ. With a supply voltage of 5 V, this will give
a worst-possible feedback current of about 2.5 µA.
To set the –3-dB pole at 100 Hz, we can calculate that the ratio R1 × C1 must equal ≈ 1.6 × 10–4. With this in
mind, we can set R1 = 100 kΩ and C1 = 1.6 pF.
With these values, we have achieved all of our design goals for the circuit.
8.2.3 Application Curve
The frequency response of the filter circuit is shown below.
20
0
-20
-40
-60
-80
Circuit response
ꢀ3 dB
-100
1
10
100
1k
10k
100k
1M
Frequency (Hz)
RCLP
Figure 40. RC Low Pass Filter Frequency Response
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9 Power Supply Recommendations
The TLV240x-Q1 is specified for operation from 2.5 V to 16 V (±1.25 V to ±8 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 16 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the .
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10 Layout
10.1 Layout Guidelines
To achieve the levels of high performance of the TLV240x-Q1, follow proper printed-circuit board design
techniques. A general set of guidelines is given in the following.
•
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-mF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 in between the device power terminals and
the ceramic capacitors.
•
•
Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
•
Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 41. Schematic Representation
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Layout Example (continued)
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 42. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV2401-Q1
TLV2402-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV2401QDBVRQ1
TLV2402QDGKRQ1
ACTIVE
ACTIVE
SOT-23
VSSOP
DBV
DGK
5
8
3000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1WU9
QWX
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF TLV2401-Q1, TLV2402-Q1 :
Catalog: TLV2401, TLV2402
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2401QDBVRQ1
TLV2402QDGKRQ1
SOT-23
VSSOP
DBV
DGK
5
8
3000
2500
180.0
330.0
8.4
3.2
5.3
3.2
3.4
1.4
1.4
4.0
8.0
8.0
Q3
Q1
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2401QDBVRQ1
TLV2402QDGKRQ1
SOT-23
VSSOP
DBV
DGK
5
8
3000
2500
210.0
346.0
185.0
346.0
35.0
29.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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