TLV2401CDR [TI]
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION; 家庭880 -NA /通道轨到轨输入/输出运算放大器,具有电池反接保护型号: | TLV2401CDR |
厂家: | TEXAS INSTRUMENTS |
描述: | FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION |
文件: | 总33页 (文件大小:1335K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
Operational Amplifier
Micro-Power Operation . . . < 1 µA/Channel
Input Common-Mode Range Exceeds the
Rails . . . –0.1 V to V + 5 V
CC
–
+
Reverse Battery Protection Up To 18 V
Rail-to-Rail Input/Output
Gain Bandwidth Product . . . 5.5 kHz
Supply Voltage Range . . . 2.5 V to 16 V
Specified Temperature Range
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
– T = 0°C to 70°C . . . Commercial Grade
A
– T = –40°C to 125°C . . . Industrial Grade
A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
A
V
T
A
= 1
V
Ultrasmall Packaging
– 5-Pin SOT-23 (TLV2401)
– 8-Pin MSOP (TLV2402)
= V
/ 2
CC
IN
= 25 °C
Universal OpAmp EVM (Refer to the EVM
Selection Guide SLOU060)
description
The TLV240x family of single-supply operational
amplifiers has the lowest supply current available
today at only 880 nA per channel. Reverse battery
protection guards the amplifier from an over-
current condition due to improper battery
installation. For harsh environments, the inputs
can be taken 5 V above the positive supply rail
without damage to the device.
0
2
4
6
8
10 12 14 16
V
– Supply Voltage – V
CC
The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-Ω
resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical
offset voltage as low as 390 µV, CMRR of 120 dB and minimum open loop gain of 130 V/mV at 2.7 V.
The maximum recommended supply voltage is as high as 16 V and ensured operation down to 2.5 V, with
electrical characteristics specified at 2.7 V, 5 V and 15 V. The 2.5-V operation makes it compatible with Li-Ion
battery-powered systems and many micro-power microcontrollers available today including TI’s MSP430.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in TSSOP.
†
SELECTION OF SINGLE SUPPLY OPERATIONAL AMPLIFIER PRODUCTS
V
(V)
V
BW
(MHz)
SLEW RATE
I
/ch
CC
IO
CC
DEVICE
RAIL-TO-RAIL
(mV)
0.390
0.600
0.450
0.020
0.200
(V/µs)
(µA)
0.880
1
‡
TLV240x
TLV224x
TLV2211
TLV245x
TLV225x
2.5–16
2.5–12
2.7–10
2.7–6
2.7–8
0.005
0.005
0.065
0.22
0.002
0.002
0.025
0.110
0.12
I/O
I/O
O
13
23
I/O
O
0.2
35
†
‡
All specifications are typical values measured at 5 V.
This device also offers 18-V reverse battery protection and 5-V over-the-rail operation on the inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
TLV2401 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
IO
†
†
T
A
SMALL OUTLINE
(D)
SOT-23
(DBV)
PLASTIC DIP
(P)
AT 25°C
SYMBOLS
0°C to 70°C
TLV2401CD
TLV2401ID
TLV2401CDBV
TLV2401IDBV
VAWC
VAWI
—
1500 µV
-40°C to 125°C
TLV2401IP
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,
TLV2401CDR).
TLV2402 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
IO
†
†
T
A
SMALL OUTLINE
(D)
MSOP
PLASTIC DIP
(P)
AT 25°C
SYMBOLS
(DGK)
0°C to 70°C
TLV2402CD
TLV2402ID
TLV2402CDGK
TLV2402IDGK
xxTIAIX
xxTIAIY
—
1500 µV
–40°C to 125°C
TLV2402IP
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,
TLV2402CDR).
TLV2404 AVAILABLE OPTIONS
PACKAGED DEVICES
V
IO
max
†
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
TSSOP
(PW)
AT 25°C
0°C to 70°C
TLV2404CD
TLV2404ID
TLV2404CN
TLV2404IN
TLV2404CPW
TLV2404IPW
1500 µV
–40°C to 125°C
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number (e.g., TLV2404CDR).
TLV240x PACKAGE PINOUTS
TLV2401
D OR P PACKAGE
(TOP VIEW)
TLV2402
D, DGK, OR P PACKAGE
(TOP VIEW)
TLV2401
DBV PACKAGE
(TOP VIEW)
1
2
3
5
4
V
CC
OUT
NC
IN–
NC
1OUT
1IN–
1IN+
GND
V
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
2OUT
2IN–
2IN+
CC
GND
IN+
IN+
OUT
NC
GND
IN–
TLV2404
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN–
1IN+
4OUT
4IN–
4IN+
GND
3IN+
3IN–
3OUT
V
CC
2IN+
2IN–
8
2OUT
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Differential input voltage range, V
Input current range, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Output current range, I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
ID
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND
DISSIPATION RATING TABLE
Θ
Θ
T
≤ 25°C
T = 125°C
A
POWER RATING
JC
JA
A
PACKAGE
POWER RATING
(°C/W)
(°C/W)
D (8)
38.3
176
710 mW
142 mW
D (14)
DBV (5)
DGK (8)
N (14)
26.9
55
122.6
324.1
259.9
78
1022 mW
385 mW
481 mW
1600 mW
1200 mW
204.4 mW
77.1 mW
96.2 mW
320.5 mW
240.4 mW
54.2
32
P (8)
41
104
PW (14)
29.3
173.6
720 mW
144 mW
recommended operating conditions
MIN
MAX
16
UNIT
V
Single supply
2.5
±1.25
–0.1
0
Supply voltage, V
CC
Split supply
±8
Common-mode input voltage range, V
ICR
V
+5
70
V
CC
C-suffix
I-suffix
Operating free-air temperature, T
°C
A
–40
125
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
electrical characteristics at recommended operating conditions, V
otherwise noted)
= 2.7, 5 V, and 15 V (unless
CC
dc performance
†
PARAMETER
Input offset voltage
Offset voltage draft
TEST CONDITIONS
= V /2 V,
= V /2 V,
CC
= 50 Ω
MIN
TYP
MAX
1200
1500
T
UNIT
µV
A
25°C
Full range
25°C
390
V
V
R
O
IC
S
CC
V
IO
α
3
µV/°C
VIO
25°C
63
60
120
V
V
V
= 2.7 V
= 5 V
CC
CC
CC
Full range
25°C
70
120
120
V
R
= 0 to V
= 50 Ω
,
IC
S
CC
CMRR Common-mode rejection ratio
dB
Full range
25°C
63
80
= 15 V
Full range
25°C
75
130
30
400
V
CC
V
CC
V
CC
= 2.7 V,
= 5 V,
V
V
= 1 V,
= 3 V,
R
R
= 500 kΩ
= 500 kΩ
O(pp)
O(pp)
L
Full range
25°C
300
100
1000
120
1000
1800
Large-signal differential voltage
amplification
A
VD
V/mV
L
Full range
25°C
= 15 V,
V
= 6 V, R = 500 kΩ
O(pp) L
Full range
†
Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C.
input characteristics
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
250
300
400
300
350
900
T
A
UNIT
25°C
Full range
25°C
25
I
Input offset current
Input bias current
TLV240xC
TLV240xI
pA
IO
IB
V
V
R
= V /2 V,
CC
= V /2 V,
CC
O
IC
S
100
= 50 Ω
I
TLV240xC
TLV240xI
pA
Full range
r
Differential input resistance
25°C
25°C
300
3
MΩ
i(d)
C
Common-mode input capacitance
f = 100 kHz
pF
i(c)
†
Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
electrical characteristics at recommended operating conditions, V
otherwise noted) (continued)
= 2.7, 5 V, and 15 V (unless
CC
output characteristics
†
PARAMETER
TEST CONDITIONS
MIN
2.65
2.63
4.95
4.93
TYP
MAX
T
A
UNIT
25°C
Full range
25°C
2.68
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 5 V
4.98
V
I
= V /2,
CC
IC
OH
= –2 µA
Full range
25°C
14.95 14.98
= 15 V
= 2.7 V
= 5 V
Full range 14.93
V
OH
High-level output voltage
V
25°C
Full range
25°C
2.62
2.6
2.65
4.95
4.92
4.9
V
= V /2,
CC
= –50 µA
IC
I
Full range
25°C
OH
14.92 14.95
= 15 V
Full range
25°C
14.9
90
150
180
230
260
V
IC
= V /2,
CC
I
I
= 2 µA
OL
OL
Full range
25°C
V
OL
Low-level output voltage
Output current
mV
180
V
V
= V /2,
CC
= 50 µA
IC
Full range
25°C
I
O
= 0.5 V from rail
±200
µA
O
†
Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C.
power supply
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
950
T
A
UNIT
25°C
Full range
25°C
880
V
= 2.7 V or 5 V
= 15 V
CC
CC
1290
990
I
Supply current (per channel)
Reverse supply current
V
= V /2
CC
nA
CC
O
900
V
Full range
1350
V
V
= –18 V,
= Open circuit
V
= 0 V,
IN
CC
O
25°C
25°C
50
nA
100
96
120
V
V
= 2.7 to 5 V,
CC
IC
dB
dB
dB
TLV240xC
TLV240xI
= V /2 V,
CC
Full range
Power supply rejection ratio
No load,
PSRR
85
(∆V /∆V
CC IO
)
25°C
100
100
120
V
= 5 to 15 V,
V
= V /2 V,
IC CC
CC
No load
Full range
†
Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is –40°C to 125°C.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
electrical characteristics at recommended operating conditions, V
otherwise noted) (continued)
= 2.7, 5 V, and 15 V (unless
CC
dynamic performance
PARAMETER
TEST CONDITIONS
T
MIN
TYP
5.5
2.5
60°
15
MAX
UNIT
kHz
A
UGBW
SR
Unity gain bandwidth
Slew rate at unity gain
Phase margin
R
= 500 kΩ,
C
C
= 100 pF
= 100 pF
25°C
25°C
L
L
L
V
O(pp)
= 0.8 V,
R
C
= 500 kΩ,
V/ms
L
L
φM
R
= 500 kΩ,
= 100 pF
25°C
25°C
L
Gain margin
dB
ms
V
V
A
V
= 2.7 or 5 V,
CC
(STEP)PP
= 1 V,
C
R
= 100 pF,
= 100 kΩ
0.1%
1.84
L
L
= –1,
t
s
Settling time
V
V
A
V
= 15 V,
CC
(STEP)PP
= –1,
0.1%
6.1
32
= 1 V,
C
R
= 100 pF,
= 100 kΩ
L
L
0.01%
noise/distortion performance
PARAMETER
Equivalent input noise voltage
Equivalent input noise current
TEST CONDITIONS
f = 10 Hz
T
MIN
TYP
800
500
8
MAX
UNIT
A
V
nV/√Hz
fA/√Hz
n
f = 100 Hz
25°C
I
n
f = 100 Hz
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input Offset Voltage
Input Bias Current
vs Common-mode input voltage
vs Free-air temperature
vs Common-mode input voltage
vs Free-air temperature
vs Common-mode input voltage
vs Frequency
1, 2, 3
4, 6, 8
5, 7, 9
4, 6, 8
5, 7, 9
10
IO
I
IB
I
IO
Input Offset Current
CMRR
Common-mode rejection ratio
High-level output voltage
Low-level output voltage
Output voltage peak-to-peak
Output impedance
V
V
V
vs High-level output current
vs Low-level output current
vs Frequency
11, 13, 15
12, 14, 16
17
OH
OL
O(PP)
o
Z
vs Frequency
18
I
Supply current
vs Supply voltage
19
CC
PSRR
Power supply rejection ratio
Differential voltage gain
Phase
vs Frequency
20
A
VD
vs Frequency
21
vs Frequency
21
Gain-bandwidth product
Slew rate
vs Supply voltage
22
SR
vs Free-air temperature
vs Capacitive load
23
φ
m
Phase margin
24
Gain margin
vs Capacitive load
25
Supply current
vs Reverse voltage
26
Voltage noise over a 10 Second Period
Large signal follower pulse response
Small signal follower pulse response
Large signal inverting pulse response
Small signal inverting pulse response
Crosstalk
27
28, 29, 30
31
32, 33, 34
35
vs Frequency
36
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT
VOLTAGE
COMMON-MODE INPUT
VOLTAGE
COMMON-MODE INPUT
VOLTAGE
100
0
400
300
1400
1200
1000
800
600
400
200
0
V
T
= 2.7 V
V
T
= 15 V
= 25 °C
CC
= 25°C
CC
A
A
200
100
–100
–200
–300
–400
0
–100
–200
–300
–400
V
T
A
= 5 V
CC
= 25 °C
–200
0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
–0.1
2.0
–0.1
4.2
6.4
8.6 10.8 13.0 15.2
––00.2.10 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9
V
– Common-Mode Input Voltage – V
V
– Common-Mode Input Voltage –V
ICR
V
– Common-Mode Input Voltage – V
ICR
ICR
Figure 1
Figure 2
Figure 3
INPUT BIAS / OFFSET CURRENT
INPUT BIAS / OFFSET CURRENT
vs
INPUT BIAS / OFFSET CURRENT
vs
vs
COMMON MODE INPUT
VOLTAGE
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
600
500
400
300
200
100
0
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
V
V
= 2.7 V
V
V
= 5 V
V
T
= 2.7 V
CC
= 1.35 V
CC
= 2.5 V
IC
CC
= 25 °C
IC
A
I
I
IO
I
I
IO
IO
0
I
–50
–100
–150
I
IB
IB
–100
–200
–100
–200
IB
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9
–0.1
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
V
– Common Mode Input Voltage – V
ICR
Figure 4
Figure 5
Figure 6
INPUT BIAS / OFFSET CURRENT
INPUT BIAS / OFFSET CURRENT
INPUT BIAS / OFFSET CURRENT
vs
vs
vs
COMMON-MODE INPUT
VOLTAGE
COMMON-MODE INPUT
VOLTAGE
FREE-AIR TEMPERATURE
200
150
100
50
700
600
500
400
300
200
100
0
250
200
150
100
50
V
V
= 15 V
V
T
= 15 V
= 25 °C
V
T
= 5 V
CC
= 7.5 V
CC
A
CC
= 25 °C
IC
A
I
IO
I
IO
0
0
I
IO
–50
–100
–150
–50
–100
–150
I
I
IB
IB
–100
–200
I
IB
–40 –25 –10
5
20 35 50 65 80 95 110 125
2
–0.1
0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
–0.2 2.0
–0.1
4.2
6.4
8.6 10.8 13.0 15.2
T
A
– Free-Air Temperature – °C
V
– Common Mode Input Voltage – V
ICR
V
– Common-Mode Input Voltage –V
ICR
Figure 7
Figure 8
Figure 9
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TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
2.7
2.4
2.1
1.8
1.5
1.2
1.50
1.25
1.00
0.75
0.50
0.25
0
120
100
80
60
40
20
0
V
T
= 2.7 V
CC
V
= 2.7 V
CC
= 25 °C
= 0 °C
= –40°C
A
T
A
T
A
T
= –40°C
A
T
T
T
T
= –0°C
A
A
A
A
= 25 °C
= 70 °C
= 125 °C
T
T
= 70 °C
= 125 °C
A
A
0
50
100
150
200
0
50
100
150
200
1
10
100
1k
10k
f – Frequency – Hz
I
– High-Level Output Current – µA
I
– Low-Level Output Current – µA
OH
OL
Figure 10
Figure 11
Figure 12
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5.0
4.5
4.0
3.5
3.0
1.50
1.25
1.00
0.75
0.50
0.25
0
15.0
14.5
14.0
13.5
13
V
= 5 V
CC
V
= 5 V
CC
T
= –40°C
A
T
= 0 °C
= –40°C
A
T
A
T
= –0°C
A
T
= –0°C
A
T
= 25 °C
= 70 °C
T = 125 °C
A
A
T
T
T
= 25 °C
= 70 °C
= 125 °C
A
A
A
T
= 25 °C
= 70 °C
= 125 °C
A
T
A
T
A
T
A
T
A
= –40°C
V
= 15 V
50
CC
0
50
100
150
200
0
50
100
150
200
0
100
150
200
I
– High-Level Output Current – µA
I
– Low-Level Output Current – µA
I
– High-Level Output Current – µA
OH
OL
OH
Figure 13
Figure 14
Figure 15
OUTPUT VOLTAGE
PEAK-TO-PEAK
vs
OUTPUT IMPEDANCE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
FREQUENCY
1.50
1.25
1.00
0.75
0.50
0.25
0
16
14
12
10
8
10k
1k
V
= 15 V
CC
V
= 15 V
CC
AV = 10
T
= –40°C
A
T
= –0°C
A
AV = 1
T
= 25 °C
= 70 °C
= 125 °C
A
6
T
A
T
A
R
C
T
A
= 100 kΩ
= 100 pF
= 25°C
L
L
4
V
= 5 V
CC
100
10
2
V
= 2.7 V
CC
0
V
= 2.7, 5, & 15 V
CC
= 25°C
T
A
0
50
100
150
200
100
1k
10k
10
100
1k
I
– Low-Level Output Current – µA
f – Frequency – Hz
f – Frequency – Hz
OL
Figure 16
Figure 18
Figure 17
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
120
110
100
90
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
T
A
= 2.7, 5, & 15 V
CC
= 25°C
80
T
= 125°C
= 70 °C
= 25 °C
= 0 °C
A
70
T
A
T
60
A
T
A
T
A
= –40°C
50
A
V
= 1
V
= V
/ 2
IN
CC
40
0
2
4
6
8
10 12 14 16
10
100
1k
10k
f – Frequency – Hz
V
– Supply Voltage – V
CC
Figure 19
Figure 20
DIFFERENTIAL VOLTAGE GAIN AND PHASE
GAIN BANDWIDTH PRODUCT
vs
vs
SUPPLY VOLTAGE
FREQUENCY
7
6
5
4
3
2
1
0
60
50
135
90
T
R
C
= 25°C
= 100 kΩ
= 100 pF
A
L
L
f = 1 kHz
40
30
20
10
45
0
0
V
R
C
= 2.7, 5, & 15 V
= 500 kΩ
= 100 pF
CC
L
L
–10
T
= 25°C
A
–20
–45
10k
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
10
100
1k
f – Frequency – Hz
V
– Supply Voltage –V
CC
Figure 21
Figure 22
SLEW RATE
vs
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
CAPACITIVE LOAD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
80
70
60
50
40
30
20
10
0
SR+
V
= 5, 15 V
CC
V
= 2.7 V
CC
V
= 2.7, 5, & 15 V
CC
V
R
T
A
= 2.7, 5, & 15 V
= 500 kΩ
= 25°C
SR–
CC
L
–40 –25 –10
5
20 35 50 65 80 95 110 125
10
100
1k
10k
T
A
– Free-Air Temperature – °C
C
– Capacitive Load – pF
L
Figure 23
Figure 24
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TYPICAL CHARACTERISTICS
GAIN MARGIN
SUPPLY CURRENT
vs
REVERSE VOLTAGE
vs
CAPACITIVE LOAD
25
20
15
10
5
60
55
R = 500 kΩ
L
T = 25°C
A
T
= 25°C
A
50
45
40
V
= 15 V
CC
35
30
25
20
15
10
V
= 2.7 & 5 V
CC
5
0
0
–18 –16 –14 –12 –10 –8 –6 –4 –2
0
10
100
1k
10k
C
– Capacitive Load – pF
L
V
– Reverse Voltage – V
CC
Figure 25
Figure 26
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
VOLTAGE NOISE
OVER A 10 SECOND PERIOD
2
4
3
V
= 5 V
CC
f = 0.1 Hz to 10 Hz
= 25°C
1
0
V
IN
T
A
2
1
V
= 2.7 V
CC
A
R
C
= 1
V
L
L
2
–1
0
= 100 kΩ
= 100 pF
= 25°C
–1
–2
–3
–4
1
T
A
V
O
2
0
0
1
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
t – Time – ms
t – Time – s
Figure 27
Figure 28
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
4
3
2
15
V
A
R
= 15 V
= 1
= 100 kΩ
= 100 pF
= 25°C
V
A
R
= 5 V
= 1
= 100 kΩ
= 100 pF
= 25°C
CC
V
L
L
CC
V
L
L
15
10
5
10
5
V
IN
V
IN
C
T
C
T
A
1
0
A
0
4
–5
3
–1
2
V
V
O
6
O
1
0
0
0
2
4
8
10 12 14 16
0
1
2
3
4
5
6
t – Time – ms
t – Time – ms
Figure 29
Figure 30
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TYPICAL CHARACTERISTICS
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
120
100
80
3
2
300
150
V
IN
V
IN
0
1
0
V
= 2.7, 5,
CC
& 15 V
–150
V
A
R
= 2.7 V
0.5
CC
A
= 1
= 100 kΩ
= 100 pF
= –1
V
V
L
L
R
C
= 100 kΩ
= 100 pF
= 25°C
L
L
0.0
–1
C
T
60
V
O
T = 25°C
A
–0.5
–1.0
–1.5
–2
A
40
20
V
3
O
0
0
100 1200 300 400 0 500
t – Time – µs
0
1
2
4
5
6
7
t – Time – ms
Figure 31
Figure 32
LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
4
3
12
9
V
IN
V
IN
2
6
1
3
0.5
0
0
V
A
R
C
T
A
= 15 V
= –1
= 100 kΩ
= 100 pF
V
A
R
= 5 V
= –1
= 100 kΩ
= 100 pF
= 25°C
CC
V
L
L
CC
V
L
L
0.0
2
–1
–3
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
0
C
T
–2
–4
–6
–8
–10
–12
= 25°C
A
V
V
O
O
–1
0
1
2
3
4
5
6
7
0
5
10 15 20 25 30 35
t – Time – ms
t – Time – ms
Figure 33
Figure 34
CROSSTALK
vs
FREQUENCY
SMALL SIGNAL INVERTING
PULSE RESPONSE
50
0
–20
200
100
0
V
V
= 2.7,
IN
CC
5, & 15 V
All Channels
R
C
V
= 100 kΩ
= 100 pF
= 1 V
V
= 2.7, 5,
L
L
IN
–40
CC
& 15 V
= –1
V
= 15 V
CC
A
PP
V
–60
–100
R
= 100 kΩ
L
C
T
A
= 100 pF
= 25°C
L
0
–80
V
= 2.7, 5 V
CC
–50
–100
–150
–100
–120
–140
V
O
–00
0
200 400 600 800 1000 1200
t – Time – ms
10
100
1k
10k
f – Frequency –Hz
Figure 35
Figure 36
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APPLICATION INFORMATION
reverse battery protection
The TLV2401/2/4 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery
condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This
current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient
temperature increases.
When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input
ESD structure will turn on—this current should be limited to less than 10 mA. If the inputs or outputs are referred
to ground, rather than midrail, no extra precautions need be taken.
common-mode input range
The TLV2401/2/4 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to V – 0.8 V a PNP
CC
differential pair will provide the gain.
For inputs between V
– 0.8 V and V , two NPN emitter followers buffering a second PNP differential pair
CC
CC
provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above
the rails, because as the inputs go above V , the NPNs switch from functioning as transistors to functioning
CC
as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to
function normally as the inputs exceed V
.
CC
The TLV2401/2/4 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken
much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion.
offset voltage
Theoutputoffsetvoltage,(V )isthesumoftheinputoffsetvoltage(V )andbothinputbiascurrents(I )times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB–
R
G
+
–
+
V
I
V
O
R
S
I
IB+
R
R
R
R
F
F
V
V
1
I
R
1
I
R
OO
IO
IB
S
IB–
F
G
G
Figure 37. Output Offset Voltage Model
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 38).
R
R
F
G
–
V
1
O
+
V
I
R1
V
C1
f
–3dB
2 R1C1
R
O
F
1
1
V
R
1
sR1C1
I
G
Figure 38. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
–3dB
2 RC
C2
R
F
1
R
=
G
R
F
2 –
)
(
R
Q
G
Figure 39. 2-Pole Low-Pass Sallen-Key Filter
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APPLICATION INFORMATION
circuit layout considerations
ToachievethelevelsofhighperformanceoftheTLV240x, followproperprinted-circuitboarddesigntechniques.
A general set of guidelines is given in the following.
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets– Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
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APPLICATION INFORMATION
general power dissipation considerations
Foragivenθ , themaximumpowerdissipationisshowninFigure40andiscalculatedbythefollowingformula:
JA
T
–T
MAX
A
P
D
JA
Where:
P
= Maximum power dissipation of THS240x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
1.5
1.25
1
θ
= 104°C/W
JA
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
–55–40 –25 –10
5
20 35 50 65 80 95 110 125
T
A
– Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 40. Maximum Power Dissipation vs Free-Air Temperature
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APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 41 are
generated using the TLV240x typical electrical and operating characteristics at T = 25°C. Using this
A
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, andJ. E. Solomon, “MacromodelingofIntegratedCircuitOperationalAmplifiers”, IEEEJournal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
V
CC+
+
–
egnd
ree
ro2
cee
fb
rp
rc1
11
rc2
12
c1
7
+
1
2
c2
vlim
–
8
IN+
IN–
+
–
r2
9
6
vc
+
q1
q2
vb
ga
–
ro1
gcm
ioff
53
dp
14
13
V
OUT
re1
re2
dlp
dln
5
91
90
92
10
–
+
–
–
+
–
iee
dc
vlp
hlim
vln
V
CC–
+
+ 54
4
de
ve
.subckt 240X_5V–X 1 2 3 4 5
*
rc1
rc2
re1
re2
ree
ro1
ro2
rp
3
3
11 978.81E3
12 978.81E3
c1
c2
11 12 9.8944E–12
30.000E–12
13 10 30.364E3
14 10 30.364E3
10 99 3.6670E9
6
7
cee 10 99 8.8738E–12
dc
5
53 dy
8
5
10
de
dlp
dln
dp
54 5 dy
90 91 dx
92 90 dx
7
99 10
3
4
0
1.4183E6
dc
vb
9
0
4
3
dx
vc
ve
vlim
vlp
vln
3
53 dc .88315
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
54
7
4
8
0
dc .88315
dc
dc 540
fb
7
6
0
99 poly(5) vb vc ve vlp vln 0 61.404E6 –1E3 1E3 61E6 –61E6
0
ga
0
6
11 12 1.0216E–6
10 99 10.216E–12
91
0
gcm
iee
ioff
92 dc 540
10 4 dc 54.540E–9
.model dx D(Is=800.00E–18)
0
6
dc 5e–12
.model dy D(Is=800.00E–18 Rs=1m Cjo=10p)
.model qx1 NPN(Is=800.00E–18 Bf=27.270E21)
.model qx2 NPN(Is=800.0000E–18 Bf=27.270E21)
.ends
hlim 90 0 vlim 1K
q1
q2
r2
11
12 1 14 qx2
100.00E3
2
13 qx1
6
9
Figure 41. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
17
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV2401CD
TLV2401CDBVR
TLV2401CDBVRG4
TLV2401CDBVT
TLV2401CDBVTG4
TLV2401CDG4
TLV2401CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
D
DBV
DBV
DBV
DBV
D
8
5
5
5
5
8
8
8
8
5
5
5
5
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
75
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
75
Green (RoHS
& no Sb/Br)
TLV2401CDRG4
TLV2401ID
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TLV2401IDBVR
TLV2401IDBVRG4
TLV2401IDBVT
TLV2401IDBVTG4
TLV2401IDG4
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
75
Green (RoHS
& no Sb/Br)
TLV2401IDR
SOIC
D
2500
2500
Green (RoHS
& no Sb/Br)
TLV2401IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
TLV2401IP
ACTIVE
ACTIVE
PDIP
PDIP
P
P
8
8
50
50
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
TLV2401IPE4
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV2402CD
TLV2402CDG4
TLV2402CDGK
TLV2402CDGKG4
TLV2402CDGKR
TLV2402CDGKRG4
TLV2402CDR
SOIC
SOIC
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLV2402CDRG4
TLV2402ID
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TLV2402IDG4
SOIC
D
75
Green (RoHS
& no Sb/Br)
TLV2402IDGK
TLV2402IDGKG4
TLV2402IDGKR
TLV2402IDGKRG4
TLV2402IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLV2402IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
TLV2402IP
TLV2402IPE4
TLV2404AIN
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
P
P
N
8
8
50
50
Pb-Free (RoHS)
Pb-Free (RoHS)
TBD
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
OBSOLETE
14
Call TI
Call TI
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV2404CD
TLV2404CDG4
TLV2404CPW
TLV2404CPWG4
TLV2404CPWR
TLV2404CPWRG4
TLV2404ID
SOIC
SOIC
D
D
14
14
14
14
14
14
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLV2404IDG4
TLV2404IDR
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
Green (RoHS
& no Sb/Br)
TLV2404IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
TLV2404IN
TLV2404INE4
TLV2404IPW
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
N
N
14
14
14
25
25
90
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
TSSOP
PW
Green (RoHS
& no Sb/Br)
TLV2404IPWG4
TLV2404IPWR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
14
14
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
2000
2000
Green (RoHS
& no Sb/Br)
TLV2404IPWRG4
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2402 :
Automotive: TLV2402-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2401CDBVR
TLV2401CDBVT
TLV2401CDR
TLV2401IDBVR
TLV2401IDBVT
TLV2401IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
180.0
180.0
330.0
180.0
180.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
9.0
9.0
3.15
3.15
6.4
3.2
3.2
5.2
3.2
3.2
5.2
5.2
3.4
5.2
3.4
5.2
5.6
9.0
5.6
1.4
1.4
2.1
1.4
1.4
2.1
2.1
1.4
2.1
1.4
2.1
1.6
2.1
1.6
4.0
4.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
2500
3000
250
12.4
9.0
12.0
8.0
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
3.15
3.15
6.4
5
9.0
8.0
8
2500
2500
2500
2500
2500
2500
2000
2500
2000
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
TLV2401IDR
SOIC
D
8
6.4
TLV2402CDGKR
TLV2402CDR
TLV2402IDGKR
TLV2402IDR
VSSOP
SOIC
DGK
D
8
5.3
8
6.4
VSSOP
SOIC
DGK
D
8
5.3
8
6.4
TLV2404CPWR
TLV2404IDR
TSSOP
SOIC
PW
D
14
14
14
6.9
6.5
TLV2404IPWR
TSSOP
PW
6.9
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2401CDBVR
TLV2401CDBVT
TLV2401CDR
TLV2401IDBVR
TLV2401IDBVT
TLV2401IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
3000
250
182.0
182.0
340.5
182.0
182.0
340.5
367.0
358.0
340.5
358.0
340.5
367.0
367.0
367.0
182.0
182.0
338.1
182.0
182.0
338.1
367.0
335.0
338.1
335.0
338.1
367.0
367.0
367.0
20.0
20.0
20.6
20.0
20.0
20.6
35.0
35.0
20.6
35.0
20.6
35.0
38.0
35.0
8
2500
3000
250
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
2500
2500
2500
2500
2500
2500
2000
2500
2000
TLV2401IDR
SOIC
D
8
TLV2402CDGKR
TLV2402CDR
TLV2402IDGKR
TLV2402IDR
VSSOP
SOIC
DGK
D
8
8
VSSOP
SOIC
DGK
D
8
8
TLV2404CPWR
TLV2404IDR
TSSOP
SOIC
PW
D
14
14
14
TLV2404IPWR
TSSOP
PW
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Copyright © 2012, Texas Instruments Incorporated
相关型号:
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