TLK10002CTR_技术文档

TLK10002

www.ti.com

SLLSE75 –MAY 2011

10Gbps Dual-Channel Multi-Rate Transceiver

Check for Samples: TLK10002

1

FEATURES

•

Programmable Transmit Output Swing on Both

High Speed and Low Speed Sides.

•

Dual Channel 10Gbps Multi-Rate Transceiver

Supports all CPRI and OBSAI Data Rates

Minimum Receiver Differential Input Threshold

of 100mV_pp

Integrated Latency Measurement Function,

Accuracy up to 814 ps

•

Loss of Signal (LOS) Detection

Interface to Backplanes, Passive and Active

Copper Cables, or SFP/SFP+ Optical Modules

•

Supports SERDES Operation with up to

10Gbps Data Rate on the High Speed Side and

up to 5Gbps on the Low Speed Side

•

Hot Plug Protection

JTAG; IEEE 1149.1 /1149.6 Test Interface

MDIO; IEEE 802.3 Clause-22 Support

65nm Advanced CMOS Technology

•

Differential CML I/Os on Both High Speed and

Low Speed Sides

Shared or Independent Reference Clock per

Channel

Industrial Ambient Operating Temperature

(–40°C to 85°C) at Full Rate

Loopback Capability on Both High Speed and

Low Speed Sides, OBSAI Compliant

•

Power Consumption: 1.6W Typical

•

Supports Data Retime Operation

Device Package: 13mm x 13mm, 144-pin

PBGA, 1-mm Ball-Pitch

Supports PRBS 2⁷-1, 2²³-1 and 2³¹-1 and

High-Frequency/Low-Frequency/Mixed-

Frequency/CRPAT Long/Short Pattern

Generation and Verification

APPLICATIONS

•

Wireless Infrastructure CPRI and OBSAI Links

High-Speed Video Applications

•

Two Power Supplies: 1.0V Core, and 1.5 or

1.8V I/O

Proprietary Cable/Backplane Links

Transmit De-emphasis and Receive Adaptive

Equalization to Allow Extended

Backplane/Cable Reach on Both High Speed

and Low Speed Sides

High-Speed Point- to-Point Transmission

Systems

TLK10002 CHANNEL A

1:11:1

2:12:1

4:14:1

0.5- 5Gbps

1/2/4 Diff Pairs

1- 10Gbps

1 Diff Pair

H

I

L

O

W

G

H

1:11:1

2:12:1

4:14:1

0.5- 5Gbps

1/ 2/4Diff Pairs

1- 10Gbps

1Diff Pair

S

P

E

D

S

P

E

D

TLK10002 CHANNEL B

1:11:1

2:12:1

4:14:1

0.5- 5Gbps

1- 10Gbps

1 Diff Pair

S

I

1/2/4 Diff Pairs

S

I

D

E

D

E

1:11:1

2:12:1

4:14:1

0.5- 5Gbps

1- 10Gbps

1Diff Pair

1/2/4 Diff Pairs

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLK10002

SLLSE75 –MAY 2011

www.ti.com

DESCRIPTION

The TLK10002 is a dual-channel multi-rate transceiver intended for use in high-speed bi-directional point-to-point

data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH)

application, but may also be used in other high speed applications. It supports all the CPRI and OBSAI rates

from 1.2288Gbps to 9.8304Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low

speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high speed (HS) side

outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams

presented on its high speed side data inputs. The deserialized 8B/10B encoded data is presented on the low

speed side outputs. Depending on the serialization/deserialization ratio, the low speed side data rate can range

from 0.5Gbps to 5Gbps and the high speed side data rate can range from 1Gbps to 10Gbps. Both low speed

and high speed side data inputs and outputs are of differential current mode logic (CML) type with integrated

termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for

transmission of PRBS data through the device.

The TLK10002 performs data serialization/deserialization and clock extraction as a physical layer interface

device. Flexible clocking schemes are provided to support various operations. They include the support for

clocking with an externally-jitter-cleaned clock recovered from the high speed side.

The TLK10002 provides two low speed side and two high speed side loopback modes for self-test and system

diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side

supports generation and verification of PRBS 2⁷-1, 2²³-1, and 2³¹-1 patterns. In addition to those PRBS patterns,

the high speed side supports High, Low, Mixed, and CRPAT long/short pattern generation and verification.

The TLK10002 has an integrated loss of signal (LOS) detection function on both high speed and low speed

sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert

threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be

cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the

low speed side interface. The interfaced upstream link partner device needs to implement the lane alignment

scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at

different data rates, and with different serialization/deserialization ratios.

The low speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local

physical system. The high speed side is ideal for interfacing with remote systems through an optical fiber, an

electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical

modules.

2

TLK10002

www.ti.com

SLLSE75 –MAY 2011

BLOCK DIAGRAM

A simplified block diagram of the TLK10002 device is shown in Figure 1 for Channel A which is identical to

Channel B. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low

speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks

carries out all the logic functions including channel synchronization, lane alignment, 8B/10B encoding/decoding,

as well as test pattern generation and verification.

The TLK10002 provides a management data input/output (MDIO) interface as well as a JTAG interface for

device configuration, control, and monitoring. Detailed description of the TLK10002 pin functions is provided in

Table 1.

Ch annel A

10

16

32

INA0P/N

LS PRBS

Verifier

TX FIFO

10

20

HS PRBS

Generator

HSTXAP/N

16

INA1P/N

INA2P/N

INA3P/N

Pattern

Generator

10

High

Speed

Side

Low

Speed

Side

10

OUTA0P/N

16

32

SERDES

RX FIFO

10

OUTA1P/N

OUTA2P/N

OUTA3P/N

HS PRBS

Verifier

LS PRBS

Generator

10

HSRXAP/N

CLKOUTAP/N

LS_OK_OUT_A

LS_OK_IN_A

Pattern

Verifier

LOSA

PDTRXA_N

VDDRA_LS

VDDRA_HS

VDDA

VDDT

VDDD

DVDD

REFCLK0P/N

REFCLK1P/N

REFCLKA_SEL

RESET_N

PRTAD [4:0]

MDC

VDDO

VSS

MDIO

Interface

TDO

TMS

MDIO

TRST_N

JTAG

TESTEN

PRBSEN

TCK

TDI

PRBS_PASS

Figure 1. Simplified Block Diagram of the TLK10002

PACKAGE

For the TLK10002, a 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used. The device

pin-out is as shown in Figure 2 and is described in detail in Table 1 and Table 2.

3

TLK10002

SLLSE75 –MAY 2011

www.ti.com

1

2

3

4

5

6

7

8

9

10

11

12

A

B

INA1P

INA1N

VSS

INA2P

INA0N

INA0P

VSS

OUTA0P OUTA0N PDTRXA_N

CLKOUTBP

CLKOUTBN

VSS

HSRXAN

VSS

OUTA1P OUTA1N

VSS

VDDO0

VPP

TMS

TDI

PRBSEN

CLKOUTAP

LS_OK_OUT_A

LOSA

LS_OK_IN_A

CLKOUTAN

VSS

AMUXA

VSS

HSRXAP

VSS

C

D

E

INA2N

VDDRA_LS OUTA2P OUTA2N

VSS

TDO

INA3P

INA3N

VSS

VDDA_LS

VSS

AMUXB

VSS

TCK

HSTXAP

OUTA3N

TRST_N VDDD

DVDD

VSS

VDDD

VSS

PRTAD0

VSS

VDDRA_HS HSTXAN

F

VDDA_LS

VSS

OUTA3P VDDT_LS

VSS

VDDD

DVDD

VDDT_HS

PRTAD1

VDDA_HS

VSS

G

H

J

VSS

VDDT_LS

VSS

DVDD

VDDD

MDC

VDDA_HS

HSRXBN

HSRXBP

VSS

INB0P

INB0N

VSS

OUTB0N

RESET_N VDDD

DVDD

MDIO

VDDO1

VSS

LS_OK_OUT_B REFCLKB_SEL

VSS

VDDA_LS

INB1P

OUTB0P PDTRXB_N VSS

PRTAD3

VSS

PRBS_PASS

REFCLK1P

PRTAD2

GPI0

VDDRB_HS

VSS

K

L

VDDRB_LS OUTB1N OUTB1P

LOSB

REFCLK1N

TESTEN

HSTXBP

HSTXBN

VSS

INB2P

INB2N

INB1N

VSS

OUTB2N OUTB2P

VSS

LS_OK_IN_B

VSS

M

VSS

INB3P

INB3N

OUTB3N OUTB3P

PRTAD4 REFCLKA_SEL REFCLK0P REFCLK0N

Figure 2. The Pin-Out of the TLK10002 in a 13-mm x 13-mm 144-pin PBGA Package

PIN FUNCTIONS

The details of the pin functions of the TLK10002 device are provided in Table 1 and Table 2.

Table 1. Pin Description – Signal Pins

DIRECTION

TYPE

SUPPLY

DESCRIPTION

SIGNAL

BGA

CHANNEL A

Serial Transmit Channel A Output. HSTXAP and HSTXAN comprise the high speed side

transmit direction Channel A differential serial output signal. During device reset (RESET_N

asserted low) these pins are driven differential zero. These CML outputs must be AC

coupled.

Output

CML

VDDA_HS

HSTXAP

HSTXAN

D12

E12

Input

CML

VDDA_HS

Serial Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed side

receive direction Channel A differential serial input signal. These CML input signals must be

AC coupled.

HSRXAP

HSRXAN

B12

A12

D1/E1

B2/C2

A1/B1

A4/A3

Parallel Channel A Inputs. INAP and INAN comprise the low speed side transmit direction

Channel A differential input signals. Only INA[0] is used in the 1:1 mode, and only INA[1:0]

are used in the 2:1 mode. These signals must be AC coupled.

Input

CML

VDDA_LS

INA[3:0]P/N

F3/E3

C4/C5

B5/B6

A6/A7

Parallel Channel A Outputs. OUTAP and OUTAN comprise the low speed side receive

direction Channel A differential output signals. During device reset (RESET_N asserted

low) these pins are driven differential zero. Only OUTA[0] is used in the 1:1 mode, and only

OUTA[1:0] are used in the 2:1 mode. These signals must be AC coupled.

Output

CML

VDDA_LS

OUTA[3:0]P/N

Channel A Receive Loss Of Signal (LOS) Indicator.

LOSA=0: Signal detected.

LOSA=1: Loss of signal.

Loss of signal detection is based on the input signal level.

When HSRXAP/N has a differential input signal swing of <75 mVpp, LOSA will be asserted

(if enabled). Once asserted, the input signal has to be > 150 mVpp for this LOS to be

deasserted.

Output

LVCMOS

1.5V/1.8V

VDDO0

LOSA

E9

Other functions can be observed on LOSA in real-time, configured via MDIO.

40Ω Driver

During device reset (RESET_N asserted low) this pin is driven low. During pin based power

down (PDTRXA_N asserted low), this pin is floating. During register based power down

(1.15 asserted high), this pin is floating. NOTE: It is highly recommended that LOSA be

brought to an easily accessible point on the application board (header), in the event that

debug is required.

4

TLK10002

www.ti.com

SIGNAL

SLLSE75 –MAY 2011

Table 1. Pin Description – Signal Pins (continued)

DIRECTION

TYPE

DESCRIPTION

BGA

SUPPLY

Reference Clock Select Channel A. This input, when low, selects REFCLK0P/N as the

clock reference to Channel A SERDES. When high, REFCLK1P/N is selected as the clock

reference to Channel A SERDES. If software control is desired (register bit 1.1), this input

signal should be tied low. See Figure 11 for more detail. Default reference clock for

Channel A is REFCLK0P/N.

Input

LVCMOS

1.5V/1.8V

VDDO0

REFCLKA_SEL

M9

Channel A High Speed Side Output Clock. By default, this output is enabled and outputs

the high speed side Channel A recovered byte clock (high speed line rate divided by 20).

Optionally it can be configured to output the VCO clock divided by 2. Additional

MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See

Figure 11.

This CML output must be AC coupled.

Output

CML

CLKOUTAP/N

C9/C10

During device reset (RESET_N asserted low) these pins are driven differential zero.

DVDD

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), these pins are

floating.

During register based power down (1.15 asserted high both channels), these pins are

floating.

Channel A high speed side recovered byte clock can also be directed to CLKOUTBP/N pins

through the MDIO interface.

Channel A Receive Lane Alignment Status Indicator.

Lane alignment status signal received from a Lane Alignment Slave on the link partner

device.

LS_OK_IN_A=0: Channel A Link Partner Receive lanes not aligned.

LS_OK_IN_A=1: Channel A Link Partner Receive lanes aligned

Input

LVCMOS

1.5V/1.8V

VDDO0

LS_OK_IN_A

B10

Output

Channel A Transmit Lane Alignment Status Indicator.

LVCMOS Lane alignment status signal sent to a Lane Alignment Master on the link partner device.

1.5V/1.8V LS_OK_OUT_A=0: Channel A Transmit lanes not aligned.

LS_OK_OUT_A

D9

A8

VDDO0

LS_OK_OUT_A=1: Channel A Transmit lanes aligned.

40Ω Driver

Input

Transceiver Power Down. When this pin is held low (asserted), Channel A is placed in

power down mode. When deasserted, Channel A operates normally. After deassertion, a

software data path reset must be issued through the MDIO interface.

LVCMOS

1.5V/1.8V

VDDO0

PDTRXA_N

CHANNEL B

Serial Transmit Channel B Output. HSTXBP and HSTXBN comprise the high speed side

transmit direction Channel B differential serial output signal. During device reset (RESET_N

asserted low) these pins are driven differential zero. These CML outputs must be AC

coupled.

Output

CML

VDDA_HS

HSTXBP

HSTXBN

K12

L12

Input

CML

VDDA_HS

Serial Receive Channel B Input. HSRXBP and HSRXBN comprise the high speed side

receive direction Channel B differential serial input signal. These CML input signals must be

AC coupled.

HSRXBP

HSRXBN

H12

G12

M3/M4

L1/M1

K2/L2

H1/J1

Parallel Channel B Inputs. INBP and INBN comprise the low speed side transmit direction

Channel B differential input signals. Only INB[0] is used in the 1:1 mode, and only INB[1:0]

are used in the 2:1 mode. These signals must be AC coupled.

Input

CML

VDDA_LS

INB[3:0]P/N

M7/M6

L6/L5

K5/K4

J3/H3

Parallel Channel B Outputs. OUTBP and OUTBN comprise the low speed side receive

direction Channel B differential output signals. During device reset (RESET_N asserted

low) these pins are driven differential zero. Only OUTB[0] is used in the 1:1 mode, and only

OUTB[1:0] are used in the 2:1 mode. These signals must be AC coupled.

Output

CML

VDDA_LS

OUTB[3:0]P/N

5

TLK10002

SLLSE75 –MAY 2011

www.ti.com

Table 1. Pin Description – Signal Pins (continued)

DIRECTION

TYPE

SUPPLY

DESCRIPTION

SIGNAL

BGA

Channel B Receive Loss Of Signal (LOS) Indicator.

LOSB=0: Signal detected.

LOSB=1: Loss of signal. Loss of signal detection is based on the input signal level. When

HSRXBP/N has a differential input signal swing of <75 mVpp, LOSB will be asserted (if

enabled). Once asserted, the input signal has to be > 150 mVpp for this LOS to be

deasserted

Output

LVCMOS

1.5V/1.8V

VDDO1

LOSB

K8

Other functions can be observed on LOSB in real-time, configured via MDIO.

During device reset (RESET_N asserted low) this pin is driven low. During pin based power

down (PDTRXB_N asserted low), this pin is floating. During register based power down

(1.15 asserted high), this pin is floating.

40Ω Driver

It is highly recommended that LOSB be brought to an easily accessible point on the

application board (header), in the event that debug is required.

Reference Clock Select Channel B. This input, when low, selects REFCLK0P/N as the

clock reference to Channel B SERDES. When high, REFCLK1P/N is selected as the clock

reference to Channel B SERDES. If software control is desired (register bit 1.1), this input

signal should be tied low. See Figure 11 for more detail. Default reference clock for

Channel B is REFCLK0P/N.

Input

LVCMOS

1.5V/1.8V

VDDO1

REFCLKB_SEL

H10

Channel B High Speed Side Output Clock. By default, this output is enabled and outputs

the high speed side Channel B recovered byte clock (high speed line rate divided by 20).

Optionally it can be configured to output the VCO clock divided by 2. Additional

MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See

Figure 11.

Output

CML

DVDD

This CML output must be AC coupled.

CLKOUTBP/N

A9/A10

During device reset (RESET_N asserted low) these pins are driven differential zero. During

pin based power down (PDTRXA_N and PDTRXB_N asserted low), these pins are floating.

During register based power down (1.15 asserted high both channels), these pins are

floating.

Channel B high speed side recovered byte clock can also be directed to CLKOUTAP/N pins

through the MDIO interface.

Input

Channel B Receive Lane Alignment Status Indicator. Lane alignment status signal

received from a Lane Alignment Slave on the link partner device.

LS_OK_IN_B=0: Channel B Link Partner Receive lanes not aligned.

LS_OK_IN_B=1: Channel B Link Partner Receive lanes aligned

LVCMOS

1.5V/1.8V

VDDO1

LS_OK_IN_B

LS_OK_OUT_B

PDTRXB_N

L8

H9

J4

Output

LVCMOS

1.5V/1.8V

VDDO1

Channel B Transmit Lane Alignment Status Indicator. Lane alignment status signal sent

to a Lane Alignment Master on the link partner device.

LS_OK_OUT_B=0: Channel B Transmit lanes not aligned.

LS_OK_OUT_B=1: Channel B Transmit lanes aligned.

40Ω Driver

Input

Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in

power down mode. When deasserted, Channel B operates normally. After deassertion, a

software data path reset should be issued through the MDIO interface.

LVCMOS

1.5V/1.8V

VDDO1

REFERENCE CLOCKS AND CONTROL AND MONITORING SIGNALS

Input

LVDS/

LVPECL

DVDD

Reference Clock Input Zero. This differential input is a clock signal used as a reference to

one or both channels. The reference clock selection is done through MDIO or

REFCLKA_SEL and REFCLKB_SEL pins. This input signal must be AC coupled. If

unused, REFCLK0P/N should be pulled down to GND through a shared 100 Ω resistor.

REFCLK0P/N

REFCLK1P/N

PRBSEN

M10/M11

K9/K10

B9

Input

LVDS/

LVPECL

DVDD

Reference Clock Input One. This differential input is a clock signal used as a reference to

one or both channels. The reference clock selection is done through MDIO. This input

signal must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND

through a shared 100 Ω resistor.

Input

Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier

circuits are enabled on both transmit and receive data paths on high speed and low speed

sides of both channels. This signal is logically OR’d with MDIO register bits B.7:6, and

B.13:12. PRBS 2³¹-1 is selected by default, and can be changed through MDIO.

LVCMOS

1.5V/1.8V

VDDO0

6

TLK10002

www.ti.com

SIGNAL

SLLSE75 –MAY 2011

Table 1. Pin Description – Signal Pins (continued)

DIRECTION

TYPE

DESCRIPTION

BGA

SUPPLY

Receive PRBS Error Free (Pass) Indicator.

When PRBS test is enabled (PRBSEN=1): PRBS_PASS=1 indicates that PRBS pattern

reception is error free. PRBS_PASS=0 indicates that a PRBS error is detected. The

channel, high speed or low speed side, and lane (for low speed side) that this signal refers

to is chosen through MDIO register bits 0.3:0.

Output

LVCMOS

1.5V/1.8V

VDDO1

During device reset (RESET_N asserted low) this pin is driven low.

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is

floating.

PRBS_PASS

J9

40Ω Driver

During register based power down, this pin is floating.

It is highly recommended that PRBS_PASS be brought to easily accessible point on the

application board (header), in the event that debug is required.

MDIO Port Address. Used to select the MDIO port address.

PRTAD[4:1] selects the MDIO port address. The TLK10002 has two different MDIO port

addresses. Selecting a unique PRTAD[4:1] per TLK10002 device allows 16 TLK10002

devices per MDIO bus. Each channel can be accessed by setting the appropriate port

address field within the serial interface protocol transaction.

M8

J6

L9

G9

E10

Input

LVCMOS

1.5V/1.8V

VDDO[1:0]

The TLK10002 will respond if the 4 MSB’s of the port address field on MDIO protocol

(PA[4:1]) matches PRTAD[4:1]. The LSB of port address field (PA[0]) determines which

TLK10002 channel responds. Channel A responds when PA[0]=0 and Channel B responds

when PA[0]=1.

PRTAD[4:0]

PRTAD[0] is not used functionally, but is present for device testability and compatibility with

other devices in the family of products. PRTAD[0] should be grounded on the application

board.

Input

Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10

µs after device power stabilization.

LVCMOS

1.5V/1.8V

VDDO1

RESET_N

MDC

H5

J8

Input

MDIO Clock Input. Clock input for the Clause 22 MDIO interface.

LVCMOS Note that an external pullup is generally not required on MDC.

with

Hysteresis

1.5V/1.8V

VDDO1

MDIO Data I/O. MDIO interface data input/output signal for the Clause 22 MDIO interface.

This signal must be externally pulled up to VDDO, using a 2kΩ resistor.

Input/Output

During device reset (RESET_N asserted low) this pin is floating. During register based

power down the management interface remains active for control register writes and reads.

Certain status bits are not deterministic as their generating clock source may be disabled

as a result of asserting either power down input signal. During pin based power down

(PDTRXA_N and PDTRXB_N asserted low), this pin is floating. During register based

power down (1.15 asserted high both channels), this pin is driven normally.

LVCMOS

1.5V/1.8V

VDDO1

MDIO

J7

25Ω Driver

Input

JTAG Input Data. TDI is used to serially shift test data and test instructions into the device

during the operation of the test port. In system applications where JTAG is not

implemented, this input signal may be left floating.

LVCMOS

1.5V/1.8V

VDDO0

(Internal

Pullup)

TDI

C8

D6

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled up. During register based power down (1.15 asserted high both channels), this pin is

pulled up.

JTAG Output Data. TDO is used to serially shift test data and test instructions out of the

device during operation of the test port. When the JTAG port is not in use, TDO is in a high

impedance state.

Output

LVCMOS

1.5V/1.8V

VDDO0

TDO

During device reset (RESET_N asserted low) this pin is floating.

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is

floating.

50Ω Driver

During register based power down (1.15 asserted high both channels), this pin is floating.

7

TLK10002

SLLSE75 –MAY 2011

www.ti.com

Table 1. Pin Description – Signal Pins (continued)

DIRECTION

TYPE

SUPPLY

DESCRIPTION

SIGNAL

BGA

JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In

system applications where JTAG is not implemented, this input signal can be left

unconnected.

Input

LVCMOS

1.5V/1.8V

VDDO0

(Internal

Pullup)

TMS

TCK

B8

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled up.

During register based power down (1.15 asserted high both channels), this pin is pulled up.

Input

LVCMOS

with

Hysteresis

1.5V/1.8V

VDDO0

JTAG Clock. TCK is used to clock state information and test data into and out of the

device during boundary scan operation. In system applications where JTAG is not

implemented, this input signal should be grounded.

D8

E5

JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode.

This input can be left unconnected in the application and is pulled down internally, disabling

the JTAG circuitry. If JTAG is implemented on the application board, this signal should be

deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal

operation mode.

Input

LVCMOS

1.5V/1.8V

VDDO0

TRST_N

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled down. During register based power down (1.15 asserted high both channels), this pin

is pulled down.

(Internal

Pulldown)

Input

Test Enable. This signal is used during the device manufacturing process. It should be

grounded through a resistor in the device application board. The application board should

allow the flexibility of easily reworking this signal to a high level if device debug is

necessary (by including an uninstalled resistor to VDDO).

LVCMOS

1.5V/1.8V

VDDO1

TESTEN

GPI0

L10

J10

Input

General Purpose Input Zero. This signal is used during the device manufacturing process.

It should be grounded through a resistor on the device application board. The application

board should also allow the flexibility of easily reworking this signal to a high level if device

debug is necessary (by including an uninstalled resistor to VDDO).

LVCMOS

1.5V/1.8V

VDDO1

SERDES Channel A Analog Testability I/O. This signal is used during the device

manufacturing process. It should be left unconnected in the device application.

AMUXA

AMUXB

C11

D4

Analog I/O

SERDES Channel B Analog Testability I/O. This signal is used during the device

manufacturing process. It should be left unconnected in the device application.

Table 2. Pin Description – Power Pins

Type

DESCRIPTION

SIGNAL

BGA

SERDES Analog Power. VDDA_LS and VDDA_HS provide supply voltage for the analog

Power circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied

together on the application board.

D2, F2, G2,

J2 / F11, G10

VDDA_LS/HS

SERDES Analog Power. VDDT_LS and VDDT_HS provide termination and supply

Power voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V

nominal. Can be tied together on the application board.

VDDT_LS/HS

F4, G4 / F9

E6, E8, F6, H6,

H8

SERDES Digital Power. VDDD provides supply voltage for the digital circuits internal to

the SERDES. 1.0V nominal.

VDDD

DVDD

Power

E7, F7, G6, G8,

H7

Power Digital Core Power. DVDD provides supply voltage to the digital core. 1.0V nominal.

SERDES Analog Regulator Power. VDDRA_LS and VDDRA_HS provide supply voltage

Power for the internal PLL regulator for Channel A low speed and high speed sides respectively.

1.5V or 1.8V nominal.

VDDRA_LS/HS

VDDRB_LS/HS

C3/E11

K3/J11

SERDES Analog Regulator Power. VDDRB_LS and VDDRB_HS provide supply voltage

Power for the internal PLL regulator for Channel B low speed and high speed sides respectively.

1.5V or 1.8V nominal.

LVCMOS I/O Power. VDDO0 and VDDO1 provide supply voltage for the LVCMOS inputs

Power

VDDO[1:0]

VPP

K7/C7

D7

and outputs. 1.5V or 1.8V nominal. Can be tied together on the application board.

Factory Program Voltage. Used during device manufacturing. The application must

Power

connect this power supply directly to DVDD.

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SLLSE75 –MAY 2011

Table 2. Pin Description – Power Pins (continued)

Type

DESCRIPTION

BGA

A2, A5, A11,

B3, B4, B7,

B11, C1, C6,

C12, D3, D5,

D10, D11, E2,

E4, F1, F5, F8,

VSS

F10, F12, G1, Ground Ground. Common analog and digital ground.

G3, G5, G7,

G11, H2, H4,

H11, J5, J12,

K1, K6, K11, L3,

L4, L7, L11, M2,

M5, M12

FUNCTIONAL DESCRIPTION

The TLK10002 is a versatile high-speed transceiver device that is designed to perform various physical layer

functions. It is equipped with a number of functions and testability features that make it easy to integrate the

device in high-speed communications systems, especially in wireless infrastructure. The details of those features

are discussed in this section.

Transmit (Low Speed to High Speed) Data Path

The TLK10002 transmit data path with the device configured to operate in the normal transceiver (mission) mode

is as shown in Figure 3 and Figure 4. In this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is

received by the low speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in

each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data

for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32-bits of lane aligned parallel

data is subsequently fed into a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The

resulting 20-bit 8B/10B encoded parallel data is handed to the high speed side SERDES for serialization and

output through the HSTX*P/N pins. This process is exactly the same for both Channel A and Channel B.

Low

10

High

Speed

Side

IN*0P/N

IN*1P/N

16

20

Speed

Side

SERDES

HSTX*P/N

1

0

TX FIFO

SERDES

Figure 3. Transmit Data Path for the 2:1 Mode

10

IN*0P/N

Low

High

Speed

Side

32

16

20

Speed

Side

SERDES

IN*1P/N

IN*2P/N

HSTX*P/N

1

0

TX FIFO

SERDES

10

IN*3P/N

Figure 4. Transmit Data Path for the 4:1 Mode

Receive (High Speed to Low Speed) Data Path

With the device configured to operate in the normal transceiver (mission) mode, the receive data path is as

shown in Figure 6. 8B/10B encoded serial data (HSRX*P/N) is received by the high speed side SERDES and

deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and

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then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment

Master which splits the data into the same number of lanes as configured on the transmit data path. The lane

data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is fed into the low speed side

SERDES for serialization and output through the OUT*P/N pins. This process is exactly the same for both

Channel A and Channel B.

10

Low

Speed

Side

High

Speed

Side

16

20

OUT*0P/N

OUT*1P/N

*P/N

HSRX

RX FIFO

SERDES

Figure 5. Receive Data Path for the 2:1 Modes

10

OUT*0P/N

OUT*1P/N

Low

Speed

Side

High

Speed

Side

32

16

20

10

*P/N

HSRX

RX FIFO

OUT*2P/N

OUT*3P/N

SERDES

Figure 6. Receive Data Path for the 4:1 Modes

1:1 Retime Mode

In the 1:1 Retime mode shown in Figure 7, the lane alignment and 8B/10B encoding/decoding blocks are not

included in the data path. In the transmit data path, low speed side data received on the IN*0P/N pins is

deserialized, phase corrected by the transmit FIFO, and serialized again before it is output through the

HSTX*P/N pins. In the receive data path, high speed side data received on the HSRX*P/N pins is deserialized,

phase corrected by the receive FIFO, and serialized again before it is output through the OUT*0P/N pins. All

SERDES controls such as pre-emphasis, swing, equalizer in registers HS/LS_SERDES_CONTROL_*, and

loopback modes are supported as in the 2:1 and 4:1 modes.

HS PRBS

Generator

10

20

LS PRBS

Verifier

INA0P/N

HSTXAP/N

TX FIFO

High

Speed

Side

Low

Speed

Side

10

20

SERDES

HSRXAP/N

OUTA0P/N

RX FIFO

HS PRBS

Verifier

LS PRBS

Generator

Figure 7. 1:1 Mode Transmit and Receive Data Paths

The 1:1 mode only uses lane 0 on the low speed side and is enabled by setting TX_MODE_SEL and

RX_MODE_SEL to 1 (1.13:12 = 2'b11) per channel. The maximum data rate supported in the 1:1 mode is

5Gbps. The minimum data rate supported is 1Gbps. LS_OK_OUT_* status pin should be ignored. If needed for

monitoring the link status, only PLL lock and LOS are relevant.

The latency measurement function is not supported in the 1:1 mode. In the 1:1 mode, the High Speed Channel

Sync (register F.10) and Low Speed Lane 0 Channel Sync (register 15.8) are not part of their respective data

paths.

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In the 1:1 mode, the data path supports non-8B/10B encoded data, e.g. PRBS.

In this mode, any registers related to lane 1, 2, or 3 are not used or do not apply. In addition, the following

registers do not apply:

•

1.11:8

9.8:4

C, D, 15(except 15.10), 16, 17, 18, 1D

F.14, F.10, F.8, F.3:2

Lane Alignment Scheme

Lower rate multi-lane serial signals per channel must be byte aligned and lane aligned such that high speed

multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10002 implements

a special lane alignment scheme on the low speed (LS) side.

During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS

transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte

boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate

data ordering is restored.

Lane alignment completes successfully when the LS receiver asserts a “Link Status OK” signal monitored by the

LS transmitter on the link partner device such as an FPGA. The TLK10002 sends out the “Link Status OK”

signals through the LS_OK_OUT_A/B output pins, and monitors the “Link Status OK” signals from the link

partner device through the LS_OK_IN_A/B input pins. If the link partner device does not need the TLK10002

Lane Align Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A/B can be tied high on the

application board.

The lane alignment scheme is activated under any of the following conditions:

•

Device/System power up (after configuration/provisioning)

Loss of channel synchronization assertion on any enabled LS lane

Loss of signal assertion on any enabled LS lane

LS SERDES PLL Lock indication deassertion

After device configuration change

After software determined LS 8B/10B decoder error rate threshold exceeded

After device reset is deasserted

Anytime the LS receiver deasserts “Link Status OK”.

Presence of reoccurring higher level / protocol framing errors

The block diagram of the lane alignment scheme is shown in Figure 8.

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Protocol FPGA (Channel A Only )

TLK10002 (Channel A Only )

LAS

LS _OK_OUT_A

Lane Alignment Slave

LAM

CH

SYNC

?

10B 8B

?

8B 10B

Lane

Alignment

Master

CH

SYNC

CH

SYNC

?

10B 8B

?

8B 10B

Lane

Align

INA[3:0]P/N

?

10B 8B

?

8B 10B

Low

Speed

Side

Low

Speed

Side

CH

SYNC

?

10B 8B

?

8B 10B

SERDES

Channel A

(4 RX/ 4 TX)

SERDES

Channel A

(4RX / 4 TX)

CH

SYNC

CH

SYNC

CH

SYNC

CH

SYNC

?

8B 10B

?

10B 8B

LAM

Lane

Alignment

Master

?

8B 10B

?

10B 8B

Lane

Align

OUTA[3:0]P/N

?

8B 10B

?

10B 8B

?

8B 10B

?

10B 8B

LAS

Lane Alignment Slave

LS _OK _IN_A

Figure 8. Block Diagram of the Lane Alignment Scheme

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Lane Alignment Components

•

Lane Alignment Master (LAM)

–

Responsible for generating proprietary LS lane alignment initialization pattern

Resides in the TLK10002 LS receiver (one instance in Channel A, one instance in Channel B)

–

Responsible for bringing up LS receive link for the data sent from the TLK10002 to a link partner

device

–

Monitors the LS_OK_IN_A/B pins for “Link Status OK” signals sent from the Lane Alignment Slave

(LAS) of the link partner device

–

Resides in the link partner device (one instance in Channel A, one instance in Channel B)

–

Responsible for bringing up LS transmit link for the data sent from the link partner device to the

TLK10002

–

Monitors the “Link Status OK” signals sent from the LS_OK_OUT_A/B pins of the Lane Alignment

Slave (LAS) of the TLK10002

•

Lane Alignment Slave (LAS)

–

Responsible for monitoring the LS lane alignment initialization pattern

Performs channel synchronization per lane (2 or 4 lanes) through byte rotation

Performs lane alignment and realignment of bytes across lanes

Resides in the TLK10002 LS transmitter (one instance in Channel A, one instance in Channel B)

–

Generates the “Link Status OK” signal for the LAM on the link partner device

Resides in the link partner device (one instance in Channel A, one instance in Channel B)

Generates the “Link Status OK” signal for the LAM on the TLK10002 device.

–

Lane Alignment Operation

During lane alignment, the LS transmitter (LAM) sends a repeating pattern of 49 characters (control + data)

simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders

in parallel. The proprietary lane alignment pattern consists of the following characters:

/K28.5/ (CTL=1, Data=0xBC)

Repeat the following sequence of 12 characters four times:

/D30.5/ (CTL=0, Data=0xBE)

/D23.6/ (CTL=0, Data=0xD7)

/D3.1/ (CTL=0, Data=0x23)

/D7.2/ (CTL=0, Data=0x47)

/D11.3/ (CTL=0, Data=0x6B)

/D15.4/ (CTL=0, Data=0x8F)

/D19.5/ (CTL=0, Data=0xB3)

/D20.0/ (CTL=0, Data=0x14)

/D30.2/ (CTL=0, Data=0x5E)

/D27.7/ (CTL=0, Data=0xFB)

/D21.1/ (CTL=0, Data=0x35)

/D25.2/ (CTL=0, Data=0x59)

The above 49-character sequence is repeated until LS_OK_IN_A/B is asserted. Once LS_OK_IN_A/B is

asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately.

The TLK10002 performs lane alignment across the lanes similar in fashion to the IEEE 802.3ae-2002 (XAUI)

specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state

machine is shown in Figure 9. The comma (K28.5) character is used for lane to lane alignment instead of XAUI’s

/A/ character.

Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that

the LS_OK_IN_A/B signal is asserted, normal system traffic is carried instead of the proprietary lane alignment

pattern.

Channel Synchronization is performed during lane alignment and normal system operation.

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Hard or Soft Reset

Loss of Lane

Alignment

(enable deskew)

Deassert LS_OK_OUT

/C/ &

CH_SYNC?

no

Align Detect 3

yes

any

deskew_err

!deskew_err

& /C/

no

Align Detect 1

(disable deskew)

yes

any

deskew_err

!deskew_err

& /C/

Lane Aligned

(Assert LS_OK_OUT)

no

yes

Any Lane

Realign

Conditions?

yes

no

Align Detect 2

any

deskew_err

!deskew_err

& /C/

no

/C/ = Character matched In All Enabled Lanes

deskew_err = Character matched in any lane,

but not in all lanes at same time

yes

CH_SYNC = Channel Sync Asserted All Lanes

Figure 9. Lane Alignment State Machine

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Channel Synchronization

The TLK10002 performs channel synchronization per lane as per IEEE802.3-2002 Figure 36–9 Synchronization

state diagram and as shown in the flowchart of Figure 10.

Reset | LOS(Loss of Signal)

Loss Of Sync

(Enable Alignment)

No Comma

Sync Status Not Ok

Comma

Comma Detect 1

(Disable Alignment)

!Comma & !Invalid Decode

Invalid Decode

Comma

Comma Detect 2

Comma

!Comma & !Invalid Decode

Comma Detect 3

Comma

!Comma & !Invalid Decode

Note:

If HS_CH_SYNC_HYSTERESIS[1:0] (1.11:10)/

LAS_CH_SYNC_HYST_SEL[1:0] (C.11:10) is equal to

2'b00), machine operates as drawn.

A

If HS_CH_SYNC_HYSTERESIS[1:0] (1.11:10)/

LAS_CH_SYNC_HYST_SEL[1:0] (C.11:10) is equal to 2'b01/

2'b10/2'b11, then a transition from all Sync Acquired states

occurs immediately upon detection of 1, 2, or 3 adjacent

invalid code words or disparity errors respectively.

Sync Acquired 1

(Sync Status Ok)

Invalid

Decode

B

Sync Acquired 2

(good cgs = 0)

Sync Acquired 2A

good cgs++

!Invalid Decode &

good_cgs !=3

!Invalid

Decode

!invalid Decode &

good_cgs=3

Invalid

Decode

C

A

Invalid Decode

Sync Acquired 3

(good cgs = 0)

Sync Acquired 3A

good cgs++

!Invalid

Decode

!Invalid Decode &

good_cgs !=3

!invalid Decode &

good_cgs=3

Invalid

Decode

B

Invalid Decode

Sync Acquired 4

(good cgs = 0)

Sync Acquired 4A

good cgs++

!Invalid

Decode

!Invalid Decode &

good_cgs !=3

Invalid

Decode

!invalid Decode &

good_cgs=3

C

Invalid Decode

Figure 10. Channel Synchronization Flowchart

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Line Rate, SERDES PLL Settings, and Reference Clock Selection

The TLK10002 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low

speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers are available

for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies

for various applications.

The external differential reference clock has a large operating frequency range allowing support for many

different applications. The reference clock frequency must be within 200 PPM of the incoming serial data rate

(±100 PPM of nominal data rate), and have less than 40ps of jitter. The following table shows a summary of line

rates and reference clock frequencies used for CPRI/OBSAI for the 1:1, 2:1, and 4:1 operation modes.

Table 3. Specific Line Rate Selection for the 1:1 Operation Mode

LOW SPEED SIDE

HIGH SPEED SIDE

LINE RATE

(Mbps)

SERDES PLL

MULTIPLIER

REFCLKP/N

(MHz)

LINE RATE

(Mbps)

SERDES PLL

MULTIPLIER

REFCLKP/N

(MHz)

RATE

4915.2

3840

20

12.5

10

Full

Half

122.88

153.6

4915.2

3840

20

12.5

10

Half

122.88

153.6

3072

153.6

3072

Half

153.6

2457.6

1920

8/10

12.5

10

153.6/122.88

153.6

2457.6

1920

16/20

12.5

10

Quarter

Eighth

153.6/122.88

153.6

1536

153.6

1536

153.6

1228.8

8/10

153.6/122.88

1228.8

16/20

153.6/122.88

Table 4. Specific Line Rate Selection for the 2:1 Operation Mode

LOW SPEED SIDE

HIGH SPEED SIDE

LINE RATE

(Mbps)

SERDES PLL

MULTIPLIER

REFCLKP/N

(MHz)

LINE RATE

(Mbps)

SERDES PLL

MULTIPLIER

REFCLKP/N

(MHz)

RATE

4915.2

3840

20

12.5

10

Full

122.88

153.6

9830.4

7680

20

Full

122.88

153.6

12.5

3072

Full

153.6

6144

10

Full

153.6

2457.6

1920

8/10

12.5

10

Full

153.6/122.88

153.6

4915.2

3840

16/20

12.5

Half

153.6/122.88

153.6

Half

1536

Half

153.6

3072

10

Half

153.6

1228.8

768

8/10

10

Half

153.6/122.88

153.6

2457.6

1536

16/20

10

Quarter

Eighth

153.6/122.88

153.6

Quarter

614.4

8/10

153.6/122.88

1228.8

16/20

153.6/122.88

Table 5. Specific Line Rate Selection for the 4:1 Operation Mode

LOW SPEED SIDE

HIGH SPEED SIDE

LINE RATE

(Mbps)

SERDES PLL

MULTIPLIER

REFCLKP/N

(MHz)

LINE RATE

(Mbps)

SERDES PLL

REFCLKP/N

(MHz)

RATE

MULTIPLIER

16/20

10

2457.6

1536

8/10

10

Full

Half

153.6/122.88

153.6

9830.4

6144

Full

153.6/122.88

153.6

1228.8

768

8/10

10

Half

153.6/122.88

153.6

4915.2

3072

16/20

10

Half

153.6/122.88

153.6

Quarter

Half

614.4

8/10

153.6/122.88

2457.6

16/20

Quarter

153.6/122.88

The above tables indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6MHz and

122.88MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has

been given for each reference clock frequency respectively. For each channel, the low speed side and the high

speed side SERDES use the same reference clock frequency. Note that Channel A and B are independent and

their application rates and references clocks are separate.

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For other line rates not shown in Table 4 and Table 5, valid reference clock frequencies can be selected with the

help of the information provided in Table 6 and Table 7 for the low speed side and high speed side SERDES.

The reference clock frequency has to be the same for the two SERDES and must be within the specified

valid ranges for different PLL multipliers.

Table 6. Line Rate and Reference Clock Frequency Ranges for the Low Speed Side SERDES

SERDES PLL

MULTIPLIER (MPY)

REFERENCE CLOCK

(MHz)

FULL RATE

(Gbps)

HALF RATE

(Gbps)

QUARTER RATE

(Gbps)

MIN

250

MAX

425

MIN

MAX

MIN

MAX

1.7

MIN

0.5

MAX

0.85

1.0625

1.25

4

5

2

3.4

4.25

5

1

200

425

2.125

2.5

0.5

6

166.667

125

416.667

312.5

250

2

1

0.5

8

2

5

1

2.5

0.5

10

12

12.5

15

20

122.88

2.4576

2.94912

3.072

3.6864

4.9152

5

1.2288

1.47456

1.536

1.8432

2.4576

2.5

0.6144

0.73728

0.768

0.9216

1.2288

208.333

200

5

2.5

5

2.5

166.667

125

5

2.5

5

2.5

RateScale: Full Rate = 0.5, Half Rate = 1, Quarter Rate = 2

Table 7. Line Rate and Reference Clock Frequency Ranges for the High Speed Side SERDES

REFERENCE CLOCK

(MHz)

FULL RATE

(Gbps)

HALF RATE

(Gbps)

QUARTER RATE

(Gbps)

EIGHTH RATE

(Gbps)

SERDES PLL

MULTIPLIER (MPY)

Min

375

Max

425

Min

Max

Min

Max

3.4

4.25

5

Min

1.5

Max

1.7

Min

Max

4

5

6

6.8

8.5

10

3

300

425

6

3

1.5

2.125

2.5

1

1.0625

1.25

6

250

416.667

312.5

250

1.5

1

8

187.5

150

6

3

5

1.5

2.5

1

10

12

12.5

15

16

20

6

3

5

1.5

2.5

1

125

208.333

200

6

3

5

1.5

2.5

1

153.6

122.88

7.68

7.3728

7.864

9.8304

3.84

3.6864

3.932

4.9152

5

1.92

1.8432

1.966

2.4576

2.5

1

166.667

156.25

125

5

2.5

1

5

2.5

5

2.5

1.2288

RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1, Eighth Rate = 2

For example, in the 2:1 operation mode, if the low speed side line rate is 1.485Gbps, the high-speed side line

rate will be 2.97Gbps. The following steps can be taken to make a reference clock frequency selection:

1. Determine the appropriate SERDES rate modes that support the required line rates. Table 6 shows that the

1.485Gbps line rate on the low speed side is only supported in the half rate mode (RateScale = 1). Table 7

shows that the 2.97Gbps line rate on the high speed side is only supported in the quarter rate mode

(RateScale = 1).

2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference

clock frequencies using the formula:

Reference Clock Frequency = (LineRate x RateScale)/MPY

The computed reference clock frequencies are shown in Table 8 along with the valid minimum and maximum

frequency values.

3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall

outside the allowed range. In this example, the common frequencies are highlighted in Table 8.

4. Select any of the remaining marked common reference clock frequencies. Higher reference clock

frequencies are generally preferred. In this example, any of the following reference clock frequencies can be

selected: 148.5MHz, 185.625MHz, 247.5MHz, 297MHz, and 371.25MHz.

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Table 8. Reference Clock Frequency Selection Example

LOW SPEED SIDE SERDES

HIGH SPEED SIDE SERDES

REFERENCE CLOCK FREQUENCY

(MHz)

REFERENCE CLOCK FREQUENCY

(MHz)

SERDES

PLL

MULTIPLIER

SERDES PLL

MULTIPLIER

COMPUTED

MIN

250

MAX

425

COMPUTED

742.5

594

MIN

375

MAX

425

4

5

371.25

297

4

5

200

425

300

425

6

247.5

185.625

148.5

123.75

118.8

99

166.667

125

416.667

312.5

250

6

495

250

425

8

371.25

297

187.5

150

390.625

312.5

10

12

12.5

15

20

122.88

10

12

12.5

15

16

20

208.333

200

247.5

237.6

198

125

260.417

250

153.6

122.88

166.667

125

208.333

195.3125

156.25

74.25

185.625

148.5

Clocking Architecture

A simplified clocking architecture for the TLK10002 is captured in Figure 11. Each channel (Channel A or

Channel B) has an option of operating with a differential reference clock provided either on pins REFCLK0P/N or

REFCLK1P/N. The choice is made either through MDIO or through REFCLKA_SEL and REFCLKB_SEL pins.

The reference clock frequencies for those two clock inputs can be different as long as they fall under the valid

ranges shown in Table 7. For each channel, the low speed side SERDES, high speed side SERDES and the

associated part of the digital core operate from the same reference clock.

The clock and data recovery (CDR) function of the high speed side receiver recovers the clock from the incoming

serial data. The high speed side SERDES makes available two versions of clocks for further processing:

1. HS_RXBCLK_A/B: recovered byte clock synchronous with incoming serial data and with a frequency

matching the incoming line rate divided by 20.

2. VCO_CLOCK_A/B_DIV2: VCO frequency divided by 2. (VCO frequency = REFCLK x PLL Multiplier).

The above-mentioned clocks can be output through the differential pins, CLKOUTAP/N and CLKOUTBP/N, with

optional frequency division ratios of 1, 2, 4, 5, 8, 10, 16, 20, or 25. The clock output options are software

controlled through the MDIO interface register bits 1.3:2, and 1.7:4. The maximum CLKOUT frequency is

500MHz.

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Low

Speed

Side

High

Speed

Side

HS_RXBCLK_A

INA [3:0]P/N

HSTXAP /N

VCO_CLOCK_A_DIV2

SERDES

OUTA [3:0]P/N

HSRXAP /N

Channel A

A S /W

2

Reg: 1.3:2

Reg: 1.7:4

_SEL

REFCLKA

4

Divide by N

+

_

CLKOUTAP/N

CLKOUTBP/N

(N= 1,2,4,5,8,

10,16,20,25)

+

_

0P/N

1P/N

REFCLK

Divide by N

+

_

+

_

,

(N= 1,2,4,5,8

10,16,20,25)

4

2

B S/W

_SEL

REFCLKB

Reg: 1.3:2

Reg: 1.7:4

Low

Speed

Side

High

Speed

Side

/N

HSTXBP

INB [3:0]P/N

VCO_CLOCK _B_DIV2

HS_RXBCLK_B

SERDES

Channel B

SERDES

Channel B

/N

HSRXBP

OUTB [3:0]P/N

Figure 11. Clocking Architecture

Loopback Modes

The TLK10002 provides two high speed side (remote) and two low speed side (local) loopback modes for

self-test and system diagnostic purposes. The details of those loopback modes are discussed below.

Deep Remote Loopback

The deep remote loopback is as shown Figure 12 for Channel A. The configuration is the same for Channel B.

The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is

accepted on the high speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the entire receive

data path excluding the CML driver and receive sense amps on the low speed side SERDES, returned through

the entire transmit data path and sent out through the high speed side transmit SERDES pins (HSTXAP/N or

HSTXBP/N).

The low speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. See MDIO register

bit 6.7 for more information. The OUTA*P/N and OUTB*P/N pins must be correctly terminated.

The link partner connected through INA*P/N or INB*P/N pins must be electrically idle at differential zero

with P and N signals at the same voltage. The TLK10002 device needs some time for lane alignment before

passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local

LS_OK_OUT_A/B.

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10

16

3 2

INA0P/N

TX FIFO

LS PRBS

Verifier

20

HSTXAP/N

16

HS PRBS

Generator

INA1P/N

INA2P/N

1

0

Pattern

Generator

10

INA3P/N

High

Speed

Side

Low

Speed

Side

10

16

20

32

OUTA0P/N

OUTA1P/N

SERDES

RX FIFO

10

OUTA2P/N

OUTA3P/N

HS PRBS

Verifier

LS PRBS

Generator

10

/N

HSRXAP

Pattern

Verifier

Figure 12. Deep Remote Loopback

Shallow Remote Loopback and Serial Retime

The shallow remote loopback is as shown in Figure 13 for Channel A. The configuration is the same for Channel

B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is

accepted on the high speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the receive data

path and looped back before the low speed SERDES, returned through the transmit data path and sent out

through the high speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).

The low speed side transmit path SERDES can be optionally enabled or disabled but the PLL needs to be

enabled to provide the required clock.

The low speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. The OUTA*P/N

and OUTB*P/N pins must be correctly terminated. The TLK10002 device needs some time for lane alignment

before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local

LS_OK_OUT_A/B.

This loopback mode can be used for high speed serial retime operation.

10

16

32

INA0P/N

LS PRBS

Verifier

TX FIFO

10

HSTXAP /N

20

HS PRBS

Generator

16

INA1P/N

INA2P/N

1

0

Pattern

Generator

10

INA3P/N

High

Speed

Side

Low

Speed

Side

10

16

OUTA0P/N

OUTA1P/N

32

SERDES

RX FIFO

10

OUTA2P/N

OUTA3P/N

HS PRBS

Verifier

LS PRBS

Generator

10

HSRXAP /N

Pattern

Verifier

Figure 13. Shallow Remote Loopback

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Deep Local Loopback

The deep local loopback mode is as shown in Figure 14 for Channel A. The configuration is the same for

Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode,

the data is accepted on the low speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit

data path excluding the CML driver, returned through the entire receive data path and sent out through the low

speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time for lane alignment

before passing traffic. The high speed side outputs on HSTXAP/N or HSTXBP/N pins are available for

monitoring.

10

16

32

INA0P/N

LS PRBS

Verifier

TX FIFO

10

HSTXAP /N

20

HS PRBS

Generator

16

INA1P/N

INA2P/N

1

0

Pattern

Generator

10

INA3P/N

High

Speed

Side

Low

Speed

Side

10

16

OUTA0P/N

OUTA1P/N

32

SERDES

RX FIFO

10

OUTA2P/N

OUTA3P/N

HS PRBS

Verifier

LS PRBS

Generator

10

HSRXAP /N

Pattern

Verifier

Figure 14. Deep Local Loopback

Shallow Local Loopback

The shallow local loopback mode is as shown in Figure 15 for Channel A. The configuration is the same for

Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode,

the data is accepted on the low speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit

data path excluding the high speed side SERDES, returned through the entire receive data path and sent out

through the low speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time

for lane alignment before passing traffic. The high speed side outputs on HSTXAP/N or HSTXBP/N pins are

available for monitoring.

10

16

32

INA0P/N

LS PRBS

Verifier

TX FIFO

10

HSTXAP /N

20

HS PRBS

Generator

16

INA1P/N

INA2P/N

1

0

Pattern

Generator

10

INA3P/N

High

Speed

Side

Low

Speed

Side

10

16

OUTA0P/N

OUTA1P/N

32

SERDES

RX FIFO

10

OUTA2P/N

OUTA3P/N

HS PRBS

Verifier

LS PRBS

Generator

10

HSRXAP /N

Pattern

Verifier

Figure 15. Shallow Local Loopback

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Test Pattern Generation and Verification

The TLK10002 has an extensive suite of built in test functions to support system diagnostic requirements. Each

channel has sets of internal test pattern generators and verifiers.

Several patterns can be selected via the MDIO interface that offer extensive test coverage. The low speed side

supports generation and verification of pseudo-random bit sequence (PRBS) 2⁷-1, 2²³-1, and 2³¹-1 patterns. In

addition to those PRBS patterns, the high speed side supports High-frequency (HF), Low-frequency (LF),

Mixed-frequency (MF), and continuous random test pattern (CRPAT) long/short pattern generation and

verification as defined in Annex 48A of the IEEE Standard 802.3ae-2002. Use of CRPAT verifier requires

checking TPsync (MDIO register bit F.15).

The TLK10002 provides two pins: PRBSEN and PRBS_PASS, for additional and easy control and monitoring of

PRBS pattern generation and verification. When the PRBSEN is asserted high, the internal PRBS generator and

verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides of both

channels. This signal is logically OR’d with an MDIO register bits B.7:6 and B.13:12.

PRBS 2³¹-1 is selected by default, and can be changed through MDIO.

When PRBS test is enabled (PRBSEN=1):

•

PRBS_PASS=1 indicates that PRBS pattern reception is error free.

PRBS_PASS=0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed),

and the lane (for low speed side) that this signal refers to is chosen through MDIO register bit 0.3:0.

Latency Measurement Function

The TLK10002 includes a latency measurement function to support CPRI and OBSAI base station applications.

There are two start and two stop locations for the latency counter as shown in Figure 16 for Channel A. The start

and stop locations are selectable through MDIO register bits 0x16.7 and 0x16.6 respectively. The elapsed time

from a comma detected at an assigned counter start location of a particular channel to a comma detected at an

assigned counter stop location of the same channel is measured and reported through the MDIO interface. The

function operates on one channel at a time. The following three control characters (containing commas) are

monitored:

1. K28.1 (control = 1, data = 0x3C)

2. K28.5 (control = 1, data = 0xBC)

3. K28.7 (control = 1, data = 0xFC).

The first comma found at the assigned counter start location will start up the latency counter. The first comma

detected at the assigned counter stop location will stop the latency counter. The 20-bit latency counter result of

this measurement is readable through the MDIO interface through register bits 0x17.3:0 and 0x18.15:0. The

accuracy of the measurement is a function of the serial bit rate at which the channel being measured is

operating. The register will return a value of 0xFFFF if the duration between transmit and receive comma

detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit

results counter is read. The counter will return zero in cases where a transmit comma was never detected

(indicating the results counter never began counting).

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TLK10002

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Chan nel A

10

32

16

INA0P/N

LS PRBS

Verifier

TX FIFO

HS PRBS

Generator

HSTXAP /N

16

20

INA1P/N

INA2P/N

Pattern

Generator

INA3P/N

Stop

Counter

Start

Counter

High

Speed

Side

Transmit Data Path Covered

Low

Speed

Laten cy

Count er

SERDES

Side

SERDES

Receive Data Path Covered

Stop

Counter

Start

Counter

10

HS PRBS

Verifier

16

20

32

OUTA0P/N

OUTA1P/N

HSRXAP /N

RX FIFO

10

1

0

LS PRBS

Generator

OUTA2P/N

OUTA3P/N

10

Pattern

Verifier

Figure 16. Location of TX and RX Comma Character Detection (Only Channel A Shown)

In high speed side SERDES full rate mode, the latency measurement function runs off of an internal clock whose

rate is equal to the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs

off of an internal clock whose rate is equal to the serial bit rate divided by 4. In quarter rate mode, the latency

measurement function runs off of an internal clock whose rate is equal to the serial bit rate divided by 2. In eighth

rate mode, the latency measurement function runs off of a clock whose rate is equal to the serial bit rate.

The latency measurement does not include the low speed side transmit SERDES blocks contribution as well as

part of the channel synchronization block. The latency introduced by these blocks can be estimated to be up to

(18 + 10) x N high speed side unit intervals (UIs), where the multiplex factor N is equal to 2 (in 2:1 mode) or 4 (in

4:1 mode). The latency measurement also doesn’t account for the low speed side receive SERDES contribution

which is estimated to be up to 20 x N high speed side UIs. The latency contributions of various sections of the

TLK10002 device are shown in Figure 15. Overall, the transmit data path full rate latency contribution is

estimated to be between 462UI and 602UI for the 2:1 mode, and between 798UI and 1058UI for the 4:1 mode.

The respective numbers for the receive data path are between 300UI and 403UI for the 2:1 mode and between

440UI and 623UI for the 4:1 mode.

The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period.

The measurement clock can be divided down if a longer duration measurement is required, in which case the

accuracy of the measurement is accordingly reduced. The high speed latency measurement clock is divided by

either 1, 2, 4, or 8 via register 0x16 bits 5:4. The measurement clock used is always selected by the channel

under test. The high speed latency measurement clock may only be used when operating at one of the serial

rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off

of the recovered byte clock for the channel under test (and gives a latency measurement clock frequency equal

to the serial bit rate divided by 20) via register 0x16 bit 2 (where the register 0x16 bits 5:4 divider value setting is

ignored).

The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 9, and assumes the

latency measurement clock is not divided down per user selection (division is required to measure a duration

greater than 682us). For each division of two in the measurement clock, the accuracy is also reduced by a factor

of two.

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NOTE: Latency numbers represent no external skew between lanes. External lane skew will increase overall latency. TX

Datapath latency includes 20xN UI of variance due to deserialization and channel sync.

Figure 17. Latency Variance and Contributions (Only Channel A Shown)

Table 9. CPRI/OBSAI Latency Measurement Function Accuracy

(Undivided Measurement Clock)

LINE RATE

(Gbps)

LATENCY CLOCK FREQUENCY

(GHz)

ACCURACY

RATE

(± ns)

1.2288

1.536

2.4576

3.072

3.84

Eighth

Quarter

Half

1.2288

0.768

1.2288

0.768

0.96

0.8138

1.302

0.8138

1.302

Half

1.0417

0.8138

1.302

4.9152

6.144

7.68

Half

1.2288

0.768

0.96

Full

1.0417

0.8138

9.8304

Full

1.2288

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TLK10002

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Power Down Mode

The TLK10002 can be put in power down either through device inputs pins or through MDIO control register

(1.15).

PDTRXA_N: Active low, powers down channel A.

PDTRXB_N: Active low, powers down channel B.

The MDIO management serial interface remains operational when in register based power down mode (1.15

asserted for both channels), but status bits may not be valid since the clocks are disabled. The low speed side

and high speed side SERDES outputs are high impedance when in power down mode. Please see the detailed

per pin description for the behavior of each device I/O signal during pin based and register based power down.

High Speed CML Output

The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up

resistors, requiring no external components. The transmit outputs must be AC coupled.

HSTXAP

HSRXAP

50 W transmission line

50 W

0.8*VDDT

50 W

GND

50 W transmission line

HSTXAN

HSRXAN

TRANSMITTER

MEDIA

RECEIVER

Figure 18. Example of High Speed I/O AC Coupled Mode (Channel A HS Side is Shown)

Current Mode Logic (CML) drivers often require external components. The disadvantage of the external

component is a limited edge rate due to package and line parasitic. The CML driver on TLK10002 has on-chip

50Ω termination resistors terminated to VDDT, providing optimum performance for increased speed

requirements. The transmitter output driver is highly configurable allowing output amplitude and de-emphasis to

be tuned to a channel's individual requirements. Software programmability allows for very flexible output

amplitude control. Only AC coupled output mode is supported.

When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is

attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed on an

oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to

provide equalization for the high frequency loss, 3-tap finite impulse response (FIR) transmit de-emphasis is

implemented. A highly configurable output driver maximizes flexibility in the end system by allowing de-emphasis

and output amplitude to be tuned to a channel’s individual requirements. Output swing is controlled via MDIO.

Figure 27 illustrates the output waveform flexibility. The level of de-emphasis is programmable via the MDIO

interface through control registers (5.7:4 and 5.12:8) through pre-cursor and post-cursor settings. Users can

control the strength of the de-emphasis to optimize for a specific system requirement.

High Speed Receiver

The high speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling.

The termination impedances of the receivers are configured as 100 Ohms with the center tap weakly tied to

0.8*VDDT with a capacitor to create an AC ground.

TLK10002 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by

amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be

enabled or disabled via register settings. Both the gain and bandwidth of the equalizer are controlled by the

receiver equalization logic.

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Loss of Signal Indication (LOS)

Loss of input signal detection is based on the voltage level of each serial input signal INA*P/N, INB*P/N,

HSRXAP/N, and HSRXBP/N. When LOS indication is enabled and a channel's differential serial receive input

level is < 75mVpp, that channel's respective LOS indicator (LOSA or LOSB) will be asserted (high true). If the

input signal is >150mVpp, the LOS indicator will be deasserted (low false). Outside of these ranges, the LOS

indication is undefined. The LOS indicators are also directly readable through the MDIO interface.

The following additional critical status conditions can be combined with the loss of signal condition enabling

additional real-time status signal visibility on the LOSA and LOSB outputs per channel:

1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of

channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated

LOS condition (per channel).

2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The

internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated

loss of signal conditions (per channel).

3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS

condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error)

is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per

channel).

4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when

enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default)

with the other internally generated loss of signal conditions (per channel).

5. AZDONE (Auto Zero Calibration Done) – Inverted and Logically OR’d with LOS conditions(s) when enabled.

HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other

internally generated loss of signal conditions (per channel).

Figure 19 shows the detailed implementation of the LOSA signal along with the associated MDIO control

registers.

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TLK10002

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Loss of Signal (HS Ch A)

ENABLE (9.0)

LOS INA0

ENABLE (A.0)

LOS INA1

ENABLE (A.1)

LOS INA2

Loss of Signal (LS Ch A)

ENABLE (A.2)

LOS INA3

ENABLE (A.3)

PLL Locked (HS Ch A)

ENABLE (9.1)

PLL Locked (LS Ch A)

ENABLE (A.12)

8B/10B Invalid Code(HS Ch A)

ENABLE (9.4)

8B/10B Invalid Code INA0

ENABLE (A.4)

LOSA

8B/10B Invalid Code INA1

ENABLE (A.5)

8B/10B Invalid Code (LS Ch A)

8B/10B Invalid Code INA2

ENABLE (A.6)

8B/10B Invalid Code INA3

ENABLE (A.7)

Loss of Ch. Sync (HS Ch A)

ENABLE (9.5)

Loss of Sync INA0

ENABLE (A.8)

Loss of Sync INA1

ENABLE (A.9)

Loss of Ch. Sync (LS Ch A)

Loss of Sync INA2

ENABLE (A.10)

Loss of Sync INA3

ENABLE (A.11)

AGCLOCK (HS Ch A)

ENABLE (9.3)

AZDONE (HS Ch A)

ENABLE (9.2)

NOTE: LOSA is asserted (driven high) duriing a failing condition, and deasserted (driven low) otherwise. Any combinations of

status signals may be enabled onto LOSA/B on MDIO register bits indicated above. LOSB circuit is similar.

Figure 19. LOSA – Logic Circuit Implementation

MDIO Management Interface

The TLK10002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the

IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.

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The MDIO Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC). The port address

is determined by control pins PRTAD[4:0] as described in Table 1.

In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2 individual

channels in TLK10002 are classified as 2 different ports. So for any PRTAD[4:1] value there will be 2 ports per

TLK10002.

TLK10002 will respond if the 4 MSB’s of PHY address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1].

The LSB of PHY address field (PA[0]) will determine which channel/port within TLK10002 to respond to.

If PA[0] = 1'b0, TLK10002 Channel A will respond.

If PA[0] = 1'b1, TLK10002 Channel B will respond.

Write transactions which address an invalid register or device or a read only register will be ignored. Read

transactions which address an invalid register will return a 0.

MDIO Protocol Timing

The Clause 22 timing required to read from the internal registers is shown in Figure 20. The Clause 22 timing

required to write to the internal registers is shown in Figure 21.

MDC

Pu(1)

0

1

0

PA4 PA0 RA4

RA0

D15

D0

0

1

MDIO

Turn

32 "1's"

Read

Code

PHY

Addr

REG

Addr

Around

Data

Idle

Start

Preamble

(1) Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK10002.

Figure 20. CL22 - Management Interface Read Timing

MDC

1

MDIO

0

1

0

1

PA [4 :0]

RA4 RA 0

1

0

D15

D0

32 "1's"

Write

Code

PHY

Addr

REG

Addr

Turn

Around

Start

Data

Idle

Preamble

Figure 21. CL22 - Management Interface Write Timing

Clause 22 Indirect Addressing

The TLK10002 Register space is divided into two register groups. One register group can be addressed directly

through Clause 22, and one register group can be addressed indirectly through Clause 22. The register group

which can be addressed through Clause 22 indirectly is implemented in the vendor specific register space

(16’h8000 onwards). Due to Clause 22 register space limitations, an indirect addressing method is implemented

so that this extended register space can be accessed through Clause 22. To access this register space

(16’h8000 onwards), an address control register (Reg 30, 5’h1E) should be written with the register address

followed by a read/write transaction to address data register (Reg 31, 5’h1F) to access the contents of the

address specified in address control register.

The following timing diagrams illustrate an example write transaction to Register 16’h8000 using indirect

addressing in Clause 22.

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MDC

MDIO

1

PA [4:0]

5'h1E

1

0

1

0

1

0

16'h8000

Data

32 "1's"

Write

Code

PHY

Addr

REG

Addr

Turn

Around

Start

Idle

Preamble

Figure 22. CL22 – Indirect Address Method – Address Write

MDC

1

MDIO

PA [4 :0]

1

0

1

0

1

5'h 1F

0

DATA

Data

32 "1's"

Write

Code

PHY

Addr

REG

Addr

Turn

Around

Start

Idle

Preamble

Figure 23. CL22 - Indirect Address Method – Data Write

The following timing diagrams illustrate an example read transaction to read contents of Register 16’h8000 using

indirect addressing in Clause 22.

MDC

1

MDIO

PA [4:0]

1

0

1

0

1

5'h1E

0

16'h8000

Data

32 "1's"

Write

Code

PHY

Addr

REG

Addr

Turn

Around

Start

Idle

Preamble

Figure 24. CL22 - Indirect Address Method – Address Write

MDC

Pu(1)

0

1

0

PA4 PA0

D15

D0

5'h1F

0

1

MDIO

Turn

32 "1's"

Read

Code

PHY

Addr

REG

Addr

Around

Data

Idle

Start

Preamble

(1) Note that the 1 in the Turn Around section is externally pulled up, and driven to Zero by TLK10002.

Figure 25. CL22 - Indirect Address Method – Data Read

The IEEE 802.3 Clause 22 specification defines many of the registers, and additional registers have been

implemented for expanded functionality.

PROGRAMMERS' REFERENCE

The following registers can be addressed directly through MDIO Clause 22. Channel identification is based on

PHY (Port) address field. Channel A can be accessed by setting LSB of PHY address to 0. Channel B can be

accessed by setting LSB of PHY address to 1. Control registers 0x01 through 0x0E are specific to the channel

addressed. Status registers 0x0F through 0x15, and 0x1D report the status of the channel addressed. The rest

are global control/status registers and are channel independent. Please note that the N.x:y register numbering

format is used in this document, where N is a hexadecimal register number, and x:y is a register bit number

range in decimal format. For example, B.10:8 denotes bits 10, 9, and 8 of register address 0x0B.

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REGISTER BIT DEFINITIONS

RW: Read-Write

User can write 0 or 1 to this register bit. Reading this register bit returns the same value that has been written.

RW/SC: Read-Write Self-Clearing

User can write 0 or 1 to this register bit. Writing a "1" to this register creates a high pulse. Reading this register

bit always returns 0.

RO: Read-Only

This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its

current value.

RO/LH: Read-Only Latched High

This register can only be read. Writing to this register bit has no effect. Reading a "1" from this register bit

indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "0"

from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last

time the register was read. A latched high register, when read high, should be read again to distinguish if a

condition occurred previously or is still occurring. If it occurred previously, the second read will read low. If it is

still occurring, the second read will read high. Reading this register bit automatically resets its value to 0.

RO/LL: Read-Only Latched Low

This register can only be read. Writing to this register bit has no effect. Reading a "0" from this register bit

indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a "1"

from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last

time the register was read. A latched low register, when read low, should be read again to distinguish if a

condition occurred previously or is still occurring. If it occurred previously, the second read will read high. If it is

still occurring, the second read will read low. Reading this register bit automatically sets its value to 1.

COR: Clear-On-Read

This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its

current value, then resets its value to 0.

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GLOBAL_CONTROL_1 — Address: 0x00 Default: 0x0600

BIT(s)

NAME

DESCRIPTION

ACCESS

Global reset (Channel A & B).

0 = Normal operation (Default 1’b0)

RW

SC⁽¹⁾

0.15

GLOBAL_RESET

1 = Resets TX and RX datapath including MDIO registers. Equivalent to

asserting RESET_N.

Global write enable.

0 = Control settings written to Registers 0x01-0x0E are specific to channel

0.11

GLOBAL_WRITE

addressed (Default 1’b0)

RW

1 = Control settings written to Registers 0x01-0x0E are applied to both

Channel A and Channel B regardless of channel addressed

0.10:8

0.7

RESERVED

For TI use only (Default 3’b110)

For TI use only (Default 1’b0)

RW

PRBS_PASS pin status selection. Applicable only when PRBS test pattern

verification is enabled on HS side or LS side. PRBS_PASS pin reflects PRBS

verification status on selected Channel HS/LS side

0000 = Status from Channel A HS SERDES side(Default 4’b0000)

0001 = Reserved

Reserved

001x =

0100 = Status from Channel A LS SERDES side Lane 0

0101 = Status from Channel A LS SERDES side Lane 1

0110 = Status from Channel A LS SERDES side Lane 2

0111 = Status from Channel A LS SERDES side Lane 3

1000 = Status from Channel B HS SERDES side

1001 = Reserved

0.3:0

PRBS_PASS_OVERLAY [3:0]

R/W

101x = Reserved

1100 = Status from Channel B LS SERDES side Lane 0

1101 = Status from Channel B LS SERDES side Lane 1

1110 = Status from Channel B LS SERDES side Lane 2

1111 = Status from Channel B LS SERDES side Lane 3

(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

CHANNEL_CONTROL_1 — Address: 0x01 Default: 0x0300

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

Setting this bit high powers down entire data path with the exception that MDIO

interface stays active.

1.15

POWERDOWN

0 = Normal operation (Default 1’b0)

1 = Power Down mode is enabled.

RX mode selection

RW

1.13

RX_MODE_SEL

TX_MODE_SEL

0 = RX mode dependent upon RX_DEMUX_SEL (1.9) (Default 1’b0)

1 = Enables 1 to 1 mode on receive channel

TX mode selection

RW

1. 12

0 = TX mode dependent upon TX_DEMUX_SEL (1.8) (Default 1’b0)

1 = Enables 1 to 1 mode on transmit channel

Channel synchronization hysteresis control on the HS receive channel.

00 = The channel synchronization, when in the synchronization state,

performs the Ethernet standard specified hysteresis to return to the

unsynchronized state (Default 2’b00)

01 = A single 8b/10b invalid decode error or disparity error causes the

channel synchronization state machine to immediately transition from

sync to unsync

HS_CH_SYNC_

HYSTERESIS[1:0]

1.11:10

10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the

channel synchronization state machine to immediately transition from

sync to unsync

11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the

channel synchronization state machine to immediately transition from

sync to unsync

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BIT(s)

NAME

DESCRIPTION

ACCESS

RX De-Mux selection control for lane de-serialization on receive channel. Valid only

when RX_MODE_SEL (1.13) is LOW

RW

1.9

RX_DEMUX_SEL

0 = 1 to 2

1 = 1 to 4 (Default 1’b1)

TX Mux selection control for lane serialization on transmit channel. Valid only when

TX_MODE_SEL (1.12) is LOW

RW

1. 8

TX_MUX_SEL

0 = 2 to 1

1 = 4 to 1 (Default 1’b1)

Output clock divide setting. This value is used to divide selected clock (Selected

using CLKOUT_SEL (1.3:2)) before giving it out onto CLKOUTxP/N.

0000 = Divide by 1 (Default 4’b0000)

0001 = RESERVED

0010 = RESERVED

0011 = RESERVED

0100 = Divide by 2

0101 = RESERVED

0110 = RESERVED

0111 = RESERVED

1000 = Divide by 4

1001 = Divide by 8

1010 = Divide by 16

1011 = RESERVED

1100 = Divide by 5

1101 = Divide by 10

1110 = Divide by 20

1111 = Divide by 25

1.7:4

CLKOUT_DIV[3:0]

See Figure 11. Clocking Architecture

Output clock select. Selected Recovered clock sent out on CLKOUTxP/N pins

RW

00 = Selects Channel A HSRX recovered byte clock as output clock (Default

2’b00)

01 = Selects Channel B HSRX recovered byte clock as output clock

10 = Selects Channel A HSRX VCO divide by 2 clock as output clock

11 = Selects Channel B HSRX VCO divide by 2 clock as output clock

See Figure 11. Clocking Architecture

1.3:2

CLKOUT_SEL[1:0]

Channel Reference clock selection. Applicable only when REFCLKx_SEL pin is

LOW.

RW

0 = Selects REFCLK_0_P/N as clock reference to Channel x (Default 1’b0)

1 = Selects REFCLK_1_P/N as clock reference to Channel x

1.1

1.0

REFCLK_ SEL

RESERVED

See Figure 11. Clocking Architecture

For TI use only (Default 1’b0)

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HS_SERDES_CONTROL_1 — Address: 0x02 Default: 0x811D

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

2.15:10 RESERVED

For TI use only (Default 6'b100000)

HS SERDES PLL Loop Bandwidth settings

2.9:8

HS_LOOP_BANDWIDTH[1:0]

RW

00 = Reserved

01 = Applicable when external JC_PLL is NOT used (Default 2’b01)

10 = Applicable when external JC_PLL is used

11 = Reserved

2.7

2.6

RESERVED

For TI use only (Default 1’b0)

RW

HS_VRANGE

HS SERDES PLL VCO range selection. This bit needs to be set HIGH if VCO

frequency (REFCLK * HS_PLL_MULT) is below 2.5GHz

0 = VCO runs at higher end of frequency range (Default 1’b0)

1 = VCO runs at lower end of frequency range

2.5

2.4

RESERVED

HS_ENPLL

For TI use only (Default 1’b0)

RW

HS SERDES PLL enable control. HS SERDES PLL is automatically disabled when

PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.

RW

0 = Disables PLL in HS SERDES

1 = Enables PLL in HS SERDES (Default 1’b1)

2.3:0

HS_PLL_MULT[3:0]

HS SERDES PLL multiplier setting (Default 4’b1101). Refer to Table 10

RW

See Line Rate, SERDES PLL Settings, and Reference Clock Selection section

for more information on PLL multiplier settings

Table 10. High Speed Side SERDES PLL Multiplier Control

2.3:0

VALUE

0000

0001

0010

0011

0100

0101

0110

0111

PLL MULTIPLIER FACTOR

VALUE

1000

1001

1010

1011

1100

1101

1110

1111

PLL MULTIPLIER FACTOR

Reserved

4x

12x

12.5x

15x

5x

16x

6x

16.5x

20x

8x

8.25x

10x

25x

Reserved

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HS_ SERDES_CONTROL_2 — Address: 0x03 Default: 0xA444

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

3.15:12 HS_SWING[3:0]

Transmitter Output swing control for HS SERDES. (Default 4’b1010) Refer to Table 11

For TI use only (Default 1’b0)

3.11

3.10

RESERVED

HS_ENTX

RW

HS SERDES transmitter enable control. HS SERDES transmitter is automatically disabled

when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.

RW

0 = Disables HS SERDES transmitter

1 = Enables HS SERDES transmitter (Default 1’b1)

3.9:8

3.7:6

HS_RATE_TX [1:0]

HS_AGCCTRL[1:0]

HS SERDES TX rate settings

RW

00 = Full rate (Default 2’b00)

01 = Half rate

10 = Quarter rate

11 = Eighth rate

Adaptive gain control loop

00 = Attenuator will not change after lock has been achieved, even if AGC becomes

unlocked

01 = Attenuator will not change when in lock state, but could change when AGC

becomes unlocked (Default 2’b01)

10 = Force the attenuator off.

11 = Force the attenuator on

Auto zero calibration.

3.5:4

HS_AZCAL[1:0]

RW

00 = Auto zero calibration initiated when receiver is enabled (Default 2’b00)

01 = Auto zero calibration disabled

10 = Forced with automatic update.

11 = Forced without automatic update

3.3

HS_ENUNSD

HS_ENRX

0 = Disable use of unscrambled data in HS Serdes Rx (Recommended setting for Full

RW

Rate) (Default 1’b0)

1 = Enable use of unscrambled data in HS Serdes Rx (Recommended setting for Half,

Quarter and Eighth Rates)

3.2

HS SERDES receiver enable control. HS SERDES receiver is automatically disabled when

PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.

0 = Disables HS SERDES receiver

1 = Enables HS SERDES receiver (Default 1’b1)

3.1:0

HS_RATE_RX [1:0]

HS SERDES RX rate settings

00 = Full rate (Default 2’b00)

01 = Half rate

10 = Quarter rate

11 = Eighth rate

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Table 11. High Speed Side SERDES AC Mode Output

Swing Control

AC MODE

VALUE

[15:12]

Typical Amplitude (mVdfpp)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

130

220

300

390

480

570

660

750

830

930

1020

1110

1180

1270

1340

1400

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HS_ SERDES_CONTROL_3 — Address: 0x04 Default: 0xB820

BIT(s)

NAME

DESCRIPTION

ACCESS

4.15

HS_ENTRACK

HSRX ADC Track mode

RW

0 = Normal operation

1 = Forces ADC into track mode (Default 1’b1)

4.14:12

HS_EQPRE[2:0]

SERDES Rx precursor equalizer selection

RW

000 = 1/9 cursor amplitude

001 = 3/9 cursor amplitude

010 = 5/9 cursor amplitude

011 = 7/9 cursor amplitude (Default 3’b011)

100 = 9/9 cursor amplitude

101 = 11/9 cursor amplitude

110 = 13/9 cursor amplitude

111 = Disable

4.11:10

4.9:8

HS_CDRFMULT[1:0] Clock data recovery algorithm frequency multiplication selection

RW

00 = First order. Frequency offset tracking disabled

01 = Second order. 1x mode

10 = Second order. 2x mode (Default 2’b10)

11 = Reserved

HS_CDRTHR[1:0]

Clock data recovery algorithm threshold selection

00 = Four vote threshold (Default 2’b00)

01 = Eight vote threshold

10 = Sixteen vote threshold

11 = Thirty two vote threshold

4.7

4.6

HS_EQLIM

HS_EQHLD

HSRX Equalizer limit control

RW

0 = Normal operation (Default 1’b0)

1 = Limits equalizer DFE tap weights

HSRX Equalizer hold control

0 = Normal operation (Default 1’b0)

1 = Holds equalizer and long tail correction in their current state

4.5

HS_H1CDRMODE

HS_TWCRF[4:0]

0 = CDR locks to h(-1)

RW

1 = CDR locks to h(+1)

4.4:0

Cursor Reduction Factor (Default 5’b00000) Refer to Table 12

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Table 12. High Speed Side SERDES Cursor Reduction Factor Weights

4.4:0

VALUE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

CURSOR REDUCTION (%)

VALUE

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

CURSOR REDUCTION (%)

0

17

20

22

25

27

30

32

35

37

40

42

45

47

50

52

55

2.5

5.0

7.5

10.0

12

15

Reserved

HS_ SERDES_CONTROL_4— Address: 0x05 Default: 0x2000

BIT(s)

NAME

DESCRIPTION

ACCESS

5.15

HS_RX_INVPAIR

Receiver polarity.

RW

0 = Normal polarity. HSRXxP considered positive data. HSRXxN considered negative

data (Default 1’b0)

1 = Inverted polarity. HSRXxP considered negative data. HSRXxN considered positive

data

5.14

5.13

HS_TX_INVPAIR

HS_FIRUPT

Transmitter polarity.

RW

0 = Normal polarity. HSTXxP considered positive data and HSTXxN considered

negative data (Default 1’b0)

1 = Inverted polarity. HSTXxP considered negative data and HSTXxN considered

positive data

HS SERDES Tx pre/post cursor filter update control

0 = Holds last state; any changes to TWCRF, TWPRE, TWPST1/2 will not take effect

until FIRUPT goes high.

1 = Pre/Post cursor fields can be updated by changing respective fields (Default 1’b1)

5.12:8

5.7:4

5.3:0

HS_TWPOST1[4:0]

HS_TWPRE[3:0]

Adjacent post cursor1 Tap weight. Selects TAP settings for TX waveform. (Default 5’b00000)

Refer to Table 13

RW

Precursor Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000)

Refer to Table 15

HS_TWPOST2[3:0]

Adjacent post cursor2 Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000)

Refer to Table 14

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Table 13. High Speed Side SERDES Post-Cursor1 Transmit Tap Weights

5.12:8

VALUE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

TAP WEIGHT (%)

0

VALUE

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

TAP WEIGHT (%)

0

+2.5

–2.5

+5.0

–5.0

+7.5

–7.5

+10.0

+12.5

+15.0

+17.5

+20.0

+22.5

+25.0

+27.5

+30.0

+32.5

+35.0

+37.5

–10.0

–12.5

–15.0

–17.5

–20.0

–22.5

–25.0

–27.5

–30.0

–32.5

–35.0

–37.5

Table 14. High Speed Side SERDES Post-Cursor2 Transmit Tap Weights

5.3:0

VALUE

0000

0001

0010

0011

0100

0101

0110

0111

TAP WEIGHT (%)

VALUE

1000

1001

1010

1011

1100

1101

1110

1111

TAP WEIGHT (%)

0

+2.5

–2.5

+5.0

–5.0

+7.5

–7.5

+10.0

+12.5

+15.0

+17.5

–10.0

–12.5

–15.0

–17.5

Table 15. High Speed Side SERDES Pre-Cursor Transmit Tap Weights

5.7:4

VALUE

0000

0001

0010

0011

0100

0101

0110

0111

TAP WEIGHT (%)

VALUE

1000

1001

1010

1011

1100

1101

1110

1111

TAP WEIGHT (%)

0

+2.5

–2.5

+5.0

–5.0

+7.5

–7.5

+10.0

+12.5

+15.0

+17.5

–10.0

–12.5

–15.0

–17.5

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LS_ SERDES_CONTROL_1 — Address: 0x06 Default: 0xF115

BIT(s)

NAME

DESCRIPTION

ACCESS

6.15:12 LS_LN_CFG_EN[3:0]

Configuration control for LS SERDES Lane settings (Default 4’b1111)

[3] corresponds to LN3, [2] corresponds to LN2

[1] corresponds to LN1, [0] corresponds to LN0

0 = Writes to LS_SERDES_CONTROL_2 (register 0x07) and

RW

LS_SERDES_CONTROL_3 (register 0x08) control registers do not affect

respective LS SERDES lane

1 = Writes to LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3

control registers affect respective LS SERDES lane

For example, if subsequent writes to LS_SERDES_CONTROL_2 and

LS_SERDES_CONTROL_3 registers need to affect the settings in Lanes 0 and 1,

LS_LN_CFG_EN[3:0] should be set to 4’b0011

Read values in LS_SERDES_CONTROL_2 & LS_SERDES_CONTROL_3 reflect

the settings value for Lane selected through LS_LN_CFG_EN[3:0].

To read settings for Lane 0, LS_LN_CFG_EN[3:0] should be set to 4’b0001

To read settings for Lane 1, LS_LN_CFG_EN[3:0] should be set to 4’b0010

To read settings for Lane 2, LS_LN_CFG_EN[3:0] should be set to 4’b0100

To read settings for Lane 3, LS_LN_CFG_EN[3:0] should be set to 4’b1000

Read values of LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3

registers are not valid for any other LS_LN_CFG_EN[3:0] combination

6.11:10 RESERVED

For TI use only(Default 2’b00)

RW

6.9:8

LS_LOOP_BANDWIDTH[1:0]

LS SERDES PLL Loop Bandwidth settings

00 = Reserved

01 = Applicable when external JC_PLL is NOT used (Default 2’b01)

10 = Applicable when external JC_PLL is used

11 = Reserved

6.7

DEEP_REMOTE_LPBK_CTRL Deep remote loopback control. Works in conjunction with

RW

DEEP_REMOTE_LPBK(B:3). Requires setting of LS_TX_ENTEST(8.3) and

LS_RX_ENTEST(8.2) for desired lane on the LS side (default 1'b0).

00= Deep Remote Loopback Disabled

01= Deep Remote Loopback through pad. The loopback path includes the

transmit CML driver and receive sense amps. The link partner connected

through INA*P/N or INB*P/N pins must be electrically idle at differential

zero with P and N signals at the same voltage.

10= Deep Remote Loopback with CML Driver Disabled. The loopback path is

fully digital and excludes the transmit CML driver and receive sense amps.

If monitoring OUT* pins is not required, this mode can save power.

11= Deep Remote Loopback with CML Driver Enabled. As above, but the CML

driver operates normally.

6.6:5

6.4

RESERVED

LS_ENPLL

For TI use only (Default 2’b00)

RW

LS SERDES PLL enable control. LS SERDES PLL is automatically disabled when

PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH.

0 = Disables PLL in LS SERDES

1 = Enables PLL in LS SERDES (Default 1’b1)

6.3:0

LS_MPY[3:0]

LS SERDES PLL multiplier setting (Default 4’b0101). Refer to Table 16

RW

See Line Rate, SERDES PLL Settings, and Reference Clock Selection section

for more information on PLL multiplier settings

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Table 16. Low Speed Side SERDES PLL Multiplier Control

6.3:0

VALUE

0000

0001

0010

0011

0100

0101

0110

0111

PLL MULTIPLIER FACTOR

VALUE

1000

1001

1010

1011

1100

1101

1110

1111

PLL MULTIPLIER FACTOR

4x

5x

15x

20x

6x

25x

Reserved

8x

Reserved

50x

10x

12x

65x

12.5x

Reserved

LS_ SERDES_CONTROL_2 — Address: 0x07 Default: 0xDC04

BIT(s)

7.15

NAME

DESCRIPTION

ACCESS

RW

RESERVED

LS_SWING[2:0]

For TI use only. (Default 1’b1)

7.14:12

Output swing control on LS SERDES side. (Default 3’b101)

RW

Refer to Table 17.

7.11

7.10

LS_LOS

LS SERDES LOS detector control

RW

0 = Disable Loss of signal detection on LS SERDES lane inputs

1 = Enable Loss of signal detection on LS SERDES lane inputs (Default 1’b1)

LS_IN_EN

LS SERDES input enable control. LS SERDES per input lane is automatically disabled when

PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. Input lanes 3 and 2 are

automatically disabled when in 2 to 1 mode

0 = Disables LS SERDES lane

1 = Enables LS SERDES lane (Default 1’b1)

7.9:8

LS_IN_RATE [1:0]

LS SERDES input lane rate settings

RW

00 = Full rate (Default 2’b00)

01 = Half rate

10 = Quarter rate

11 = Reserved

7.7:4

7.3

LS_DE[3:0]

RESERVED

LS_OUT_EN

LS SERDES output de-emphasis settings. (Default 4’b0000) Refer to Table 18

For TI use only . (Default 1’b0)

RW

7.2

LS SERDES output lane enable control. LS SERDES per output lane is automatically

disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. Output

lanes 3 and 2 are automatically disabled when in 1 to 2 mode.

0 = Disables LS SERDES lane

1 = Enables LS SERDES lane (Default 1’b1)

7.1:0

LS_OUT_RATE [1:0] LS SERDES output lane rate settings

RW

00 = Full rate (Default 2’b00)

01 = Half rate

10 = Quarter rate

11 = Reserved

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SLLSE75 –MAY 2011

Table 17. Low Speed Side SERDES AC Mode Output

Swing Control

AC MODE

VALUE

7.14:12

TYPICAL AMPLITUDE (mVdfpp)

000

001

010

011

100

101

110

111

190

380

560

710

850

950

1010

1050

Table 18. Low Speed Side SERDES Output De-emphasis

7.7:4

AMPLITUDE REDUCTION

VALUE

(%)

0

dB

0

(%)

dB

4.16

4.86

5.61

6.44

7.35

8.38

9.54

10.87

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

38.08

42.85

47.61

52.38

57.14

61.9

4.76

9.52

14.28

19.04

23.8

28.56

33.32

0.42

0.87

1.34

1.83

2.36

2.92

3.52

66.66

71.42

41

TLK10002

SLLSE75 –MAY 2011

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LS_ SERDES_CONTROL — Address: 0x08 Default: 0x0001

BIT(s)

NAME

DESCRIPTION

ACCESS

8.15

LS_OUT_INVPAIR

LS SERDES output lane polarity. (x = Channel A or B, y = Lane 0 or 1 or 2 or 3)

RW

0 = Normal polarity. OUTxyP considered positive data. OUTxyN considered negative

data (Default 1’b0)

1 = Inverted polarity. OUTxyP considered negative data. OUTxyN considered positive

data

8.14

LS_IN_INVPAIR

LS SERDES input lane polarity. (x = Channel A or B, y = Lane 0 or 1 or 2 or 3)

RW

0 = Normal polarity. INxyP considered positive data and INxyN considered negative

data (Default 1’b0)

1 = Inverted polarity. INxyP considered negative data and INxyP considered positive

data

8.13:12 RESERVED

For TI use only (Default 2’b00)

RW

8.11:8

8.7

LS_EQ[3:0]

RESERVED

LS_CDR[2:0]

LS SERDES Equalization control (Default 4’b0000). Refer to Table 19.

For TI use only (Default 1’b0)

8.6:4

LS SERDES CDR control (Default 3’b000)

000 – 1st Order. Threshold of 1

001 – 1st Order. Threshold of 17

010 – 2nd Order. High precision. Threshold of 1

011 – 2nd Order. High precision. Threshold of 17

100 – 1st Order. Low precision. Threshold of 1

101 – 2nd Order. Low precision. Threshold of 17

11x – Reserved

8.3

LS_TX_ENTEST

LS_RX_ENTEST

RESERVED

LS SERDES test mode control on the channel input

RW

0 = Normal operation (Default 1’b0)

1 = Enable test mode

8.2

LS SERDES test mode control on the channel output

0 = Normal operation (Default 1’b0)

1 = Enable test mode

8.1:0

For TI use only (Default 2’b01)

Table 19. Low Speed Side SERDES Equalization

8.11:8

Low Freq Gain

Maximum

8.11:8

Value

Zero Freq

Value

1000

1001

1010

1011

1100

1101

1110

1111

Low Freq Gain

Zero Freq

0000

0001

0010

0011

0100

0101

0110

0111

365 MHz

275 MHz

195 MHz

140 MHz

105 MHz

75 MHz

Adaptive

Reserved

55 MHz

50 MHz

42

TLK10002

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HS_OVERLAY_CONTROL — Address: 0x09 Default: 0x0900

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

9.15:10 RESERVED

For TI use only. (Default 6’b000010)

HS Serdes PEAK_DISABLE control

9.9

9.8

HS_PEAK_DISABLE

RW

0 = Track-and-hold has peaking for bandwidth extension

1 = Track-and-hold is without peaking; has flat AC response

HS_LOS_MASK

0 = HS SERDES LOS status is used to generate HS channel synchronization

status. If HS SERDES indicates LOS, channel synchronization indicates

synchronization is not achieved

RW

1 = HS SERDES LOS status is not used to generate HS channel

synchronization status (Default 1’b1)

9.5

9.4

HS_CH_SYNC_OVERLAY

0 = LOSx pin does not reflect receive channel loss of channel synchronization

RW

status (Default 1’b0)

1 = Allows channel loss of synchronization to be reflected on LOSx pin

HS_INVALID_CODE_OVERLAY

0 = LOSx pin does not reflect receive channel invalid code word error (Default

1’b0)

1 = Allows invalid code word error to be reflected on LOSx pin

9.3

9.2

HS_AGCLOCK_OVERLAY

HS_AZDONE_OVERLAY

0 = LOSx pin does not reflect HS SERDES AGC unlock status (Default 1’b0)

1 = Allows HS SERDES AGC unlock status to be reflected on LOSx pin

RW

0 = LOSx pin does not reflect HS SERDES auto zero calibration not done

status (Default 1’b0)

1 = Allows auto zero calibration not done status to be reflected on LOSx pin

9.1

9.0

HS_PLL_LOCK_OVERLAY

HS_LOS_OVERLAY

0 = LOSx pin does not reflect loss of HS SERDES PLL lock status (Default

RW

1’b0)

1 = Allows HS SERDES loss of PLL lock status to be reflected on LOSx pin

0 = LOSx pin does not reflect HS SERDES Loss of signal condition (Default

1’b0)

1 = Allows HS SERDES Loss of signal condition to be reflected on LOSx pin

43

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SLLSE75 –MAY 2011

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LS_OVERLAY_CONTROL — Address: 0x0A Default: 0x4000

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

A.15:14 RESERVED

For TI use only

A.13

A.12

BER_TIMER_CLK_EN

LS_PLL_LOCK_OVERLAY

0 = Disable BER timer clock (Default 1’b0)

1 = Enable BER timer clock

RW

0 = LOSx pin does not reflect loss of LS SERDES PLL lock status

RW

(Default 1’b0)

1 = Allows LS SERDES loss of PLL lock status to be reflected on

LOSx pin

A.11:8 LS_CH_SYNC_OVERLAY_LN[3:0]

[3] Corresponds to Lane 3, [2] Corresponds to Lane 2

[1] Corresponds to Lane 1, [0] Corresponds to Lane 0

0 = LOSx pin does not reflect LS SERDES lane loss of

synchronization condition (Default 1’b0)

1 = Allows LS SERDES lane loss of synchronization condition to be

reflected on LOSx pin

A.7:4

A.3:0

LS_INVALID_CODE_OVERLAY_LN[3:0] [3] Corresponds to Lane 3, [2] Corresponds to Lane 2

[1] Corresponds to Lane 1, [0] Corresponds to Lane 0

RW

0 = LOSx pin does not reflect LS SERDES lane invalid code

condition (Default 1’b0)

1 = Allows LS SERDES lane invalid code condition to be reflected on

LOSx pin

LS_LOS_OVERLAY_LN[3:0

[3] Corresponds to Lane 3, [2] Corresponds to Lane 2

[1] Corresponds to Lane 1, [0] Corresponds to Lane 0

0 = LOSx pin does not reflect LS SERDES lane Loss of signal

condition (Default 1’b0)

1 = Allows LS SERDES lane Loss of signal condition to be reflected

on LOSx pin

44

TLK10002

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LOOPBACK_TP_CONTROL — Address: 0x0B Default: 0x0700

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

B.15:14 RESERVED

For TI use only

B.13

B.12

HS_TP_GEN_EN

HS_TP_VERIFY_EN

0 = Normal operation (Default 1’b0)

1 = Activates test pattern generation selected by bits B.10:8

RW

0 = Normal operation (Default 1’b0)

RW

1 = Activates test pattern verification selected by bits B.10:8

B.10:8 HS_TEST_PATT_SEL[2:0]

Test Pattern Selection. Note that for CRPAT, TPsync must be high to be valid. See

MDIO bit F.15.

RW

000 = High Frequency Test Pattern

001 = Low Frequency Test Pattern

010 = Mixed Frequency Test Pattern

011 = CRPAT Short

100 = CRPAT Long

101 = 2⁷- 1 PRBS pattern

110 = 2²³- 1 PRBS pattern

111 = 2³¹- 1 PRBS pattern (Default 3’b111)

Errors can be checked by reading HS_ERROR_COUNTER register (0x10)

B.7

LS_TP_GEN_EN

0 = Normal operation (Default 1’b0)

RW

1 = Activates test pattern generation selected by bits B.5:4 on the LS side

Requires setting of LS_RX_ENTEST (8.2) for desired lane on the LS side

B.6

LS_TP_VERIFY_EN

0 = Normal operation (Default 1’b0)

1 = Activates test pattern verification selected by bits B.5:4 on the LS side

Requires setting of LS_TX_ENTEST (8.3) for desired lane on the LS side

RW

B.5:4

LS_TEST_PATT_SEL[1:0]

Test Pattern Selection

00 = 2³¹- 1 PRBS pattern (Default 2’b00)

01 = Alternating 0/1 pattern with a period of 2 UI (LS side bit UI)

10 = 2⁷- 1 PRBS pattern

11 = 2²³- 1 PRBS pattern

B.3

DEEP_REMOTE_LPBK

0 = Normal functional mode (Default 1’b0)

RW

1 = Enable deep remote loopback mode

Requires setting of LS_TX_ENTEST(8.3) and LS_RX_ENTEST (8.2) for desired lane

on the LS side.See Figure 12 and MDIO bit 6.7 for additional controls.

B.2

B.1

B.0

SHALLOW_REMOTE_LPBK

DEEP_LOCAL_LPBK

0 = Normal functional mode (Default 1’b0)

1 = Enable shallow remote loopback mode/serial retime mode

RW

See Figure 13

0 = Normal functional mode (Default 1’b0)

1 = Enable deep remote loopback mode

See Figure 14

SHALLOW_LOCAL_LPBK

0 = Normal functional mode (Default 1’b0)

1 = Enable shallow remote loopback mode

See Figure 15

45

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LAS_CONFIG_CONTROL — Address: 0x0C Default: 0x03F0

BIT(s)

NAME

DESCRIPTION

ACCESS

RW

C.15:14 RESERVED

For TI use only. (Default 2’b0)

C.13:12 LAS_STATUS_CFG[1:0]

Selects selected lane status to be reflected in LAS_STATUS_1 register (0x15)

RW

00 = Lane 0 (Default 2’b00)

01 = Lane 1

10 = Lane 2

11 = Lane 3

C.11:10 LAS_CH_SYNC_HYS_SEL[1:0]

Lane alignment slave Channel synchronization hysteresis selection

RW

00 = The channel synchronization, when in the synchronization state, performs

the Ethernet standard specified hysteresis to return to the LOS state

(Default 2’b00)

01 = A single 8b/10b invalid decode error or disparity error causes the channel

synchronization state machine to immediately transition from sync to LOS

10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the

channel synchronization state machine to immediately transition from sync

to LOS

11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the

channel synchronization state machine to immediately transition from sync

to LOS

C.9:8

C.7

LAS_LA_COL_CFG[1:0]

Minimum distance between align character in Lane alignment slave

RW

00 =

8

01 = 16

1x = 24 (Default 2’b11)

LS_DECODE_ERR_MASK

0 = LS side decode errors of enabled lanes are used to generate link status if

error rate exceeds threshold. Valid only when hardware BER function is

enabled by setting A.13 to 1'b1.

1 = LS side decode errors of any lane are not used to generate link status

(Default 1’b1)

C.6

C.5

RESERVED

For TI use only.

RW

LS_LOS_MASK

0 = LS SERDES LOS status of enabled lanes is used to generate link status

1 = LS SERDES LOS status of enabled lanes is not used to generate link

status (Default 1’b1)

C.4

LS_PLL_LOCK_MASK

0 = LS SERDES PLL Lock status is used to generate link status

RW

1 = LS SERDES PLL Lock status is not used to generate link status (Default

1’b1)

C.2

FORCE_LM_REALIGN

LAS_BER_THRESH[1:0]

0 = Normal operation (Default 1’b0)

RW

1 = Force lane realignment in Link status monitor

C.1:0

Threshold setting for 8b/10b error rate checking. Valid only when hardware BER

function is enabled by setting A.13 to 1'b1.

00 = Link Ok if <1 error when timer expires (Default 2’b00)

01 = Link Ok if <15 error when timer expires

10 = Link Ok if <127 error when timer expires

11 = Link Ok if <1023 error when timer expires

LAS_BER_TMER_CONTROL — Address: 0x0D Default: 0xFFFF

BIT(s)

NAME

DESCRIPTION

ACCESS

D.15:0 LAS_BER_TIMER[15:0]

16 bit value to configure 8b/10b error rate checking on the link monitor (Default

16’hFFFF). Valid only when hardware BER function is enabled by setting A.13 to

1'b1.

RW

46

TLK10002

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RESET_CONTROL — Address: 0x0E Default: 0x0000

BIT(s) NAME

DESCRIPTION

ACCESS

E.3

DATAPATH_RESET

Channel datapath reset control. Required once the desired functional mode is configured.

RW

SC⁽¹⁾

0 = Normal operation. (Default 1’b0)

1 = Resets channel logic excluding MDIO registers. (Resets both Tx and Rx datapath)

E.2

TXFIFO_RESET

RXFIFO_RESET

Transmit FIFO reset control

RW

SC⁽¹⁾

0 = Normal operation. (Default 1’b0)

1 = Resets transmit datapath FIFO.

Receive FIFO reset control

E.1

RW

SC⁽¹⁾

0 = Normal operation. (Default 1’b0)

1 = Resets receive datapath FIFO.

(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

CHANNEL_STATUS_1 — Address: 0x0F Default: 0x0000

BIT(s) NAME

DESCRIPTION

ACCESS

F.15

HS_TP_ STATUS

Test Pattern status for High/Low/Medium/CRPAT test patterns

0 = Alignment has not achieved

RO

1 = Alignment has been determined and correct pattern has been received. Any bit errors

are reflected in HS_ERROR_COUNTER register (0x10)

F.14

F.13

LA_SLAVE_STATUS

HS_LOS

Lane alignment slave status

0 = Lane alignment is not achieved on the slave side

1 = Lane alignment is achieved on the slave side

RO/LL

RO/LH

Loss of Signal Indicator.

When high, indicates that a loss of signal condition is detected on HS serial receive

inputs

F.12

F.11

F.10

HS_AZ_DONE

Auto zero complete indicator.

When high, indicates auto zero calibration is complete

RO/LL

HS_AGC_LOCKED

HS_CHANNEL_SYNC

Adaptive gain control loop lock indicator.

When high, indicates AGC loop is in locked state

Channel synchronization status indicator.

When high, indicates channel synchronization has achieved

F.9

F.8

RESERVED

For TI use only. (Default 1’b0).

RO/LH

HS_DECODE_INVALID

Valid when decoder is enabled and during CRPAT test pattern verification.

When high, indicates decoder received an invalid code word, or a 8b/10b disparity error.

In functional mode, number of DECODE_INVALID errors are reflected in

HS_ERROR_COUNTER register (0x10)

F.7

F.6

F.5

F.4

F.3

TX_FIFO_UNDERFLOW

TX_FIFO_OVERFLOW

RX_FIFO_UNDERFLOW

RX_FIFO_OVERFLOW

RX_LS_OK

When high, indicates underflow has occurred in the transmit datapath FIFO.

When high, indicates overflow has occurred in the transmit datapath FIFO.

When high, indicates underflow has occurred in the receive datapath FIFO.

When high, indicates overflow has occurred in the receive datapath FIFO.

RO/LH

RO/LL

Receive link status indicator from LS side.

When high, indicates receive link status is achieved on the LS side

F.2

F.1

TX_LS_OK

Link status indicator from Link training slave inside TLK10002

When high, indicates Link training slave has achieved sync and alignment

RO/LL

LS_PLL_LOCK

LS SERDES PLL lock indicator

When high, indicates LS SERDES PLL is locked to the selected incoming

REFCLK0/1_P/N

F.0

HS_PLL_LOCK

HS SERDES PLL lock indicator

RO/LL

When high, indicates HS SERDES PLL is locked to the selected incoming

REFCLK0/1_P/N

47

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HS_ERROR_COUNTER — Address: 0x10 Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

10.15:0 HS_ERR_COUNT [15:0]

In functional mode, this counter reflects number of invalid code words (including

disparity errors) received by decoder.

COR

In HS test pattern verification mode, this counter reflects error count for the test

pattern selected through B.10:8

When PRBSEN pin is set, this counter reflects error count for selected PRBS

pattern. Counter value cleared to 16’h0000 when read.

LS_LN0_ERROR_COUNTER — Address: 0x11 Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

11.15:0 LS_LN0_ERR_COUNT [15:0]

Lane 0 Error counter

COR

In functional mode, this counter reflects number of invalid code words (including

disparity errors) received by decoder in lane alignment slave.

In LS test pattern verification mode, this counter reflects error count for the test

pattern selected through B.5:4

Counter value cleared to 16’h0000 when read.

LS_LN1_ERROR_COUNTER — Address: 0x12 Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

12.15:0 LS_LN1_ERR_COUNT [15:0]

Lane 1 Error counter

COR

In functional mode, this counter reflects number of invalid code words (including

disparity errors) received by decoder in lane alignment slave.

In LS test pattern verification mode, this counter reflects error count for the test

pattern selected through B.5:4

Counter value cleared to 16’h0000 when read.

LS_LN2_ERROR_COUNTER — Address: 0x13 Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

13.15:0 LS_LN2_ERR_COUNT [15:0]

Lane 2 Error counter

COR

In functional mode, this counter reflects number of invalid code words (including

disparity errors) received by decoder in lane alignment slave.

In LS test pattern verification mode, this counter reflects error count for the test

pattern selected through B.5:4

Counter value cleared to 16’h0000 when read.

LS_LN3_ERROR_COUNTER — Address: 0x14 Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

14.15:0 LS_LN3_ERR_COUNT [15:0]

Lane 3 Error counter

COR

In functional mode, this counter reflects number of invalid code words (including

disparity errors) received by decoder in lane alignment slave.

In LS test pattern verification mode, this counter reflects error count for the test

pattern selected through B.5:4

Counter value cleared to 16’h0000 when read.

48

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LAS_STATUS_1 — Address: 0x15 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

15.15

LAS_LN_ALIGN_FIFO_ERR

LAS Lane alignment FIFO error status

0 = FIFO error not detected

1 = FIFO error detected

For TI use only

RO/LH

15.14:12 RESERVED

RO

15.11

LAM_ ALIGN_SEQ_ST

LAM Lane align sequence state

0 = Sending normal traffic

1 = Sending lane align sequence

15.10

LS_LOS

Loss of Signal Indicator.

RO/LH

When high, indicates that a loss of signal condition is detected on LS serial

receive inputs for selected lane. Lane can be selected through

LAS_STATUS_CFG[1:0] (register C.13:12)

15.9

15.8

RESERVED

For TI use only. (Default 1’b0).

RO/LL

LAS_CH_SYNC_STATUS

LAS Channel sync status for selected lane. Lane can be selected through

LAS_STATUS_CFG[1:0] (register C.13:12)

15.6:4

15.3

RESERVED

For TI use only. (Default 2’b000).

RO

LAS_INVALID_DECODE

LAS Invalid decode error for selected lane. Lane can be selected through

RO/LH

LAS_STATUS_CFG[1:0] (register C.13:12). Error count for each lane can also be

monitored through respective LS_LNx_ERROR_COUNTER registers (0x11,

0x12, 0x13, and 0x14)

15.2:0

RESERVED

For TI use only. (Default 2’b000).

RO

LATENCY_MEASURE_CONTROL — Address: 0x16 Default: 0x7F00

BIT(s)

16.15:8

16.7

NAME

DESCRIPTION

ACCESS

RW

RESERVED

For TI use only (Default 8'b11111111)

LATENCY_MEAS_START_SEL Latency measurement start point selection

0 = Selects LS TX as start point (Default 1’b0)

RW

1 = Selects HS RX as start point

16.6

LATENCY_MEAS_STOP_SEL

Latency measurement stop point selection

0 = Selects LS RX as stop point (Default 1’b0)

1 = Selects HS TX as stop point

RW

16.5:4

LATENCY_MEAS_CLK_DIV[1:0] Latency measurement clock divide control. Valid only when bit 16.2 is 0. Divides

clock to needed resolution. Higher the divide value, lesser the latency

measurement resolution

00 = Divide by 1 (Default 2’b00) (Most Accurate Measurement)

01 = Divide by 2

10 = Divide by 4

11 = Divide by 8 (Longest Measurement Capability)

See Table 9

16.2

LATENCY_MEAS_CLK_SEL

Latency measurement clock selection.

RW

0 = Selects clock listed in Table 9. Bits 16.5:4 can be used to divide this

clock to achieve needed resolution. (Default 1’b0)

1 = Selects respective channel recovered byte clock (Frequency = Serial bit

rate/ 20).

16.1

16.0

LATENCY_MEAS_EN

Latency measurement enable

RW

0 = Disable Latency measurement (Default 1’b0)

1 = Enable Latency measurement

LATENCY_MEAS_CH_SEL

Latency measurement channel selection

0 = Selects Latency measurement for channel A (Default 1’b0)

1 = Selects Latency measurement for channel B

49

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LATENCY_COUNTER_2 — Address: 0x17 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

17.15:12

LATENCY_MEAS_START_COMMA[3:0] Latency measurement start comma location status. “1” indicates

comma found at the start location. If LS TX is selected as start point

(16.7 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS

RX is selected as start point (16.7 = 1), [0] indicates status for

RO/LH⁽¹⁾

data[9:0], [1] indicates status for data[19:10]. [3:2] is unused.

17.11:8

17.4

LATENCY_MEAS_STOP_COMMA[3:0]

Latency measurement stop comma location status. “1” indicates

comma found at the stop location. If LS RX is selected as stop point

(16.6 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS

TX is selected as stop point (16.6 = 1), [0] indicates status for

data[9:0], [1] indicates status for data[19:10]. [3:2] is unused.

RO/LH⁽¹⁾

LATENCY_ MEAS_READY

Latency measurement ready indicator

0 = Indicates latency measurement not complete.

1 = Indicates latency measurement is complete and value in latency

measurement counter (LATENCY_MEAS_COUNT[19:0]) (in registers

17.3:0 and 18.15:0) is ready to be read.

17.3:0

LATENCY_MEAS_COUNT[19:16]

Bits[19:16] of 20 bit wide latency measurement counter.

COR⁽¹⁾

Latency measurement counter value represents the latency in number

of clock cycles. This counter will return 20’h00000 if it is read before a

comma is received at the stop point. If latency is more than

20’hFFFFF clock cycles then this counter returns 20’hFFFFF.

(1) User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to

20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when

Register 0x18 is read.

LATENCY_COUNTER_1 — Address: 0x18 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

18.15:0

LATENCY_MEAS_COUNT[15:0]

Bits[15:0] of 20 bit wide latency measurement counter.

COR⁽¹⁾

(1) User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to

20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when

Register 0x18 is read.

TI_RESERVED_CONTROL_1 — Address: 0x19 Default: 0x0000

BIT(s)

19.10

19.9

NAME

DESCRIPTION

ACCESS

RW

RESERVED

For TI use only. (Default 1’b0)

For TI use only. (Default 2’b00)

For TI use only. (Default 4’b0000)

RW

19.8

RW

19.6

RW

19.5:4

19.3:0

RW

TI_RESERVED_CONTROL_2 — Address: 0x1A Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

1A.15:0

RESERVED

For TI use only.

RW

TI_RESERVED_STATUS_1 — Address: 0x1B Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

1B.15:0

RESERVED

For TI use only.

RO

50

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MISC_CONTROL_3 — Address: 0x1C Default: 0x3000

BIT(s)

1C.15

1C.14

1C.13

NAME

DESCRIPTION

ACCESS

RW

RESERVED

CLKOUT_B_EN

For TI use only. (Default 1’b0)

RW

Output clock enable

RW

0 = Holds CLKOUTBP/N output to a fixed value

1 = Allows CLKOUTBP/N output to toggle normally (Default 1'b1)

Output clock enable

1C.12

CLKOUT_A_EN

RW

0 = Holds CLKOUTAP/N output to a fixed value

1 = Allows CLKOUTAP/N output to toggle normally (Default 1'b1)

For TI use only. (Default 10’b0000000000)

1C.9:0

RESERVED

LAS_STATUS_2 — Address: 0x1D Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

RO

1D.15:12

1D.11:8

1D.7:4

LAS_LN3_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 3.

LAS_LN2_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 2.

LAS_LN1_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 1.

LAS_LN0_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 0.

RO

1D.3:0

RO

EXT_ADDRESS_CONTROL — Address: 0x1E Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

1E.15:0

EXT_ADDR_CONTROL[15:0] This register should be written with the extended register address to be

RW

written/read. Contents of address written in this register can be accessed from

Register 0x1F. (Default 4’h0000)

EXT_ADDRESS_DATA — Address: 0x1F Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

1F.15:0

EXT_ADDR_DATA[15:0]

This register contains the data associated with the register address written in

Register 0x1E

RO

TI_ RESERVED_STATUS_2 — Address: 0x8000 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8000.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_3 — Address: 0x8001 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8001.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_4 — Address: 0x8002 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8002.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_5 — Address: 0x8003 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8003.15:0 RESERVED

For TI use only.

RO

51

TLK10002

SLLSE75 –MAY 2011

www.ti.com

TI_RESERVED_STATUS_6 — Address: 0x8004 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8004.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_7 — Address: 0x8005 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8005.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_8 — Address: 0x8006 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8006.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_9 — Address: 0x8007 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8007.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_10 — Address: 0x8008 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8008.15:0 RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_11 — Address: 0x8009 Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

8009.15:0

RESERVED

For TI use only.

RO

TI_RESERVED_STATUS_12 — Address: 0x800A Default: 0x0000

BIT(s)

NAME

DESCRIPTION

ACCESS

800A.15:0 RESERVED

For TI use only.

RO

52

TLK10002

www.ti.com

SLLSE75 –MAY 2011

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

MAX

UNIT

MIN

–0.3

–65

1

Supply voltage

DVDD, VDDA_LS/HS, VDDT_LS/HS, VPP, VDDD

VDDRA_LS/HS, VDDRB_LS/HS, VDDO[1:0]

V_I, (LVCMOS/LVDS/LVPECL/CML/Analog)

1.4

2.2

V

Supply voltage

Input voltage

Supply + 0.3 V

150

V

Storage temperature

Electrostatic discharge

°C

KV

V

HBM

CDM

500

–40

Characterized free-air operating temperature range

85

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION - JEDEC High-K PCB

TLK10002

THERMAL METRIC⁽¹⁾

PBGA

144 PINS

25.5

UNITS

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

2.8

18

°C/W

ψ_JT

ψ_JB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.8

13.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

THERMAL INFORMATION - EVM Board (5in. x 7in., 14 layer, 1-oz. copper)

TLK10002

THERMAL METRIC⁽¹⁾

PBGA

144 PINS

24.5

2.8

UNITS

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

12

°C/W

ψ_JT

ψ_JB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.9

11

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

53

TLK10002

SLLSE75 –MAY 2011

www.ti.com

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

Digital / Analog supply voltages VDDD, VDDA_LS/HS, DVDD, VDDT_LS/HS, VPP

0.95 1.00

1.05

1.575

1.89

1.575

1.89

375

460

220

540

50

V

1.5V Nominal

1.425

1.71

1.5

1.8

1.5

1.8

VDDRA_LS/HS

VDDRB_LS/HS

SERDES PLL regulator voltage

LVCMOS I/O supply voltage

1.8V Nominal

1.5V Nominal

1.8V Nominal

1.425

1.71

VDDO[1:0]

VDDD

VDDA_LS/HS

DVDD + VPP

VDDT_LS/HS

VDDRA_LS

I_DDSupply current

10Gbps

mA

VDDRA_HS

20

VDDRB_LS

50

VDDRB_HS

20

VDDO[1:0] (1.5V /1.8V Mode)

6/8

P_DAll supplies worst case

I_SDShutdown Current

1.75⁽¹⁾

W

VDDD

80

VDDA

25

DVDD + VPP

VDDT

15

PD* Asserted

mA

45

VDDRA_HS/LS + VDDRB_HS/LS

(1.5V Mode /1.8V Mode)

0.5/0.5

5/5

VDDO (1.5V Mode /1.8V Mode)

(1) Total worst case power is not a sum of the individual power supply worst case as the individual power is taken from multiple modes.

These modes are mutually exclusive and therefore used only for power supply requirements.

54

TLK10002

www.ti.com

SLLSE75 –MAY 2011

10Gbps POWER CHARACTERISTICS

at V_max, 1.0 V Core, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

2 Ch Mode, 4:1 at 10Gpbs

MIN TYP

0.95 1.0

MAX UNIT

Power supply

voltage

VDDA_LS/HS,

1.05

V

A

VDDT_LS/HS, VDDD,

DVDD, VPP

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

Power supply

current

VDDA_LS/HS

VDDT_LS/HS

DVDD+VPP

VDDD

0.407

0.411

0.222

0.22

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0.229

0.228

0.489

0.347

0.268

0.197

0.273

0.199

0.1743

0.1887

0.1375

0.1407

0.1356

0.1414

0.3151

0.333

0.21

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

0.2136

0.209

0.2165

55

TLK10002

SLLSE75 –MAY 2011

www.ti.com

10Gbps POWER CHARACTERISTICS

at V_max, 1.5 V I/O, over operating free-air temperature range (unless otherwise noted)

PARAMETER

VDDRA_LS/HS,

VDDRB_LS/HS, VDDO

TEST CONDITIONS

2 Ch Mode, 4:1 at 10Gpbs

MIN TYP

1.425 1.5

MAX UNIT

Power supply

voltage

1.575

V

A

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

Power supply

current

VDDRA_LS

0.0191

0.0371

0.019

0.0371

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

VDDRA_HS

VDDRB_LS

VDDRB_HS

VDDO[1:0]

0.0152

0.0153

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0192

0.0374

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0192

0.0374

0.0155

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0156

0.0037

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

56

TLK10002

www.ti.com

SLLSE75 –MAY 2011

10Gbps POWER CHARACTERISTICS

at V_max, 1.8 V I/O, over operating free-air temperature range (unless otherwise noted)

PARAMETER

VDDRA_LS/HS,

VDDRB_LS/HS, VDDO

TEST CONDITIONS

2 Ch Mode, 4:1 at 10Gpbs

MIN TYP

1.71 1.8

MAX UNIT

Power supply

voltage

1.89

V

A

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

Power supply

current

VDDRA_LS

0.0191

0.0372

0.0191

0.0372

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

VDDRA_HS

VDDRB_LS

VDDRB_HS

VDDO[1:0]

0.0151

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0194

0.0376

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0193

0.0376

0.0154

0

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

2 Ch Mode, 4:1 at 10Gpbs

0

0.0155

0.0047

0.0046

0.0047

0.0046

0.0047

2 Ch Mode, 2:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 4:1 at 10Gpbs

1 Ch Mode, Ch A on, Ch B off, 2:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 4:1 at 10Gpbs

1 Ch Mode, Ch A off, Ch B on, 2:1 at 10Gpbs

57

TLK10002

SLLSE75 –MAY 2011

www.ti.com

HIGH SPEED SIDE SERIAL TRANSMITTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

50

TYP

130

MAX UNIT

220

SWING (3.15:12) = 0000

SWING (3.15:12) = 0001

SWING (3.15:12) = 0010

SWING (3.15:12) = 0011

SWING (3.15:12) = 0100

SWING (3.15:12) = 0101

SWING (3.15:12) = 0110

SWING (3.15:12) = 0111

SWING (3.15:12) = 1000

SWING (3.15:12) = 1001

SWING (3.15:12) = 1010

SWING (3.15:12) = 1011

SWING (3.15:12) = 1100

SWING (3.15:12) = 1101

SWING (3.15:12) = 1110

SWING (3.15:12) = 1111

110

180

250

320

390

460

530

590

660

740

820

890

970

1060

1090

220

320

300

430

390

540

480

650

570

770

660

880

750

1000

mV_pp

1100

TX Output differential

peak-to-peak voltage swing

V_OD(pp)

830

930

1220

1320

1430

1520

1610

1680

1740

1020

1110

1180

1270

1340

1400

TX Output common mode

voltage

V_DDT

-

V_CMT

t_skew

t_r, t_f

100-Ω differential termination, DC-coupled

mV

(0.25*V_OD(pp)

)

Intra-pair output skew

SWING(3.15:12) = 0110

0.09

UI

ps

Differential output signal rise,

Fall time (20% to 80%)

20

Differential load = 100Ω

Serial Rate ≤ 3.072 Gbps

(Not Applicable to LV-II)

0.35

0.30

0.17

0.15

0.279

0.14

Serial output total jitter (CPRI

LV/LV-II and OBSAI Rates)

J_T1

UI

Serial Rate > 3.072 Gbps

(And All LV-II Rates)

Serial Rate ≤ 3.072 Gbps

(Not Applicable to LV-II)

Serial output deterministic

jitter (CPRI LV/LV-II and

OBSAI Rates)

J_D1

Serial Rate > 3.072 Gbps

(And All LV-II Rates)

Serial output total jitter (CPRI

E.6/12.HV)

J_T2

J_D2

CPRI E.6/12.HV (0.6144 and 1.2288 Gbps)

Serial output deterministic

jitter (CPRI E.6/12.HV)

100MHz < f < 1.0 GHz

1.0GHz < f < 5.0 GHz

See Figure 17

7

5

Common-mode output return

loss

S_cc22

dB

UI

T_(LATENCY)Transmit path latency

0.5 * V_DE

V_OD(pp)

*

0.5 *

V_OD(pp)

V_CMT

0.25 * V_DE* V_OD(pp)

0.25 * V_OD(pp)

t_r, t_f

bit

time

Figure 26. Transmit Output Waveform Parameter Definitions

58

TLK10002

www.ti.com

SLLSE75 –MAY 2011

+V_0/0

+V_pst

+V_pre

+V_ss

0

-V_ss

-V_pre

-V_pst

-V_0/0

UI

h_-1= TWPRE (0% > -17.5% for typical application) setting

h₁= TWPOST1 (0%

h₀= 1 - |h₁| - |h_-1|

-37.5% for typical application) setting

>

V_0/0= Output Amplitude with TWPRE = 0%, TWPOST = 0%.

V_ss= Steady State Output Voltage = V_0/0* | h₁+ h₀+ h_-1|

V_pre= PreCursor Output Voltage = V_0/0* | -h₁– h₀+ h_-1|

V_pst= PostCursor Output Voltage = V_0/0* | -h₁+ h₀+ h_-1|

Figure 27. Pre/Post Cursor Swing Definitions

HIGH SPEED SIDE SERIAL RECEIVER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

50

TYP

MAX UNIT

Full Rate AC Coupled

600

mV

800

V_ID

RX Input differential voltage |RXP – RXN|

Half/Quarter/Eighth Rate AC Coupled

Full Rate AC Coupled

50

100

1200

mV_pp

1600

RX Input differential peak-to-peak voltage swing

2 * |RXP – RXN|

V_ID(pp)

C_I

Half/Quarter/Eighth Rate AC Coupled

RX Input capacitance

2

0.66

0.65

0.50

0.35

pF

Zero crossing Half/Quarter/Eighth Rate

Zero crossing Full Rate

Jitter tolerance, total jitter at serial input (DJ +

J_TOL

UI_pp

RJ) (BER 10^-15

)

Zero crossing Half/Quarter/Eighth Rate

Zero crossing Full Rate

J_DR

Serial input deterministic jitter (BER 10^-15

)

UI_pp

100 MHz < f < 0.75*[Serial Bit Rate]

8

dB

SDD11

t_skew

Differential input return loss

Intra-pair input skew

0.75 × [Serial Bit Rate] < f < [Serial Bit

Rate]

(1)

See

0.23

UI

t_(LATENCY)Receive path latency

See Figure 17

(1) Differential input return loss, SDD11 = 8 – 16.6 log10(f / (0.75 × [Serial Bit Rate])) dB

59

TLK10002

SLLSE75 –MAY 2011

www.ti.com

High Speed Side Receiver Jitter Tolerance

The peak to peak total jitter tolerance for the RP3 receiver is 0.65 UI. This total jitter is composed of three

components; deterministic jitter, random jitter, and an additional sinusoidal jitter.

The deterministic jitter tolerance is 0.37 UI minimum. The sum of deterministic and random jitter is 0.55 UI

minimum. The additional sinusoidal jitter which the receiver must tolerate will have frequencies and amplitudes

conforming to the mask presented in the Figure 28 and Table 20.

UI 2pp

Sinusoidal

Jitter

Amplitude

(UI)

UI1pp

f1

f2

20 MHz

Frequency

Figure 28. OBSAI Sinusoidal Jitter Mask

Table 20. Sinusoidal Jitter Mask Values.

Frequency

(MBaud)

f1

(kHz)

f2

(kHz)

UI1pp

UI2pp

768

1536

3072

6144

9830.4

5.4

10.9

21.8

36.9

59

460.8

921.6

1843.2

3686

0.1

8.5

5

0.1

0.05

5897.6

5

J_DR

J_R

J_TOL

NOTE: J_TOL= J_R+ J_DR, where J_TOLis the receive jitter tolerance, J_DRis the received deterministic jitter, and J_Ris the

Gaussian random edge jitter distribution at a maximum BER = 10^-12for CPRI link and BER = 10^-15for OBSAI (RP3)

link.

Figure 29. Input Jitter Definition

60

TLK10002

www.ti.com

SLLSE75 –MAY 2011

LOW SPEED SIDE SERIAL TRANSMITTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

110

280

420

560

690

760

800

830

TYP

MAX UNIT

280

SWING (7:14:12) = 000

190

380

SWING (7:14:12) = 001

SWING (7:14:12) = 010

SWING (7:14:12) = 011

SWING (7:14:12) = 100

SWING (7:14:12) = 101

SWING (7:14:12) = 110

SWING (7:14:12)= 111

490

560

700

710

870

mV_pp

1020

Transmitter output differential

peak-to-peak voltage swing

V_OD(pp)

850

950

1150

1230

1270

1010

1050

Transmitter output common mode

voltage

V_DDT

(0.5*V_OD(pp)

-

)

V_CMT

t_skew

100-Ω differential termination, DC-coupled

mV

Intra-pair output skew

0.045

-

UI

ps

Differential output signal rise, fall

time (20% to 80%) Differential Load

= 100Ω

t_R, t_F

30

-

J_T

J_D

Serial output total jitter

0.35

0.17

UI

Serial output deterministic jitter

LOW SPEED SIDE SERIAL RECEIVER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

Full Rate AC Coupled

50

600

800

V_ID

Receiver input differential voltage| INP – INN|

mV

Half/Quarter Rate AC Coupled

Full Rate AC Coupled

Receiver input differential peak-to-peak voltage

100

1200

swing

2 × |INP – INN|

V_ID(pp)

mV_dfpp

Half/Quarter Rate AC Coupled

100

1600

C_I

Receiver input capacitance

2

0.66

0.65

0.50

0.35

8

pF

Zero crossing Half/Quarter Rate

Zero crossing Full Rate

Jitter tolerance, total jitter at serial input

J_TOL

UI_pp

(DJ + RJ)(BER 10^-15

)

Zero crossing Half/Quarter Rate

Zero crossing Full Rate

J_DR

Serial input deterministic jitter(BER 10^-15

)

UI_pp

S_dd11

t_skew

Differential input return loss

Intra-pair input skew

625 MHz < f < 2.5 GHz

dB

UI

0.23

30

t_lane-skewLane-to-lane input skew

REFERENCE CLOCK CHARACTERISTICS (REFCLK0P/N, REFCLK1P/N)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

F

Frequency

122.88

425

100

200

0

MHz

Relative to Nominal HS Serial Data Rate

Relative to Incoming HS Serial Data Rate

Synchronous (Multiple/Divide)

High Time

–100

–200

0

FHS_offsetAccuracy

ppm

FLS_offsetAccuracy to LS serial data

0

DC

V_ID

C_IN

R_IN

T_RISE

J_R

Duty cycle

45% 50% 55%

Differential input voltage

Input capacitance

Differential input impedance

Rise/fall time

250

2000

1

mVpp

pF

80

50

100

120

350

4

Ω

10% to 90%

ps

Random jitter

12 kHz to 20 MHz

ps-RMS

61

TLK10002

SLLSE75 –MAY 2011

www.ti.com

DIFFERENTIAL OUTPUT CLOCK CHARACTERISTICS (CLKOUTAP/N, CLKOUTBP/N)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Differential Output Voltage

Output Rise Time

TEST CONDITIONS

MIN TYP MAX UNIT

V_OD

T_RISE

R_TERM

F

Peak to peak

1000

2000 mV_pp

10% to 90%, 2pF lumped capacitive load, AC-Coupled

CLKOUTA/BP/N to DVDD

350

60

ps

Output Termination

Output Frequency

40

0

50

Ω

500 MHz

62

TLK10002

www.ti.com

SLLSE75 –MAY 2011

LVCMOS ELECTRICAL CHARACTERISTICS (VDDO)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDDO –

I_OH= 2 mA, Driver Enabled (1.8 V)

VDDO

V

0.45

V_OH

High-level output voltage

0.75 ×

VDDO

I_OH= 2 mA, Driver Enabled (1.5 V)

I_OL= –2 mA, Driver Enabled (1.8 V)

I_OL= –2 mA, Driver Enabled (1.5 V)

VDDO

0

0.45

V_OL

Low-level output voltage

High-level input voltage

V

0.25 ×

0

VDDO

0.65 ×

VDDO

V_IH

VDDO + 0.3

V

0.35 ×

VDDO

V_IL

Low-level input voltage

Low/high input current

–0.3

I_IH, I_IL

Receiver only

±170

±25

±195

3

µA

pF

Driver disabled

I_OZ

High-impedance output current

Input capacitance

Driver disabled with pull up/down enabled

C_IN

MDIO TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted)

PARAMETER

MDC period

TEST CONDITIONS

MIN

100

10

TYP

MAX UNIT

t_period

t_setup

t_hold

See Figure 30

ns

MDIO setup to ↑ MDC

MDIO hold to ↑ MDC

MDIO valid from MDC ↑

10

t_valid

0

40

ns

MDC

t

PERIOD

t

SETUP

HOLD

MDIO

Figure 30. MDIO Read/Write Timing

63

TLK10002

SLLSE75 –MAY 2011

www.ti.com

JTAG TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

See Figure 31

MIN

TYP MAX UNIT

t_PERIOD

t_SETUP

t_HOLD

TCK period

66.67

ns

TDI/TMS/TRST_N setup to ↑ TCK

TDI/TMS/TRST_N hold from ↑ TCK

TDO delay from TCK falling

See Figure 31

3

5

0

t_VALID

10

ns

TCK

t

PERIOD

t

HOLD

SETUP

TDI/TMS/

TRST_N

t

VALID

TDO

Figure 31. JTAG Timing

64

TLK10002

www.ti.com

SLLSE75 –MAY 2011

POWER SEQUENCING GUIDELINES

The TLK10002 allows either the core or I/O power supply to be powered up for an indefinite period of time while

the other supply is not powered up, if all of the following conditions are met:

1. All maximum ratings and recommended operating conditions are followed.

2. Bus contention while 1.5V/1.8V power is applied (>0V) must be limited to 100 hours over the projected

lifetime of the device.

3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute

maximum voltage values for up to 100 hours of lifetime operation at a junction temperature of 105°C or lower

will minimally impact reliability.

The TLK10002 inputs are not failsafe (i.e., cannot be driven with the I/O power disabled). TLK10002 inputs

should not be driven high until their associated power supplies are active.

DEVICE INITIALIZATION

The following sequence should be performed to initialize and ensure proper operation of the TLK10002 device.

This procedure is optimized for electrical connection on HS serial side.

4:1 Mode (9.8304Gbps on HS side, 2.4576Gbps per lane on LS side)

Note: Assume both channel A and channel B have the same setup.

REFCLK frequency = 122.88MHz, Mode = Transceiver, 4 to 1 serialization on LS side inputs and 1 to 4

deserialization on HS side inputs.

•

Device Pin Setting(s) – Pin settings allow for maximum software configurability.

–

Ensure PD_TRXA_N input pin is High.

Ensure PD_TRXB_N input pin is High.

Ensure PRBSEN input pin is Low.

Ensure REFCLKA_SEL input pin is Low to enable software control.

Ensure REFCLKB_SEL input pin is Low to enable software control.

•

Reset Device

–

Issue a hard or soft reset (RESET_N asserted for at least 10 µs -or- Write 1’b1 to 0.15 GLOBAL_RESET)

after power supply stabilization.

•

Enable MDIO global write so that each MDIO write affects both channels to shorten provisioning time

Write 1’b1 to 0.11 GLOBAL_WRITE

Clock Configuration and Mode control

–

Write 1’b1 to 1.9 RX_DEMUX_SEL to select 1 to 4 on the receive side

Write 1’b1 to 1.8 TX_MUX_SEL to select 4 to 1 on the transmit side

Select respective Channel SERDES REFCLK input (Default = REFCLK0P/N)

–

If REFCLK0P/N used – Write 1’b0 to 1.1 REFCLK_ SEL

If REFCLK1P/N used – Write 1’b1 to 1.1 REFCLK_ SEL

•

HS/LS Data Rate Setting (Refer to Table 4 for more CPRI/OBSAI Rates)

–

Write 4’b1101 to 2.3:0 HS_PLL_MULT[3:0], write 2’b00 to 3.9:8 HS_RATE_RX[1:0], write 2’b00 to 3.1:0

HS_RATE_TX[1:0], to select FULL rate and 20x MPY on HS side (HS_SERDES_CONTROL_1 = 0x811D,

HS_SERDES_CONTROL_2 = 0xA444).

–

Write 1'B1 to 9.9 HS_PEAK_DISABLE (HS_OVERLAY_CONTROL = 0x0B00).

Write 4’b0101 to 6.3:0 LS_MPY[3:0], write 2’b00 to 7.9:8 LS_IN_RATE[1:0], write 2’b00 to 7.1:0

LS_OUT_RATE [1:0], to select FULL rate and 10x MPY on LS side (LS_SERDES_CONTROL_1 =

0xF115, LS_SERDES_CONTROL_2 = 0xDC04).

•

HS Serial Configuration

Configure the following bits per the desired application:

–

2.9:8 (HS_LOOP_BANDWIDTH[1:0]), 2.6 (HS_VRANGE)

3.15:12 (HS_SWING[3:0]), 3.7:6 (HS_AGCCTRL[1:0])

3.5:4 (HS_AZCAL[1:0]), 4.14:12 (HS_EQPRE[2:0])

65

TLK10002

SLLSE75 –MAY 2011

www.ti.com

–

4.11:10 (HS_CDRFMULT[1:0]), 4.9:8 (HS_CDRTHR[1:0])

4.4:0 (HS_TWCRF[4:0]), 5.12:8 (HS_TWPOST1[4:0])

5.7:4 (HS_TWPRE[3:0]), 5.3:0 (HS_TWPOST2[3:0])

•

LS Serial Configuration

Configure the following bits per the desired application:

–

7.14:12 (LS_SWING[2:0]), 7.7:4 (LS_DE[3:0])

8.11:8 (LS_EQ [3:0]), 8.6:4 (LS_CDR [2:0])

Toggle HS_ENRX

–

Write 1'b0 to 3.2 (HS_SERDES_CONTROL_2 = 0xA440)

Write 1'b1 to 3.2 (HS_SERDES_CONTROL_2 = 0xA444)

•

Wait 10ms

Check SERDES PLL Status for Locked State

–

Poll F.1 LS_PLL_LOCK (per channel) until it is asserted (high)

Poll F.0 HS_PLL_LOCK (per channel) until it is asserted (high)

•

Issue Data path Reset

Write 1’b1 to E.3 DATAPATH_RESET

Clear Latched Registers

Read 0x0F CHANNEL_STATUS_1 to clear (per channel)

–

•

Device provisioning has completed at this point

Periodically Check Device Operational Mode Status (Non-Errored Read Values Shown Below):

–

Read 0x0F CHANNEL_STATUS_1 and verify the following bits:

–

F.14 LA_SLAVE_STATUS (1’b1) (per channel)

F.13 HS_LOS (1’b0) (per channel)

F.12 HS_AZ_DONE (1’b1) (per channel)

F.11 HS_AGC_LOCKED (1’b1) (per channel)

F.10 HS_CHANNEL_SYNC (1’b1) (per channel)

F.8 HS_DECODE_INVALID (1’b0) (per channel)

F.7 TX_FIFO_UNDERFLOW (1’b0) (per channel)

F.6 TX_FIFO_OVERFLOW (1’b0) (per channel)

F.5 RX_FIFO_UNDERFLOW (1’b0) (per channel)

F.4 RX_FIFO_OVERFLOW (1’b0) (per channel)

F.3 RX_LS_OK (1’b1) (per channel).

F.2 TX_LS_OK (1’b1) (per channel).

F.1 LS_PLL_LOCK (1’b1) (per channel)

F.0 HS_PLL_LOCK (1’b1) (per channel)

66

TLK10002

www.ti.com

SLLSE75 –MAY 2011

2:1 Mode (9.8304Gbps on HS side, 4.9152Gbps per lane on LS side, Only Lanes 0 and 1 on LS

side active)

Note: Assume both channel A and channel B have the same setup.

REFCLK frequency = 122.88MHz, Mode = Transceiver, 2 to 1 serialization on LS side inputs and 1 to 2

deserialization on HS side inputs.

•

Device Pin Setting(s) – Pin settings allow for maximum software configurability.

–

Ensure PD_TRXA_N input pin is High.

Ensure PD_TRXB_N input pin is High.

Ensure PRBSEN input pin is Low.

Ensure REFCLKA_SEL input pin is Low to enable software control.

Ensure REFCLKB_SEL input pin is Low to enable software control.

•

Reset Device

–

Issue a hard or soft reset (RESET_N asserted for at least 10 µs -or- Write 1’b1 to 0.15 GLOBAL_RESET)

after power supply stabilization.

•

Enable MDIO global write so that each MDIO write affects both channels to shorten provisioning time

Write 1’b1 to 0.11 GLOBAL_WRITE

Clock Configuration and Mode control

–

Write 1’b0 to 1.9 RX_DEMUX_SEL to select 1 to 2 on the receive side

Write 1’b0 to 1.8 TX_MUX_SEL to select 2 to 1 on the transmit side

Select respective Channel SERDES REFCLK input (Default = REFCLK0P/N)

–

If REFCLK0P/N used – Write 1’b0 to 1.1 REFCLK_ SEL

If REFCLK1P/N used – Write 1’b1 to 1.1 REFCLK_ SEL

•

HS/LS Data Rate Setting (Refer to Table 4 for more CPRI/OBSAI Rates)

–

Write 4’b1101 to 2.3:0 HS_PLL_MULT[3:0], write 2’b00 to 3.9:8 HS_RATE_RX[1:0], write 2’b00 to 3.1:0

HS_RATE_TX[1:0], to select FULL rate and 20x MPY on HS side (HS_SERDES_CONTROL_1 = 0x811D,

HS_SERDES_CONTROL_2 = 0xA444).

–

Write 1'b1 to 9.9 HS_PEAK_DISABLE (HS_OVERLAY_CONTROL = 0x0B00)

Write 4’b1001 to 6.3:0 LS_MPY[3:0], write 2’b00 to 7.9:8 LS_IN_RATE[1:0], write 2’b00 to 7.1:0

LS_OUT_RATE [1:0], to select FULL rate and 20x MPY on LS side (LS_SERDES_CONTROL_1 =

0XF119, LS_SERDES_CONTROL_2 = 0xDC04).

•

HS Serial Configuration

Configure the following bits per the desired application:

–

2.9:8 (HS_LOOP_BANDWIDTH[1:0]), 2.6 (HS_VRANGE)

3.15:12 (HS_SWING[3:0]), 3.7:6 (HS_AGCCTRL[1:0])

3.5:4 (HS_AZCAL[1:0]), 4.14:12 (HS_EQPRE[2:0])

4.11:10 (HS_CDRFMULT[1:0]), 4.9:8 (HS_CDRTHR[1:0])

4.4:0 (HS_TWCRF[4:0]), 5.12:8 (HS_TWPOST1[4:0])

5.7:4 (HS_TWPRE[3:0]), 5.3:0 (HS_TWPOST2[3:0])

•

LS Serial Configuration

Configure the following bits per the desired application:

–

7.14:12 (LS_SWING[2:0]), 7.7:4 (LS_DE[3:0])

8.11:8 (LS_EQ [3:0]), 8.6:4 (LS_CDR [2:0])

Toggle HS_ENRX

–

Write 1'b0 to 3.2 (HS_SERDES_CONTROL_2 = 0xA440)

Write 1'b1 to 3.2 (HS_SERDES_CONTROL_2 = 0xA444)

•

Wait 10ms

Check SERDES PLL Status for Locked State

–

Poll F.1 LS_PLL_LOCK (per channel) until it is asserted (high)

Poll F.0 HS_PLL_LOCK (per channel) until it is asserted (high)

•

Issue Data path Reset

67

TLK10002

SLLSE75 –MAY 2011

www.ti.com

–

Write 1’b1 to E.3 DATAPATH_RESET

•

Clear Latched Registers

–

Read 0x0F CHANNEL_STATUS_1 to clear (per channel)

•

Device provisioning has completed at this point

Periodically Check Device Operational Mode Status (Non-Errored Read Values Shown Below):

–

Read 0x0F CHANNEL_STATUS_1 and verify the following bits:

–

F.14 LA_SLAVE_STATUS (1’b1) (per channel)

F.13 HS_LOS (1’b0) (per channel)

F.12 HS_AZ_DONE (1’b1) (per channel)

F.11 HS_AGC_LOCKED (1’b1) (per channel)

F.10 HS_CHANNEL_SYNC (1’b1) (per channel)

F.8 HS_DECODE_INVALID (1’b0) (per channel)

F.7 TX_FIFO_UNDERFLOW (1’b0) (per channel)

F.6 TX_FIFO_OVERFLOW (1’b0) (per channel)

F.5 RX_FIFO_UNDERFLOW (1’b0) (per channel)

F.4 RX_FIFO_OVERFLOW (1’b0) (per channel)

F.3 RX_LS_OK (1’b1) (per channel).

F.2 TX_LS_OK (1’b1) (per channel).

F.1 LS_PLL_LOCK (1’b1) (per channel)

F.0 HS_PLL_LOCK (1’b1) (per channel)

68

TLK10002

www.ti.com

SLLSE75 –MAY 2011

1:1 Mode (4.9152Gbps on HS side, 4.9152Gbps on LS side, Only Lane 0 on LS side active)

Note: Assume both channel A and channel B have the same setup.

REFCLK frequency = 122.88MHz, Mode = Transceiver, 1 to 1 serialization on LS side inputs and 1 to 1

deserialization on HS side inputs.

•

Device Pin Setting(s) – Pin settings allow for maximum software configurability.

–

Ensure PD_TRXA_N input pin is High.

Ensure PD_TRXB_N input pin is High.

Ensure PRBSEN input pin is Low.

Ensure REFCLKA_SEL input pin is Low to enable software control.

Ensure REFCLKB_SEL input pin is Low to enable software control.

•

Reset Device

–

Issue a hard or soft reset (RESET_N asserted for at least 10 µs -or- Write 1’b1 to 0.15 GLOBAL_RESET)

after power supply stabilization.

•

Enable MDIO global write so that each MDIO write affects both channels to shorten provisioning time

Write 1’b1 to 0.11 GLOBAL_WRITE

Clock Configuration and Mode control

–

Write 1’b1 to 1.13 RX_MODE_SEL to select 1 to 1 on the receive side

Write 1’b1 to 1.12 TX_MODE_SEL to select 2 to 1 on the transmit side

Select respective Channel SERDES REFCLK input (Default = REFCLK0P/N)

–

If REFCLK0P/N used – Write 1’b0 to 1.1 REFCLK_ SEL

If REFCLK1P/N used – Write 1’b1 to 1.1 REFCLK_ SEL

•

HS/LS Data Rate Setting (Refer to Table 4 for more CPRI/OBSAI Rates)

–

Write 4’b1101 to 2.3:0 HS_PLL_MULT[3:0], write 2’b00 to 3.9:8 HS_RATE_RX[1:0], write 2’b00 to 3.1:0

HS_RATE_TX[1:0], to select FULL rate and 20x MPY on HS side (HS_SERDES_CONTROL_1 = 0x811D,

HS_SERDES_CONTROL_2 = 0xA444).

–

Write 4’b1001 to 6.3:0 LS_MPY[3:0], write 2’b00 to 7.9:8 LS_IN_RATE[1:0], write 2’b00 to 7.1:0

LS_OUT_RATE [1:0], to select FULL rate and 20x MPY on LS side (LS_SERDES_CONTROL_1 =

0xF119, LS_SERDES_CONTROL_2 = 0xDC04).

HS Serial Configuration

Configure the following bits per the desired application:

–

2.9:8 (HS_LOOP_BANDWIDTH[1:0]), 2.6 (HS_VRANGE)

3.15:12 (HS_SWING[3:0]), 3.7:6 (HS_AGCCTRL[1:0])

3.5:4 (HS_AZCAL[1:0]), 4.14:12 (HS_EQPRE[2:0])

4.11:10 (HS_CDRFMULT[1:0]), 4.9:8 (HS_CDRTHR[1:0])

4.4:0 (HS_TWCRF[4:0]), 5.12:8 (HS_TWPOST1[4:0])

5.7:4 (HS_TWPRE[3:0]), 5.3:0 (HS_TWPOST2[3:0])

•

LS Serial Configuration

Configure the following bits per the desired application:

–

7.14:12 (LS_SWING[2:0]), 7.7:4 (LS_DE[3:0])

8.11:8 (LS_EQ [3:0]), 8.6:4 (LS_CDR [2:0])

Toggle HS_ENRX

–

Write 1'b0 to 3.2 (HS_SERDES_CONTROL_2 = 0xA449)

Write 1'b1 to 3.2 (HS_SERDES_CONTROL_2 = 0xA44D)

•

Wait 10ms

Check SERDES PLL Status for Locked State

–

Poll F.1 LS_PLL_LOCK (per channel) until it is asserted (high)

Poll F.0 HS_PLL_LOCK (per channel) until it is asserted (high)

•

Issue Data path Reset

Write 1’b1 to E.3 DATAPATH_RESET

–

69

TLK10002

SLLSE75 –MAY 2011

www.ti.com

•

Clear Latched Registers

Read 0x0F CHANNEL_STATUS_1 to clear (per channel)

–

•

Device provisioning has completed at this point

Periodically Check Device Operational Mode Status (Non-Errored Read Values Shown Below):

–

Read 0x0F CHANNEL_STATUS_1 and verify the following bits:

–

F.13 HS_LOS (1’b0) (per channel)

F.12 HS_AZ_DONE (1’b1) (per channel)

F.11 HS_AGC_LOCKED (1’b1) (per channel)

F.7 TX_FIFO_UNDERFLOW (1’b0) (per channel)

F.6 TX_FIFO_OVERFLOW (1’b0) (per channel)

F.5 RX_FIFO_UNDERFLOW (1’b0) (per channel)

F.4 RX_FIFO_OVERFLOW (1’b0) (per channel)

F.1 LS_PLL_LOCK (1’b1) (per channel)

F.0 HS_PLL_LOCK (1’b1) (per channel)

70

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型号：	TLK10002CTR
厂家：	TEXAS INSTRUMENTS
描述：	10Gbps Dual-Channel Multi-Rate Transceiver 10Gbps的双通道多速率收发器线路驱动器或接收器驱动程序和接口接口集成电路
文件：	总73页 (文件大小：619K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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