TLC59108IRGYR [TI]
8-BIT Fm+ I2C-BUS CONSTANT-CURRENT LED SINK DRIVER; 8 - BIT FM + I2C总线恒流LED驱动器
| 型号： | TLC59108IRGYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT Fm+ I2C-BUS CONSTANT-CURRENT LED SINK DRIVER |
| 文件： | 总31页 (文件大小：809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC59108
www.ti.com .................................................................................................................................................................................................. SLDS156–MARCH 2009
8-BIT Fm+ I2C-BUS CONSTANT-CURRENT LED SINK DRIVER
1
FEATURES
2
•
Eight LED Drivers (Each Output Programmable
At Off, On, Programmable LED Brightness,
Programmable Group Dimming/Blinking Mixed
With Individual LED Brightness
•
•
Software Reset Feature (SWRST Call) Allows
Device to be Reset Through I2C Bus
Up to 14 Possible Hardware-Adjustable
Individual I2C Bus Addresses Per Device, So
That Each Device Can Be Programmed
•
•
Eight Constant-Current Open-Drain Output
Channels
•
•
Open-Load/Overtemperature Detection Mode
to Detect Individual LED Errors
256-Step (8-Bit) Linear Programmable
Brightness Per LED Output Varying From Fully
Off (Default) to Maximum Brightness Using a
97-kHz PWM Signal
Output State Change Programmable on the
Acknowledge or the Stop Command to Update
Outputs Byte by Byte or All at the Same Time
(Default to Change on Stop)
•
256-Step Group Brightness Control Allows
General Dimming (Using a 190-Hz PWM Signal
From Fully Off to Maximum Brightness
(Default)
•
•
Output Current Adjusted Through an External
Resistor
Constant Output Current Range: 10 mA to
120 mA
•
•
•
256-Step Group Blinking With Frequency
Programmable From 24 Hz to 10.73 s and Duty
Cycle From 0% to 99.6%
•
•
Maximum Output Voltage: 17 V
25-MHz Internal Oscillator Requires No
External Components
1-MHz Fast Mode Plus Compatible I2C Bus
Interface With 30-mA High Drive Capability on
SDA Output for Driving High-Capacitive Buses
Four Hardware Address Pins Allow 14
TLC59108 Devices to be Connected to the
Same I2C Bus
•
Four Software-Programmable I2C Bus
Addresses (One LED Group Call Address and
Three LED Sub Call Addresses) Allow Groups
of Devices to be Addressed at the Same Time
in Any Combination. For Example, One
Register Used for All Call, so That All the
TLC59108 Devices on the I2C Bus Can be
Addressed at the Same Time, and the Second
Register Can be Used for Three Different
Addresses so That One-Third of All Devices on
the Bus Can be Addressed at the Same Time
in a Group.
•
•
•
•
•
•
•
•
•
Internal Power-On Reset
Noise Filter on SCL/SDA Inputs
No Glitch on Power Up
Active-Low Reset
Supports Hot Insertion
Low Standby Current
3.3-V or 5-V Supply Voltage
5.5-V Tolerant Inputs
Offered in 20-Pin TSSOP (PW) and QFN (RGY)
Packages
•
Software Enable and Disable for I2C Bus
Address
•
–40°C to 85°C Operation
DESCRIPTION/ORDERING INFORMATION
The TLC59108 is an I2C bus controlled 8-bit LED driver that is optimized for red/green/blue/amber (RGBA) color
mixing and backlight application for amusement products. Each LED output has its own 8-bit resolution
(256 steps) fixed-frequency individual PWM controller that operates at 97 kHz, with a duty cycle that is adjustable
from 0% to 99.6%. The individual PWM controller allows each LED to be set to a specific brightness value. An
additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190 Hz and an
adjustable frequency between 24 Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0%
to 99.6%. The group PWM controller dims or blinks all LEDs with the same value.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLC59108
SLDS156–MARCH 2009 .................................................................................................................................................................................................. www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Each LED output can be off, on (no PWM control), or set at its individual PWM controller value at both individual
and group PWM controller values.
The TLC59108 is one of the first LED controller devices in a new Fast-mode Plus (Fm+) family. Fm+ devices
offer higher frequency (up to 1 MHz) and longer, more densely populated bus operation (up to 4000 pF).
Software programmable LED group and three Sub Call I2C bus addresses allow all or defined groups of
TLC59108 devices to respond to a common I2C bus address, allowing for example, all red LEDs to be turned on
or off at the same time or marquee chasing effect, thus minimizing I2C bus commands. Four hardware address
pins allow up to 14 devices on the same bus.
The Software Reset (SWRST) call allows the master to perform a reset of the TLC59108 through the I2C bus,
identical to the Power-On Reset (POR) that initializes the registers to their default state, causing the outputs to
be set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same
condition.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
Reel of 1000
Reel of 2000
ORDERABLE PART NUMBER
TLC59108IRGYR
TOP-SIDE MARKING
Y59108
QFN – RGY
–40°C to 85°C
TSSOP – PW
TLC59108IPWR
Y59108
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
BLOCK DIAGRAM
A0 A1 A2 A3
REXT
OUT0 OUT1
OUT6 OUT7
SCL
SDA
I/O Regulator
I2C Bus Control
Input Filter
Output Driver and Error Detection
Power-On
Reset Control
RESET
LED State
Select Register
PWM Register X
Brightness Control
GRPFRQ
Register
24.3 kHz
97 kHz
GRPPWM
Register
25-MHz
Oscillator
190 kHz
0 = Permanently off
1 = Permanently on
VCC
GND
2
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TLC59108
www.ti.com .................................................................................................................................................................................................. SLDS156–MARCH 2009
RGY PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
R
V
EXT
CC
R
V
1
20
19
18
17
16
15
14
13
12
11
EXT
A0
A1
A2
A3
CC
1
20
2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SDA
SCL
SDA
A0
A1
3
SCL
4
RESET
GND
RESET
GND
A2
A3
5
6
OUT0
OUT1
GND
OUT7
OUT6
GND
OUT7
OUT6
GND
OUT0
OUT1
GND
OUT2
7
8
9
OUT2
OUT3
OUT5
OUT4
OUT5
10
10
11
OUT3
OUT4
TERMINAL FUNCTIONS
TERMINAL
I/O(1)
DESCRIPTION
PW/RGY
PIN NO.
NAME
A0
A1
2
I
I
I
I
Address input 0
Address input 1
Address input 2
Address input 3
Ground
3
A2
4
A3
5
GND
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
RESET
REXT
SCL
8, 13, 16
6
O
O
O
O
O
O
O
O
I
Constant current output 0, LED on at low
Constant current output 1, LED on at low
Constant current output 2, LED on at low
Constant current output 3, LED on at low
Constant current output 4, LED on at low
Constant current output 5, LED on at low
Constant current output 6, LED on at low
Constant current output 7, LED on at low
Active-low reset input
7
9
10
11
12
14
15
17
1
Input terminal used to connect an external resistor for setting up all output currents
18
19
20
I
Serial clock input
Serial data input/output
Power supply
SDA
I/O
VCC
(1) I = input, O = output
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TLC59108
SLDS156–MARCH 2009 .................................................................................................................................................................................................. www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
7
UNIT
V
VCC
VI
Supply voltage range
Input voltage range
–0.4
–0.5
7
V
VO
IO
Output voltage range
20
V
Output current
120
83
mA
°C/W
°C
θJA
TJ
Thermal impedance, junction to free air(2)
Junction temperature range
Storage temperature range
–40
–55
150
150
Tstg
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
0.7 × VCC
0
5.5
VCC
V
V
V
V
High-level input voltage
Low-level input voltage
Supply voltage to output pins
SCL, SDA, RESET, A0, A1, A2, A3
SCL, SDA, RESET, A0, A1, A2, A3
OUT0 to OUT7
0.3 × VCC
17
VO
VCC = 3 V
20
IOL
Low-level output current sink
SDA
mA
VCC = 3 V
30
IO
Output current
OUT0 to OUT7
5
120
mA
°C
TA
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
4
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TLC59108
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ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
SCL, SDA, A0,
A1, A2, A3,
RESET
Input/output leakage
current
II
VI = VCC or GND
±0.3
0.5
µA
Output leakage current
Power-on reset voltage
OUT0 to OUT7 VO = 17 V, TJ = 25°C
µA
VPOR
IOL
2.5
26
V
VCC = 3 V, VOL = 0.4 V
20
30
Low-level output current SDA
mA
VCC = 5 V, VOL = 0.4 V
IO(1)
Output current 1
OUT0 to OUT7 VO = 0.6 V, Rext = 720 Ω, CG = 0.992
mA
%
IO = 26 mA, VO = 0.6 V, Rext = 720 Ω,
Output current error
OUT0 to OUT7
TJ = 25°C
±8
±3
Output channel to
channel current error
IO = 26 mA, VO = 0.6 V, Rext = 720 Ω,
OUT0 to OUT7
TJ = 25°C
%
mA
%
IO(2)
Output current 2
OUT0 to OUT7 VO = 0.8 V, Rext = 360 Ω, CG = 0.992
52
IO = 52 mA, VO = 0.8 V, Rext = 360 Ω,
Output current error
OUT0 to OUT7
TJ = 25°C
±8
±3
Output channel to
channel current error
IO = 52 mA, VO = 0.8 V, Rext = 360 Ω,
OUT0 to OUT7
TJ = 25°C
%
VO = 1 V to 3 V, IO = 26 mA
OUT0 to OUT7
±0.1
±1
IOUT vs
VOUT
Output current vs output
voltage regulation
%/V
VO = 3 V to 5.5 V, IO = 26 mA to 120 mA
Threshold current 1 for
error detection
0.5 ×
ITARGET
IOUT,Th1
IOUT,Th2
IOUT,Th3
OUT0 to OUT7 IOUT,target = 26 mA
OUT0 to OUT7 IOUT,target = 52 mA
OUT0 to OUT7 IOUT,target = 104 mA
%
%
%
Threshold current 2 for
error detection
0.5 ×
ITARGET
Threshold current 3 for
error detection
0.5 ×
ITARGET
TSD
Overtemperature shutdown(2)
150
175
15
200
°C
°C
THYS
Restart hysteresis
SCL, A0, A1,
A2, A3, RESET
Ci
Input capacitance
VI = VCC or GND
VI = VCC or GND
5
5
pF
pF
Cio
Input/output capacitance SDA
OUT0 to OUT7 = OFF,
Rext = Open
17
OUT0 to OUT7 = OFF,
Rext = 720 Ω
20
23
28
21
23
28
OUT0 to OUT7 = OFF,
Rext = 360 Ω
OUT0 to OUT7 = OFF,
Rext = 180 Ω
ICC
Supply current
VCC = 5.5 V
mA
OUT0 to OUT7 = ON,
Rext = 720 Ω
OUT0 to OUT7 = ON,
Rext = 360 Ω
OUT0 to OUT7 = ON,
Rext = 180 Ω
(1) All typical values are at TA = 25°C.
(2) Specified by design
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TLC59108
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TIMING REQUIREMENTS
TA = –40°C to 85°C
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
FAST MODE PLUS
I2C BUS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
I2C Interface
fSCL
SCL clock frequency(1)
I2C bus free time between stop and
start
0
4.7
4
100
0
1.3
0.6
0.6
400
0
0.5
1000 kHz
tBUF
µs
µs
µs
tHD;STA
tSU;STA
Hold time (repeated) Start condition
0.26
0.26
Set-up time for a repeated Start
condition
4.7
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
Set-up time for Stop condition
4
0
0.6
0
0.26
0
µs
Data hold time
ns
Data valid acknowledge time(2)
Data valid time(3)
0.3
0.3
250
4.7
4
3.45
3.45
0.1
0.1
100
1.3
0.6
0.9
0.9
0.05
0.05
50
0.45
0.45
µs
µs
ns
µs
µs
Data set-up time
Low period of the SCL clock
High period of the SCL clock
0.5
tHIGH
0.26
Fall time of both SDA and SCL
signals(4)(5)
(6)
tf
300 20+0.1Cb
1000 20+0.1Cb
50
300
300
50
120
120
50
ns
ns
ns
Rise time of both SDA and SCL
signals
(6)
tr
Pulse width of spikes that must be
suppressed by the input filter(7)
tSP
Reset
tW
Reset pulse width
Reset recovery time
Time to reset(8)(9)
10
0
10
0
10
0
ns
ns
ns
tREC
tRESET
400
400
400
(1) Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
low for a minimum of 25 ms. Disable bus time-out feature for DC operation.
(2) tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low.
(3) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCLs falling edge.
(5) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(6) Cb = total capacitance of one bus line in pF.
(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns
(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(9) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
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TLC59108
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PARAMETER MEASUREMENT INFORMATION
Start
SCL
ACK or Read Cycle
SDA
30%
tRESET
50%
50%
RESET
OUTn
tREC
tW
tRESET
Figure 1. Reset Timing
SDA
SCL
tBUF
tHD;STA
tSP
tr
tf
tLOW
tSU;DAT
tHD;STA
tSU;STO
tHD;DAT
tSU;DAT
tHIGH
P
S
Sr
P
Figure 2. Definition of Timing
Start
Condition
(S)
Bit 7
MSB
(A7)
Stop
Condition
(P)
Bit 6
(A6)
Bit 7
(D1)
Bit 8
(D0)
Acknowledge
(A)
Protocol
tSU;STA
tLOW
tHIGH
1/fSCL
SCL
tr
tf
tBUF
SDA
tHD;STA
NOTE: Rise and fall times refer to VIL and VIH
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
.
Figure 3. I2C Bus Timing
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TLC59108
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
Open
GND
VCC
RL
VI
VO
Pulse
Generator
DUT
RT
CL
NOTE: RL = Load resistance for SDA and SCL; should be >1 kΩ at 3-mA or lower current.
CL = Load capacitance; includes jig and probe capacitance.
RT = Termination resistance; should be equal to the output impedance (ZO) of the pulse generator.
Figure 4. Test Circuit for Switching Characteristics
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TLC59108
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APPLICATION INFORMATION
Functional Description
Device Address
Following a Start condition, the bus master must output the address of the slave it is accessing.
Regular I2C Bus Slave Address
The I2C bus slave address of the TLC59108 is shown in Figure 5. To conserve power, no internal pullup resistors
are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer
management purpose, a set of sector information data should be stored.
Slave Address
1
0
0
A3 A2 A1 A0 R/W
Hardware
Selectable
Fixed
Figure 5. Slave Address
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is
selected. When set to logic 0, a write operation is selected.
LED All Call I2C Bus Address
•
•
•
Default power-up value (ALLCALLADR register): 90h or 1001 000
Programmable through I2C bus (volatile programming)
At power-up, LED All Call I2C bus address is enabled. TLC59108 sends an ACK when 90h (R/W = 0) or 91h
(R/W = 1) is sent by the master.
See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.
NOTE:
The default LED All Call I2C bus address (90h or 1001 000) must not be used as a
regular I2C bus slave address since this address is enabled at power-up. All the
TLC59108s on the I2C bus will acknowledge the address if sent by the I2C bus master
LED Sub Call I2C Bus Address
•
•
Three different I2C bus address can be used
Default power-up values:
–
–
–
SUBADR1 register: 92h or 1001 001
SUBADR2 register: 94h or 1001 010
SUBADR3 register: 98h or 1001 100
•
•
Programmable through I2C bus (volatile programming)
At power-up, Sub Call I2C bus address is disabled. TLC59108 does not send an ACK when 92h (R/W = 0) or
93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.
See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.
NOTE:
The default LED Sub Call I2C bus address may be used as a regular I2C bus slave
address as long as they are disabled.
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TLC59108
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Software Reset I2C Bus Address
The address shown in Figure 6 is used when a reset of the TLC59108 needs to be performed by the master. The
software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59108 does not
acknowledge the SWRST. See Software Reset for more detail.
1
0
0
1
0
1
1
R/W
Figure 6. Software Reset Address
NOTE:
The Software Reset I2C bus address is reserved address and cannot be use as
regular I2C bus slave address or as an LED All Call or LED Sub Call address.
Control Register
Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address,
the bus master will send a byte to the TLC59108, which will be stored in the Control register. The lowest 5 bits
are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as
Auto-Increment flag and Auto-Increment options (AI[2:0]).
Auto-Increment
Flag
Register Address
AI2 AI1 AI0 D4 D3 D2 D1 D0
Auto-Increment
Options
Figure 7. Control Register
When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the registers sequentially. Four
different types of Auto-Increment are possible, depending on AI1 and AI0 values.
Table 1. Auto-Increment Options
AI2
AI1
AI0
DESCRIPTION
0
0
0
No auto-increment
Auto-increment for all registers. D[4:0] roll over to 0 0000 after the last register (1 1011) is
accessed.
1
1
1
1
0
0
1
1
0
1
0
1
Auto-increment for individual brightness registers only. D[4:0] roll over to 0 0010 after the last
register (1 0001) is accessed.
Auto-increment for global control registers only. D[4:0] roll over to 1 0010 after the last register (1
0011) is accessed.
Auto-increment for individual and global control registers only. D[4:0] roll over to 0 0010 after the
last register (1 0011) is accessed.
NOTE:
Other combinations not shown in Table 1. (AI[2:0] = 001, 010 and 011) are reserved
and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus
communication, for example, changes the brightness of a single LED. Data is overwritten each time the register
is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the
same I2C bus communication, for example, changing color setting to another color setting.
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AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same
I2C bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus
communication, for example, changing color and global brightness at the same time.
Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the first register that will be
addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in ). When
AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment
stops and goes to the next one is determined by AI[2:0]. See for rollover values. For example, if the Control
register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):
14 → ... → 1B → 00 → ... → 13 → 02 → ... → 13 → 02 → ... as long as the master keeps sending or reading
data.
Driver Output
Constant Current Output
In LED display applications, TLC59108 provides nearly no current variations from channel to channel and from
device to device. While IOUT ≤ 100 mA, the maximum current skew between channels is less than ±3% and less
than ±6% between devices.
Adjusting Output Current
TLC59108 scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current (Iout) at
each output port. The following formulas can be used to calculate the target output current IOUT,target in the
saturation region:
VREXT = 1.26 V × VG
Iref = VREXT/Rext, if another end of the external resistor Rext is connected to ground
IOUT,target = Iref × 15 × 3CM – 1
Where Rext is the resistance of the external resistor connected to the REXT terminal, and VREXT is the voltage of
REXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code.
The Current Multiplier (CM) determines that the ratio IOUT,target/Iref is 15 or 5. After power on, the default value of
VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio IOUT,target/Iref = 15. Based on the default
VG and CM.
VREXT = 1.26 V × 127/128 = 1.25 V
IOUT,target = (1.25 V/Rext) × 15
Therefore, the default current is approximately 52 mA at 360 Ω and 26 mA at 720 Ω. The default relationship
after power on between IOUT,target and Rext is shown in Figure 8.
140
120
100
80
40
0
0
500 1000
1500 2000 2500 3000 3500 4000
Rext – W
Figure 8. IOUT,target vs Rext
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Register Descriptions
Table 2 describes the registers in the TLC59108.
Table 2. Register Descriptions
REGISTER
NUMBER
(HEX)
NAME
MODE1
ACCESS(1) DESCRIPTION
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Mode 1
MODE2
PWM0
Mode 2
Brightness control LED0
Brightness control LED1
Brightness control LED2
Brightness control LED3
Brightness control LED4
Brightness control LED5
Brightness control LED6
Brightness control LED7
Group duty cycle control
Group frequency
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
GRPPWM
GRPFREQ
LEDOUT0
LEDOUT1
SUBADR1
SUBADR2
SUBADR3
ALLCALLADR
IREF
LED output state 0
LED output state 1
I2C bus subaddress 1
I2C bus subaddress 2
I2C bus subaddress 3
LED All Call I2C bus address
IREF configuration
Error flag
EFLAG
(1) R = read, W = write
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Mode Register 1 (MODE1)
Table 3 describes Mode Register 1.
Table 3. MODE1 – Mode Register 1 (Address 00h) Bit Description
BIT
SYMBOL
ACCESS(1)
VALUE
0(2)
1
DESCRIPTION
Register Auto-Increment disabled
Register Auto-Increment enabled
Auto-Increment bit 1 = 0
Auto-Increment bit 1 = 1
Auto-Increment bit 0 = 0
Auto-Increment bit 0 = 1
Normal mode(3)
Low power mode. Oscillator off(4)
.
Device does not respond to I2C bus subaddress 1.
Device responds to I2C bus subaddress 1.
Device does not respond to I2C bus subaddress 2.
Device responds to I2C bus subaddress 2.
Device does not respond to I2C bus subaddress 3.
Device responds to I2C bus subaddress 3.
Device does not respond to LED All Call I2C bus address.
Device responds to LED All Call I2C bus address.
7
AI2
R
0(2)
6
5
4
3
2
1
0
AI1
AI0
R
1
0(2)
1
R
0
SLEEP
SUB1
SUB2
SUB3
ALLCALL
R/W
R/W
R/W
R/W
R/W
1(2)
0(2)
1
0(2)
1
0(2)
1
0
1(2)
(1) R = read, W = write
(2) Default value
(3) Requires 500 µs maximum for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LED outputs are
not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 100 µs window.
(4) No blinking or dimming is possible when the oscillator is off.
Mode Register 2 (MODE2)
Table 4 describes Mode Register 2.
Table 4. MODE2 – Mode Register 2 (Address 01h) Bit Description
BIT
7
SYMBOL
ACCESS(1)
VALUE
0(2)
1
0(2)
0(2)
1
0(2)
0(2)
1
DESCRIPTION
Enable error status flag
Clear error status flag
Reserved
EFCLR
R/W
R
6
Group control = dimming
Group control = blinking
Reserved
Outputs change on Stop command(3)
Outputs change on ACK
Reserved
5
DMBLNK
OCH
R/W
R
4
3
R/W
R
2:0
000(2)
(1) R = read, W = write
(2) Default value
(3) Change of the outputs at the Stop command allows synchronizing outputs of more than one TLC59108. Applicable to registers from 02h
(PWM0) to 0Dh (LEDOUT) only.
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Brightness Control Registers 0 to 7 (PWM0 to PWM7)
Table 6 describes Brightness Control Registers 0 to 7.
Table 5. PWM0 to PWM7 – PWM Registers 0 to 7 (Address 02h to 09h) Bit Description
ADDRESS
02h
REGISTER
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
BIT
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
SYMBOL
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
IDC4[7:0]
IDC5[7:0]
IDC6[7:0]
IDC7[7:0]
ACCESS(1)
VALUE
DESCRIPTION
R/W
0000 0000(2) PWM0 individual duty cycle
0000 0000(2) PWM1 individual duty cycle
0000 0000(2) PWM2 individual duty cycle
0000 0000(2) PWM3 individual duty cycle
0000 0000(2) PWM4 individual duty cycle
0000 0000(2) PWM5 individual duty cycle
0000 0000(2) PWM6 individual duty cycle
0000 0000(2) PWM7 individual duty cycle
03h
R/W
04h
R/W
05h
R/W
06h
R/W
07h
R/W
08h
R/W
09h
R/W
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).
Duty cycle = IDCn[7:0] / 256
Group Duty Cycle Control Register (GRPPWM)
Table 6 describes the Group Duty Cycle Control Register.
Table 6. GRPPWM – Group Brightness Control Register (Address 0Ah) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS(1)
VALUE
DESCRIPTION
0Ah
GRPPWM
7:0
GDC0[7:0]
R/W
1111 1111(2) GRPPWM register
(1) R = read, W = write
(2) Default value
When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is
superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness
control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't
care.
General brightness for the eight outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with
LDRx = 11 (LEDOUT0 and LEDOUT1 registers).
When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ defines the blinking period (from 24 Hz to 10.73 s) and GRPPWM defines the duty
cycle (ON/OFF ratio in %).
Duty cycle = GDC0[7:0] / 256
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Group Frequency Register (GRPFREQ)
Table 7 describes the Group Frequency Register.
Table 7. GRPFREQ – Group Frequency Register (Address 0Bh) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS(1)
VALUE
DESCRIPTION
0Bh
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000(2) GRPFREQ register
(1) R = read, W = write
(2) Default value
GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1.
Value in this register is a Don't care when DMBLNK = 0. Applicable to LED output programmed with LDRx = 11
(LEDOUT0 and LEDOUT1 registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24
LED Driver Output State Registers (LEDOUT0, LEDOUT1)
Table 8 describes LED Driver Output State Registers 0 and 1.
Table 8. LEDOUT0 and LEDOUT1 – LED Driver Output State Registers (Address 0Ch and 0Dh) Bit
Description
ADDRESS
REGISTER
BIT
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
SYMBOL
LDR3[1:0]
LDR2[1:0]
LDR1[1:0]
LDR0[1:0]
LDR7[1:0]
LDR6[1:0]
LDR5[1:0]
LDR4[1:0]
ACCESS(1)
VALUE
00(2)
00(2)
00(2)
00(2)
00(2)
00(2)
00(2)
00(2)
DESCRIPTION
R/W
LED3 output state control
LED2 output state control
LED1 output state control
LED0 output state control
LED7 output state control
LED6 output state control
LED5 output state control
LED4 output state control
R/W
0Ch
LEDOUT0
R/W
R/W
R/W
R/W
0Dh
LEDOUT1
R/W
R/W
(1) R = read, W = write
(2) Default value
LDRx = 00: LED driver x is off (default power-up state).
LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx
register and the GRPPWM registers.
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I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)
Table 9 describes I2C Bus Subaddress Registers 1 to 3.
Table 9. SUBADR1 to SUBADR3 – I2C Bus Subaddress Registers 1 to 3 (Address 0Eh to 10h) Bit
Description
ADDRESS
REGISTER
BIT
7:5
4:1
0
SYMBOL
A1[7:5]
A1[4:1]
A1[0]
ACCESS(1)
VALUE
100(2)
1001(2)
0(2)
DESCRIPTION
R
R/W
R
Reserved
0Eh
SUBADR1
I2C bus subaddress 1
Reserved
7:5
4:1
0
A2[7:1]
A2[4:1]
A2[0]
R
100(2)
1010(2)
0(2)
100(2)
1100(2)
0(2)
Reserved
I2C bus subaddress 2
0Fh
10h
SUBADR2
SUBADR3
R/W
R
Reserved
7:5
4:1
0
A3[7:1]
A3[4:1]
A3[0]
R
Reserved
I2C bus subaddress 3
R/W
R
Reserved
(1) R = read, W = write
(2) Default value
Subaddresses are programmable through the I2C bus. Default power-up values are 92h, 94h, 98h. The
TLC59108 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit in
MODE1 register is equal to 0).
Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to
allows the device to acknowledge these addresses.
Only the 7 MSBs representing the I2C bus subaddress are valid. The LSB in SUBADRx register is a read-only bit
(0).
When SUBx is set to 1, the corresponding I2C bus subaddress can be used during either an I2C bus read or write
sequence.
LED All Call I2C Bus Address Register (ALLCALLADR)
Table 10 describes the LED All Call I2C Bus Address Register.
Table 10. ALLCALLADR – LED All Call I2C Bus Address Register (Address 11h) Bit Description
ADDRESS
REGISTER
BIT
7:5
4:1
0
SYMBOL
AC[7:5]
AC[4:1]
AC[0]
ACCESS(1)
VALUE
100(2)
1000(2)
0(2)
DESCRIPTION
R
R/W
R
Reserved
11h
ALLCALLADR
All Call I2C bus address register
Reserved
(1) R = read, W = write
(2) Default value
The LED All Call I2C bus address allows all the TLC59108 devices in the bus to be programmed at the same
time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is
programmable through the I2C bus and can be used during either an I2C bus read or write sequence. The
register address can also be programmed as a Sub Call.
Only the 7 MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a
read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.
Output Gain Control Register (IREF)
Table 11 describes the Output Gain Control Register.
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Table 11. IREF – Output Gain Control Register (Address 12h) Bit Description
ADDRESS
REGISTER
BIT
7
SYMBOL
CM
ACCESS(1)
VALUE
1(2)
1(2)
DESCRIPTION
R/W
High/low current multiplier
Subcurrent
11h
ALLCALLADR
6
HC
R/W
5:0
CC[5:0]
R/W
11 1111(2)
Current multiplier
(1) R = read, W = write
(2) Default value
IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the reference
current (IREF) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM) bit, which
determines the ratio IOUT,target/Iref. Each combination of VG and CM sets a Current Gain (CG).
•
VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown below:
VG = (1 + HC) × (1 + D/64) / 4
D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point
number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage
gain VG into 128 steps and two sub-bands:
Low voltage sub-band (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps
High voltage sub-band (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps
CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
CG: The total Current Gain is defined as the following.
•
•
VREXT = 1.26 V × VG
Iref = VREXT/Rext, if the external resistor, Rext, is connected to ground.
IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG
CG = VG × 3CM – 1
Therefore, CG = (1/12) to (127/128), and it is divided into 256 steps. If CG = 127/128 = 0.992, the
IOUT,target-Rext
.
Examples
•
•
•
IREF Code {CM, HC, CC[0:5]} = {1,1,111111}
VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992
IREF Code {CM, HC, CC[0:5]} = {1,1,000000}
VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
IREF Code {CM, HC, CC[0:5]} = {0,0,000000}
VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12
After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore,
VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 9.
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1.00
CM = 0 (Low Current Multiplier)
0.75
HC = 0 (Low
Voltage SubBand)
HC = 1 (High
Voltage SubBand)
HC = 0 (Low
Voltage SubBand)
0.50
0.25
0.00
HC = 1 (High
Voltage SubBand)
CM = 1 (High Current Multiplier)
Configuration Code (CM, HC, CC[0:5]) in Binary Format
Figure 9. Current Gain vs Configuration Code
Error Flags Registers (EFLAG)
Table 12 describes the Error Flags Register.
Table 12. EFLAG – Error Flags Register (Address 13h) Bit Description
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS(1)
VALUE
DESCRIPTION
13h
EFLAG
7:0
EFLAG[7:0]
R
1111 1111(2) Error flag status by channel
(1) R = read, W = write
(2) Default value
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Open-Circuit Detection
The TLC59108 LED open-circuit detection compares the effective current level Iout with the open load detection
threshold current IOUT, Th. If IOUT is below the threshold IOUT, Th the TLC59108 detects an open load condition. This
error status can be read out as an error flag through the EFLAG register.
For open-circuit error detection, a channel must be on.
Table 13. Open-Circuit Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT
ERROR STATUS CODE
MEANING
CURRENT
Off
IOUT = 0 mA
0
Detection not possible
Open circuit
(1)
IOUT < IOUT,Th
0
On
(1)
I
OUT ≥ IOUT,Th
Channel n error status bit 1
Normal
(1) IOUT,Th = 0.5 × IOUT,target (typical)
Overtemperature Detection and Shutdown
The TLC59108 LED is equipped with a global overtemperature sensor and eight individual channel-selective
overtemperature sensors.
•
When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
after cooling down and can be read out as the error status code in the EFLAG register.
•
When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in the
EFLAG register.
For channel-specific overtemperature error detection, a channel must be on.
The error flags of open-circuit and overtemperature are ORed to set the EFLAG register.
The error status code due to overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The
host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag.
Table 14. Overtemperature Detection(1)
STATE OF OUTPUT PORT
CONDITION
Tj < Tj,trip global
ERROR STATUS CODE
MEANING
Normal
1
On
On → all channels Off
Tj > Tj,trip global
All error status bits = 0
1
Global overtemperature
Normal
Tj < Tj,trip channel n
Tj > Tj,trip channel n
On
On → Off
Channel n error status bit = 0
Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TLC59108 in a reset condition until VCC
reaches VPOR. At this point, the reset condition is released and the TLC59108 registers, and I2C bus state
machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter,
VCC must be lowered below 0.2 V to reset the device.
External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59108 registers and
I2C state machine are held in their default states until the RESET input is again high.
This input requires a pullup resistor to VCC if no active connection is used.
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Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state
value through a specific I2C bus command. To be performed correctly, the I2C bus must be functional and there
must be no device hanging the bus.
The SWRST Call function is defined as the following:
1. A Start command is sent by the I2C bus master.
2. The reserved SWRST I2C bus address 1101 011 with the R/W bit set to 0 (write) is sent by the I2C bus
master.
3. The TLC59108 device(s) acknowledge(s) after seeing the SWRST Call address 1101 0110 (96h) only. If the
R/W bit is set to 1 (read), no acknowledge is returned to the I2C bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two
specific values (SWRST data byte 1 and byte 2):
a. Byte1 = A5h: the TLC59108 acknowledges this value only. If byte 1 is not equal to A5h, the TLC59108
does not acknowledge it.
b. Byte 2 = 5Ah: the TLC59108 acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59108
does not acknowledge it.
If more than two bytes of data are sent, the TLC59108 does not acknowledge any more.
5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly
acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59108 then resets to
the default value (power-up value) and is ready to be addressed again within the specified bus free time
(tBUF).
The I2C bus master may interpret a non-acknowledge from the TLC59108 (at any time) as a SWRST Call Abort.
The TLC59108 does not initiate a reset of its registers. This happens only when the format of the Start Call
sequence is not correct.
Individual Brightness Control With Group Dimming/Blinking
A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual
brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four
LED outputs):
•
A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global
brightness control.
•
A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking
control.
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N × 40 ns
with N = 0 to 255
(PWM register)
M × 256 × 2 × 40 ns
with M = 0 to 255
256 × 40 ns = 10.24 µs
(GRPPWM register)
(97.6 kHz)
Group Dimming Signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
Resulting Brightness + Group Dimming Signal
NOTE: Minimum pulse width for LEDn brightness control is 40 ns.
Minimum pulse width for group dimming is 20.48 µs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two
pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).
This resulting Brightness + Group Dimming signal shows a resulting control signal with n = 4 (8 pulses).
Figure 10. Brightness and Group Dimming Signals
Characteristics of the I2C Bus
The I2C bus is for two-way two-line communication between different devices or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a
pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 11).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 11. Bit Transfer
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Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 12).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 12. Start and Stop Conditions
System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices which are controlled by the master are the slaves (see Figure 13).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
I2C Bus
Multiplexer
Slave
Receiver
Master
Transmitter
Slave
Figure 13. System Configuration
Acknowledge
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on
the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and
hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a Stop condition.
22
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TLC59108
www.ti.com .................................................................................................................................................................................................. SLDS156–MARCH 2009
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
1
2
8
9
Master
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 14. Acknowledge/Not Acknowledge on I2C Bus
Slave Address
Control Register
S A6 A5 A4 A3 A2 A1 A0
0
A
X
X
X
D4 D3 D2 D1 D0
A
A
P
Start Condition
R/W
ACK From Slave
Auto-Increment Options
ACK From Slave Stop Condition
Auto-Increment Flag
ACK From Slave
Figure 15. Write to a Specific Register
Slave Address
Control Register
MODE1 Register
MODE2 Register
S A6 A5 A4 A3 A2 A1 A0
0
A
1
0
0
0
0
0
0
0
A
A
A
Start Condition
R/W
ACK From Slave
MODE1 Register Selection
Auto-Increment On All Registers (see Note A)
Auto-Increment On
ACK From Slave
ACK From Slave
SUBADR3 Register
ALLCALLADR Register
A
A
P
ACK From Slave
ACK From Slave Stop Condition
A. See Table 2 for register definitions.
Figure 16. Write to All Registers Using Auto-Increment
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23
TLC59108
SLDS156–MARCH 2009 .................................................................................................................................................................................................. www.ti.com
Slave Address
Control Register
PWM0 Register
PWM1 Register
S A6 A5 A4 A3 A2 A1 A0
0
A
1
0
1
0
0
0
1
0
A
A
A
Start Condition
R/W
ACK From Slave
PWM0 Register Selection
Auto-Increment On Brightness Registers Only
Auto-Increment On
ACK From Slave
ACK From Slave
PWM4 Register
PWM5 Register
PWM0 Register
PWMx Register
A
A
A
A
P
ACK From Slave
ACK From Slave
ACK From Slave
ACK From Slave
Stop Condition
Figure 17. Multiple Writes to Individual Brightness Registers Using Auto-Increment
Slave Address
Control Register
Slave Address
Data From MODE1 Register
A
0
0
A6
A5 A4 A3 A2 A1 A0
Sr
S
A6 A5 A4 A3 A2 A1 A0
A
1
0
0
0
0
0
0
A
1
A
Start Condition
R/W
ACK From Slave
MODE1 Register Selection
Auto-Increment On All Registers
Auto-Increment On
ACK From Slave
R/W ACK From Slave
ACK From Master
Data From MODE2 Register
Data From PWM0 Register
Data From ALLCALLADR Register Data From MODE1 Register
A
A
A
A
ACK From Master
ACK From Master
ACK From Master
ACK From Master
Data From Last Read Byte
A
P
ACK From Master
Stop Condition
Figure 18. Read All Registers Auto-Increment
24
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Copyright © 2009, Texas Instruments Incorporated
TLC59108
www.ti.com .................................................................................................................................................................................................. SLDS156–MARCH 2009
New LED All Call I2C Address
(see Note B)
Slave Address
Control Register
0
S A6 A5 A4 A3 A2 A1 A0
0
A
X
X
X
1
1
0
1
1
A
1
0
1
1
0
1
X
A
P
Sequence A
Start Condition
R/W
ACK From Slave
ALLCALLADR Register Selection
Auto-Increment Options
Auto-Increment Flag
ACK From Slave
ACK From Slave Stop Condition
The 16 LEDs are on at ACK (see Note C)
LEDOUT0 Register (LED3 to 0 Fully On)
LED All Call I2C Address
Control Register
1
1
X
1
0
0
S
0
0
1
0
1
0
A
X
X
0
1
0
0
A
1
0
1
1
0
1
A
P
Sequence B
Start Condition
R/W
ACK From the
Four Slaves
ACK From the Stop Condition
Four Slaves
LEDOUT0 Register Selection
ACK From Slave
A. In this example, several TLC59108 devices are used, and the same Sequence A is sent to each of them.
B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.
C. The OCH bit in the MODE2 register is equal to 1 for this example.
Figure 19. LED All Call I2C Bus Address Programming and LED All Call Sequence
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25
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2010
PACKAGING INFORMATION
Orderable Device
TLC59108IPWR
TLC59108IRGYR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
VQFN
RGY
20
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC59108IPWR
TLC59108IRGYR
TSSOP
VQFN
PW
20
20
2000
3000
330.0
180.0
16.4
12.4
6.95
3.8
7.1
4.8
1.6
1.6
8.0
8.0
16.0
12.0
Q1
Q1
RGY
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC59108IPWR
TLC59108IRGYR
TSSOP
VQFN
PW
20
20
2000
3000
346.0
190.5
346.0
212.7
33.0
31.8
RGY
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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