TLC5910PZP [TI]
LED DRIVER; LED驱动器型号: | TLC5910PZP |
厂家: | TEXAS INSTRUMENTS |
描述: | LED DRIVER |
文件: | 总30页 (文件大小:476K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Drive Capability and Output Counts
– 80 mA (Current Sink) x 16 Bits
Protection
– WDT (Watchdog Timer) Function (Turn
Output Off When Scan Signal Stopped)
– TSD (Thermal Shutdown) Function (Turn
Output Off When Junction Temperature
Exceeds Limit)
Constant Current Output Range
– 5 to 80 mA (Current Value Setting for All
Output Terminals Using External Resistor
and Internal Brightness Control Register)
LOD
Constant Current Accuracy
– LED Open Detection (Detection for LED
Disconnection)
– ±4% (Maximum Error Between Bits)
Voltage Applied to Constant Current Output
Terminals
– Minimum 0.4 V (Output Current 5 to
‡
Data Input/Output
– Port A (for Data Display)
– Clock Synchronized 10 Bit Parallel
Input (Schmitt Triggered Input)
– Clock Synchronized 10 Bit Parallel
Output (3-State Output)
40 mA)
– Minimum 0.7 V (Output Current 40 to
80 mA)
1024 Gray Scale Display
– Pulse Width Control 1024 Steps
– Port B (for Dot Correction Data)
– Clock Synchronized 6 Bit Parallel
Input (Schmitt-Triggered Input)
– Clock Synchronized 6 Bit Parallel
Output
†
Brightness Adjustment
– All Output Current Adjustment for 64
Steps (Adjustment for Brightness
Deviation Between LED Modules)
– Output Current Adjustment by Output
(OUT0 to OUT15) for 64 Steps
(Adjustment for Brightness Deviation
Between Dots)
– Brightness Control by 16 Steps
Frequency Division Gray Scale Control
Clock (Brightness Adjustment for Panel)
Input/Output Signal Level
– CMOS Level
Power Supply Voltage
– 4.5 V to 5.5 V (Logic, Analog and
Constant Current)
– 3 V to 5.5 V (Interface)
Maximum Output Voltage . . . 15 V (Max)
Data Transfer Rate . . . 20 MHz (Max)
Gray Scale Clock Generation
– Gray Scale Control Clock Generation by
Internal PLL or External Input Selectable
Gray Scale Clock Frequency
– 16 MHz (Max) Using Internal PLL
– 8 MHz (Max) Using External Clock
Clock Invert/Noninvert Selectable
– Clock Invert Selectable to Reduce
Changes in Duty Ratio at Cascade
Operation
Operating Free-Air Temperature Range
–20°C to 85°C
100-Pin HTQFP Package (P =4.7 W,
D
T = 25°C)
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
‡
These functions are adjustable independently.
Allows the writting of all the data at port A by setting the logic to 1.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
description
The TLC5910 is a constant current driver, incorporating a shift register, data latch, and constant current circuitry
with current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display
using pulse width control. The output current is a maximum of 80 mA with 16 bits, and the current value of
constant current output can be set by one external resistor. The device has two channel I/O ports. The
brightness deviation between LED modules (ICs) can be adjusted by external data input from a display data
port. The brightness control for the panel can be accomplished by the brightness adjustment circuitry.
Independentlyofthesefunctions, thedeviceincorporatestheshiftregisteranddatalatchtocorrectthedeviation
between LEDs adjusting output current using data from a dot correction data port. Moreover, the device
incorporates watchdog timer (WDT) circuitry, which turns the constant current output off when a scan signal is
stopped at the dynamic scanning operation. It incorporates thermal shutdown (TSD) circuitry, which turns
constant current output off when the junction temperature exceeds the limit. It also incorporates LOD (LED open
detection) circuitry, which creates an error signal output when LED disconnection occurs and test mode
functions detect LED open or short conditions.
PZP PACKAGE
(TOP VIEW)
GNDLED
OUT0
OUT1
GNDLED
OUT2
OUT3
GNDLED
OUT4
OUT5
GNDLED
OUT6
1
2
3
4
5
6
7
8
VCOIN
RBIAS
MAG0
MAG1
MAG2
PDOUT
GSPOL
GSCLK
BLANK
XENABLE
XOE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OUT7
GNDLED
OUT8
DCLK
XLATCH
DCCLK
XDCLAT
RSEL0
RSEL1
LEDCHK
OPEN
WDTRG
XDOWN1
XDOWN2
BOUT
OUT9
GNDLED
OUT10
OUT11
GNDLED
OUT12
OUT13
GNDLED
OUT14
OUT15
GNDLED
XGSOUT
XPOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
functional block diagram
XOE
BCENA
DCLK
DPOL
DCLK
Control
DOUT 0–9
XENABLE
DIN 0–9
,
1 x 10 bit B.C.
Data Shift Register
Data Latch
16 x 10 bit
Data Shift Register
XLATCH
RSEL 0–1
DCDIN 0–5
..........
16 x 10 bit
Data Latch
,
XDCLAT,
DCCLK
..........
XPOUT
XGSOUT
MAG 0–2 , GSPOL,
GSCLK, RBIAS,
10 bit
Clock Countor
16 x 10 bit
Data Comparator
VCOIN, PDOUT
PLL
BLANK
XRST
BOUT
..........
OUT0
· · ·
OUT15
16 bit
LED Driver+LOD
WDCAP
WDTRG
WDT
TSD
XDOWN1
XDOWN2
LEDCHK
XDOWN2TST
..........
TSENA
16 bit
Current Controller
..........
IREF
16 x 6 bit
D.C. Data Latch
DCENA
..........
16 x 6 bit
D.C. Data Shift Register
DCDOUT 0–5
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C (Dot Control) : Adjustment for brightness deviation between dots.
NOTE: All the input terminals are with Schmitt-triggered inverters except RBIAS, VCOIN, PDOUT, IREF, and WDCAP.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
functional block diagram for shift register and data latch
XOE
10 16
10 16
DATA
S/R
DATA
LATCH
DATA
Comparator
†
1
10
DCLK
DPOL
XENABLE
a
DCLK
Controller
A
B
b
c
a
DCCLK
A
10
10
b
c
0
1
10
DOUT<0–9>
10
a
b
c
HI–Z
10
6
A
B
DIN<0–9>
10
10
10
B.C.
S/R
B.C.
LATCH
Clock Counter
Current Controller
DCDIN<0–5>
a
A
B
XLATCH
XDCLAT
b
c
6
DCDOUT<0–5>
‡
2
6
6 16
6 16
RSEL<0–1>
D.C.
S/R
D.C.
LATCH
1
6 16
DATA
Comparator
0
6 16
Default
BCENA
DCENA
†
‡
1 : Connect to 16th 10 bit bus
2 : Connect to 16th 6 bit bus
B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels.
D.C. (dot control) : Adjustment for brightness deviation between dots.
RSEL
CONNECTION
RSEL1
RSEL0
0
0
1
1
0
1
0
1
A – a, B – c
A – b, B – c
A – c
INHIBIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
schematic
Input
VCCIF
INPUT
GNDLOG
DOUT0–9, DCDOUT0–5, XGSOUT, XPOUT, BOUT
VCCLOG
OUTPUT
GNDLOG
XDOWN1, XDOWN2
XDOWN1, XDOWN2
GNDLOG
OUTn
OUTn
GNDLED
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Brightness control enable. When BCENA is low, brightness control latch is set to the default
value. The output current value in this status is 100% of setting the value by an external resistor.
ThefrequencydivisionratioofGSCLKis1/1. WhenBCENAishigh, writingtobrightnesscontrol
latch is enabled.
BCENA
94
I
Blank(light off). When BLANK is high, all outputs of the constant current driver are turned off.
When GSPOL is high, the output is turned on (LED on), synchronizing to the falling edge of
GSCLKafterthenextrisingedgeofGSCLK, whenBLANKgoesfromhightolow. WhenGSPOL
is low, the output is turned on (LED on), synchronizing to the rising edge of GSCLK after the
next falling edge of GSCLK, when BLANK goes from high to low.
BLANK
67
I
BOUT
53
62
O
I
BLANK buffered output
Clock input for data transfer. The input data is from DCDIN (port B) , output data at DCDOUT,
and all data on the shift register for dot correction data, from DCDIN, is shifted by 1 bit
synchronizing to the rising edge of DCCLK.
DCCLK
DCDIN0 –
DCDIN5
86,87,88,
89,90,91
Input for 6 bit parallel data (port B). These terminals are used as a shift register input for dot
correction data.
I
O
I
DCDOUT0 –
DCDOUT5
40,39,38,
37,36,35
Output for 6 bit parallel data (port B). These terminals are used as a shift register output for dot
correction data.
Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.
At this time, the output current value is 100% of the value set by an external resistor.
DCENA
DCLK
95
64
Clock input for data transfer. The input data is from DIN (port A) , all data on the shift register
selected by RSEL, 1 and output data at DOUT is shifted by 1 bit synchronizing to DCLK. Note
that synchronizing to either the rising or falling edge of DCLK depends on the value of DPOL.
I
I
Inputfor10bitparalleldata(portA). Theseterminalsareinputstotheshiftregisterforgrayscale
data,brightnesscontrol,anddotcorrectiondata.TheregisterselectedisdeterminedbyRSEL0,
1.
76,77,78,79,80,
81,82,83,84,85
DIN0 – DIN9
Output for 10 bit parallel data (port A). These terminals are outputs to the shift register for gray
scale data, brightness control, and dot correction data. The register selected is determined by
RSEL0, 1.
DOUT0 –
DOUT9
50,49,48,47,46,
45,44,43,42,41
O
I
Select the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When
DPOL is low, the falling edge of DCLK is valid.
DPOL
96
GNDANA
GNDLOG
28
98
Analog ground (internally connected to GNDLOG and GNDLED)
Logic ground (internally connected to GNDANA and GNDLED)
1,4,7,10,13,
16,19,22,25
GNDLED
LED driver ground (internally connected to GNDANA and GNDLED)
Clock input for gray scale. When MAG0 to MAG2 are all low, GSCLK is used for pulse width
control, and GSCLK is used for PLL timing control when either MAG is not low. The gray scale
display is accomplished by lighting LEDs on until the number of GSCLK or PLL clocks counted
is equal to data latched.
GSCLK
68
I
I
Selectthe valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When
GSPOL is low, the falling edge of GSCLK is valid.
GSPOL
IREF
69
32
58
Constantcurrentvaluesetting. LEDcurrentissettothedesiredvaluebyconnectinganexternal
I/O resistor between IREF and GND. The 38 times current compares current across the external
resistor sink on the output terminal.
LED disconnection detection enable. When LEDCHK is high, LED disconnection detection is
enabledandXDOWN2isvalid. WhenLEDCHKislow, LEDdisconnectiondetectionisdisabled.
LEDCHK
I
MAG0 – MAG2
OPEN
73,72,71
57
I
PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set.
TEST. Factory test terminal. OPEN should be opened.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
2,3,5,6,8,9,11,12,
14,15,17,18,20,21,
23,24
OUT0–DOUT15
O
Constant current output
PDOUT
RBIAS
70
74
I/O
I/O
Resistor connection for PLL feedback adjustment
Resistor connection for PLL oscillation frequency setting
Input/output port selection and shift register data latch switching.
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected
to port A and the dot correction register latch is selected to port B.
When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
port A and the dot correction register latch is selected to port B.
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port
A and no register latch is selected to port B.
RSEL0
RSEL1
60
59
I
I
TEST1–TEST4
THERMAL PAD
29,97,99,100
TEST. Factory test terminal. These terminals should be connected to GND.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
package bottom
TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is
low, TSD is disabled.
TSENA
31
I
VCOIN
75
33
93
92
26
I/O
Capacitance connection for PLL feedback adjustment
Analog power supply voltage
VCCANA
VCCLOG
VCCIF
Logic power supply voltage
Interface power supply voltage
VCCLED
LED driver power supply voltage
WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan
signal can be monitored by turning the constant current output off and protecting the LED
from damage when the scan signal stopped during the constant period designed.
WDTRG
WDCAP
56
30
I
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
between WDCAP and GND. When WDCAP is directly connected to GND, WDT function
is disabled. In this case, WDTRG should be tied to a high or low level.
I/O
Data latch for dot correction. When XDCLAT is high, data on the shift register for dot
correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is
latched. Accordingly, if data on the shift register is changed during XDCLAT high, this new
value is latched (level latch).
XDCLAT
61
I
Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current
output is shut down by WDT or TSD function.
XDOWN1
XDOWN2
XDWN2TST
XENABLE
XGSOUT
55
54
27
66
52
O
O
I
LED disconnection detection output. XDOWN2 is configured as an open collector.
XDOWN2 goes low when an LED disconnection is detected.
TestforXDOWN2. WhenXDWN2TSTislow, XDOWN2goeslow. (Thisterminalisinternally
pulled up with 50 kΩ)
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
validedgeofDCLKafterXENABLEgoeslow. DuringXENABLEhigh, nodataistransferred.
I
Clockoutputforgrayscale. WhenMAG0toMAG2arealllow, theclockwithGSCLKinverted
appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal.
O
Latch. When XLATCH is high, data on the shift register from DIN (port A) goes throughlatch.
When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed
during XLATCH high, this new value is latched (level latch).
XLATCH
63
I
Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,
DOUT0–9 terminals go to a high-impedance state.
XOE
65
51
34
I
O
I
XPOUT
XRST
GSPOL output inverted
Blank (Light off). When XRST is low, all the output of the constant current driver is turned
off. (This terminal is internally pulled up with 50 kΩ)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
†
absolute maximum ratings (see Note 1)
Logic supply voltage, VCCLOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Supply voltage for interface circuit, VCCIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Supply voltage for constant current circuit, VCCLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Analog supply voltage, VCCANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output current (dc), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA
O(LC)
I
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V
Output voltage range, V
, V
, V
, V
O(DOUT) O(DCDOUT) BOUT XPOUT
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V
XGSOUT
Output voltage range, V
Storage temperature range, T
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W
Power dissipation rating at (or above) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2 mW/°C
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16 V
O(OUT)
O(XDOWNn)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
str
A
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GNDLOG terminal.
recommended operating conditions
dc characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Logic supply voltage, VCCLOG
4.5
5
5.5
5.5
V
Supply voltage for interface circuit,
VCCIF
3.0
5
V
Supply voltage for constant current
circuit, VCCLED
4.5
4.5
5
5
5.5
5.5
V
V
Analog power supply, VCCANA
V
= VCCLOG – VCCANA
DIFF1
Voltage between VCC, V
VCCLOG – VCCLED
VCCANA – VCCLED
– 0.3
– 0.3
0
0
0.3
V
DIFF1
DIFF2
V
= GNDLOG – GNDANA
DIFF2
Voltage between GND, V
GNDLOG – GNDLED
GNDANA – GNDLED
0.3
V
V
Voltage applied to constant current
output, V
OUT0 to OUT15 off
15
OUT
High-level input voltage, V
0.8 VCCLOG
GNDLOG
VCCLOG
V
V
IH
Low-level input voltage, V
0.2 VCCLOG
IL
VCCLOG = 4.5 V,
High–level output current, I
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
– 1.0
1.0
OH
mA
VCCLOG = 4.5V,
DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,
BOUT, XGSOUT, XPOUT
Low–level output current, I
OL
VCCLOG = 4.5 V, XDOWN1, XDOWN2
OUT0 to OUT15
5
mA
mA
Constant output current, I
5
80
OLC
Operating free-air temperature range,
T
A
– 20
85
°C
PLL capacitance, C
VCO
1
22
30
µF
kΩ
kΩ
PLL resistor, R
At 16 MHz oscillation
BIAS
PD
PLL resistor, R
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
ac characteristics, VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, T = – 20 to 85°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
At single operation
MIN
TYP
MAX
20
UNIT
DCLK, DCCLK clock frequency, f
f
MHz
DCLK, DCCLK
At cascade operation
15
DCLK, DCCLK pulse duration (high or low level), t /t
wh wl
20
ns
MHz
ns
GSCLK clock frequency, f
GSCLK
8
GSCLK pulse duration (high or low level), t /t
wh wl
40
WDT clock frequency, f
WDT
8
MHz
ns
WDT pulse duration (high or low level), t /t
wh wl
40
30
XLATCH, XDCLAT pulse duration (high level), t
wh
ns
Rise / fall time, t /t
r f
100
ns
DINn – DCLK
5
5
DCDINn – DCCLK
BLANK – GSCLK
XENABLE – DCLK
XLATCH – DCLK
XLATCH – GSCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
10
15
10
10
10
10
15
30
15
Setup time, t
ns
su
DINn – DCLK
15
15
20
30
20
20
20
20
10
DCDINn – DCCLK
XENABLE – DCLK
XLATCH – DCLK
XDCLAT – DCCLK
RSEL – DCLK
RSEL – DCCLK
RSEL – XLATCH
RSEL – XDCLAT
Hold time, t
ns
h
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
electrical characteristics, LEDCHK = L,
MIN/MAX: VCCLOG = VCCANA = VCCLED = 4.5 V to 5.5 V, T = – 20 to 85°C
A
TYP: VCCLOG = VCCANA = VCCLED = 5 V, T = 25°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCLOG
–0.5
DOUTn, DCOUTn, XGSOUT, XPOUT,
V
V
High-level output voltage
V
OH
BOUT
I
= –1 mA
OH
DOUTn, DCOUTn, XGSOUT, XPOUT,
0.5
BOUT = 1 mA
I
OL
XDOWN1, XDOWN2 I
Low-level output voltage
Input current
V
OL
= 5 mA
0.5
OL
= VCCLOG or GNDLOG
I
I
V
IN
± 1
µA
Input signal is static,
TSENA = H, WDCAP = OPEN,
No PLL is used
0.1
1
mA
Input signal is static,
TSENA = H, WDCAP = OPEN,
PLL multiple ratio = 1042
I
Supply current (logic)
mA
LOG
Data transfer,
DCLK = 20 MHz, GSCLK = 8 MHz
No PLL is used
35
45
49
Data transfer,
DCLK = 20 MHz, GSCLK = 15 kHz
PLL multiple ratio = 1042
39
mA
mA
BLANK = L,
BLANK = L,
R
= 1200 Ω
= 600 Ω
= 1200 Ω
=600 Ω
6.5
13
12
20
8
15
20
35
IREF
IREF
IREF
IREF
IREF
I
I
Supply current (analog)
ANA
R
LED turn off, R
LED turn off, R
V
= 1V, R
= 1200Ω
OUT
Supply current (constant current driver)
mA
LED
12
20
40
80
20
35
45
90
All output bits turn on
V
= 1V, R
= 600 Ω
OUT
IREF
All output bits turn on
Constant output current (includes error
between bits)
V
R
= 1V, V
IREF
= 1200Ω
= 1.21 V,
OUT
IREF
I
I
35
70
mA
mA
OLC1
Constant output current (includes error
between bits)
V
R
= 0.7 V, V
= 600 Ω
= 1.21 V,
IREF
OUT
IREF
OLC2
OUT0 to OUT15 (V
= 15 V)
= 15 V)
0.1
1
µA
µA
OUTn
XDOWN1,2 (V
XDOWNn
I
Constant output leakage current
OLK
DOUTn, DCDOUTn
(V = VCCLOG or GND)
1
µA
OUTn
VCCLOG=VCCANA=VCCLED= 5 V,
∆I
OLC
Constant output current error between bit
V
= 1 V,
R
= 600 Ω
± 1% ± 4%
OUT
All output bits turn on
IREF
Changes in constant output current
depend on supply voltage
V
V
= 1V, R
IREF
= 600 Ω,
OUT
IREF
I∆
I∆
± 1
± 1
± 4
± 3
%/V
%/V
OLC1
= 1.21 V
Changes in constant output current
depend on output voltage
V
OUT
V
IREF
= 1 V to 3 V,
= 1.21 V,
R
= 600 Ω,
IREF
1 bit output turn on
OLC2
T
TSD detection temperature
WDT detection temperature
Voltage reference
Junction temperature
No external capacitor
150
5
160
10
170
15
°C
ms
V
tsd
T
wdt
V
BCENA = L, R
IREF
= 590 Ω,
1.21
IREF
Voltage applied to LED disconnection
detection
V
0.2
0.3
0.4
2%
V
LEDDET
R
C
= 22 kΩ, R = 30 kΩ,
PD
= 0.1 µF
BIAS
VCO
P
PLL jitter
0.4%
LLJITTER
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
switching characteristics, C = 15pF,
L
MIN/MAX: VCCLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, T = – 20 to 85°C,
A
TYP: VCCLOG = VCCANA = VCCLED = 5 V, T = 25°C (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
DOUTn, DCDOUTn
MIN
TYP
12
MAX
30
UNIT
t
Rise time
Fall time
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
DOUTn, DCDOUTn
12
110
10
10
130
30
50
20
7
30
ns
r
f
30
t
XGSOUT, BOUT, XPOUT
OUTn (see Figure 1)
OUTn+1 – OUTn
30
ns
45
105
40
BLANK↑ – OUT0
40
BLANK – BOUT
10
GSCLK – OUT0 (see Note 2)
GSCLK – XGSOUT
DCLK – DOUTn
10
15
15
15
10
10
10
20
30
30
30
20
15
20
40
45
t
d
Propagation delay time
ns
DCLK – DCDOUTn
DCCLK – DCDOUTn
XOE↓ – DOUTn (see Note 3)
XOE↑ – DOUTn (see Note 3)
RSEL – DOUTn
45
45
35
25
40
LEDCHK – XDOWN2
1000
NOTES: 2. MAG0 to MAG2 are all low level.
3. Until DOUT will be turned on (drive) or turned off (Hi-Z).
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
51 Ω
V
CC
IREF
OUTn
GND
600 Ω
15pF
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
V
or V
or V
100%
IH
OH
V
IH
IL
90%
10%
50%
0%
V
V
IL
OL
t
t
r
f
t
d
V
or V
or V
100%
V
V
100%
IH
OH
IH
50%
0%
50%
0%
V
IL
OL
IL
t
t
wl
wh
Figure 2. Timing Requirements
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
external resistor, R (connectedbetweenIREFandGND), canflow. Theexternal resistorvalueiscalculated
IREF
using the following equation:
R
(Ω) 38 × 1.21 (V)/I
(A) where both BCENA and DCENA are low.
O(LC)
IREF
Note that more current flows if IREF is connected to GND directly.
constant output current operation
If GSPOL is high, the constant current output turns on the sink constant current if all the gray scale data in the
gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale
clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10 bit gray
scale counter. Then, the output counted corresponding to the gray scale data is turned off (stop to sink constant
current). The gray scale clock can be selected from GSCLK or that generated by internal PLL circuitry. If the
shift register for gray scale is updated during XLATCH high, data on the gray scale data latch is also updated
affecting the constant current output number of the gray scale. Accordingly, during the on-state of the constant
current output, keep the XLATCH to a low level and hold the gray scale data latch.
input/output port and shift register selection
The TLC5910 supplies two parallel input ports such as DIN (10 bits) and DCDIN (6 bits). The DIN and DCDIN
ports also supply DCLK and DCCLK for shift clock, XLATCH and XDCLAT for latch, and DOUT and DCDOUT
for output, respectively. The device has three types of shift register latches, gray scale data, brightness control,
and dot correction. The port and shift register can be selected by RSEL0 and RSEL1. Table 1 shows the
selection using RESL0 and RSEL1. Note that the RSELn setting should be done at DCLK low, (when DPOL
is high, and at DCLK high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and
XDCLAT should be connected to GND.
Table 1. Shift Register Latch Selection
SELECTED SHIFT REGISTER LATCH
PORT A
PORT B
DCDIN, DCCLK, XDCLATCH
Dot correction
RSEL1 RSEL0
DIN, DCLK, XLATCH, DOUT
Gray scale data displayed
Brightness control
DCDOUT
L
L
L
H
L
Dot correction
Dot correction
Dot correction
N/A (inhibit)
Dot correction
H
H
Dot correction (see Note)
N/A (inhibit)
Not connected
H
N/A (inhibit)
NOTE: Zero is output to DOUT6 to DOUT9.
shift register latch for gray scale data
The shift register latch for gray scale data is configured with 16 x 10 bits. The gray scale data, configured with
10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). When
the gray scale data is 1023, the time is longest, and it turns on during time of 1023 clocks from the gray scale
clock. The configuration of the shift register and latch for gray scale data is shown in Figure 3.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
Latch for Gray Scale Data
OUT15
Data
OUT14
OUT1
Data
OUT0
Data
Data
XLATCH
(10 bits)
(10 bits)
(10 bits)
(10 bits)
Shift Register for Gray Scale Data
16th byte
DIN9 MSB
DIN0 LSB
15th byte
DIN9 MSB
DIN0 LSB
2nd byte
DIN9 MSB
DIN0 LSB
1st byte
DIN9 MSB
DIN0 LSB
DCLK
DOUT0 to 9
DIN0 to 9
Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data
shift register latch for brightness control
The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for
brightness control, the division ratio of the gray scale clock can be set and the output current value on constant
current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not
initialized. Data should be written to the shift register latch prior to lighting-on (BLANK=L) when these functions
are used. Also, the latch value for brightness control cannot be rewritten when the constant current output is
turned on. When these functions are not used, the latch value can be set to the default value setting BCENA
to low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain
the compatibility with TLC5901/02/03 family. The configuration of the shift register and the latch for brightness
control is shown below.
Latch for Brightness Control
Gray Scale Clock Division Ratio Data Set
Current Data Adjusted On Constant Current Output
XLATCH
(Note A)
0
0
0
0
1
1
1
1
1
1
MSB
LSB
MSB
LSB
Shift Register for Brightness Control
DCLK
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
DIN9
DOUT0 to 9
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DIN0 to 9
Note A: Indicates default value at BCENA low.
Figure 4. Relationship Between Shift Register and Latch for Brightness Control
shift register latch for dot correction
The shift register latch for dot correction is configured with 16 × 6 bits. Using the shift register latch for dot
correction, the current value on the constant current output can be set individually. When powered up, the latch
data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior
to lighting-on (BLANK=L) when these functions are used. Also, the latch value for dot correction cannot be
rewritten when the constant current output is turned on. When these functions are not used, the latch value can
be set to the default value setting of DCENA to low level (connect to GND). The configuration of the shift register
and the latch for dot correction is shown in Figure 5.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
Latch for Dot Correction
OUT15
Data
OUT14
Data
OUT1
OUT0
Data
Data
XLATCH
(6 bits)
(6 bits)
(6 bits)
(6 bits)
Shift Register for Dot Correction
16th byte
15th byte
2nd byte
1st byte
DCCLK
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DCDOUT0 to 5
DCDIN0 to 5
Using Port B (RSEL0=L or H, RSEL1=L)
Latch for Dot Correction
OUT15
Data
OUT14
Data
OUT1
Data
OUT0
Data
XLATCH
(6 bits)
(6 bits)
(6 bits)
(6 bits)
Shift Register for Dot Correction
16th byte
15th byte
2nd byte
1st byte
DCLK
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DCDIN5 MSB
DCDIN0 LSB
DOUT0 to 5
DIN0 to 5
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between Shift Register and Latch for Dot Correction
write data to shift register latch
The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. At port A, the data is applied
to the DIN data input terminal and clocked into the shift register synchronizing to the rising edge of DCLK after
XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal and clocked into the
shift register synchronizing to the rising edge of DCCLK. The shift register for the gray scale data is configured
with 16 × 10 bits and the shift register for dot correction is configured with 16 x 6 bits resulting in sixteen times
DCLK, and the shift register for brightness control is configured with 1 x 10 bits resulting in one times DCLK.
At number of DCLK input for each case, data can be written into the shift register. In this condition, when
XLATCH at port A or XDCLAT at port B is pulled high, data in the shift register is clocked into latch (data through),
and when XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
brightness control function
By writting data into the brightness control latch, the current on all constant current outputs can be adjusted to
control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control
the variation of brigtness for the total panel system. Furthermore, by writing data into the dot correction latch,
the current on each constant current output can be adjusted.
output current adjustment on all constant current outputs – brightness adjustment between ICs
By using the lower 6 bits of the brightness control latch, the output current can be adjusted to 64 steps. 1 step
of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an external resistor (note
that the current value is lower if the constant current output is corrected using the dot correction function). By
using this function, the brightness control between modules (ICs) can be adjusted sending the desired data
externally even if the ICs are mounted on a print-circuit board. When BCENA is pulled low, output current is set
to 100%.
Table 2. Relative Current Ratio For Total Constant Current Output
CODE
CURRENT RATIO
20
(mA)
80
(mA)
V
IREF
(TYP)
(%)
MSB 000000 LSB
50.8
10.2
40.6
0.61
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
111110
99.2
100
19.8
20.0
79.7
80.0
1.20
1.21
†
111111
BCENA is low.
†
frequency division ratio setting for gray scale clock – panel brightness adjustment
By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16.
If the gray scale clock is set to 16 times the speed (1024×16=16384) of frequency during horizontal scanning
time, the brightness can be adjusted to 16 steps selecting the frequency division ratio. By using this function,
the total panel brightness can be adjusted at once, and it applies to the brightness of day or night circumstances.
When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can
be adjusted (see Table 3).
Table 3. Relative Brightness Ratio For Total Constant Current Output
FREQUENCY
DIVISION RATIO
RELATIVE BRIGHTNESS RATIO
(%)
CODE
†
MSB 0000 LSB
1/1
6.3
.
.
.
.
.
.
.
.
.
.
.
.
1110
1111
1/15
1/16
93.8
100
†
BCENA is low.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
output current adjustment on each constant current output – LED brightness adjustment
By using the 6 bits of the dot correction latch, the output current on each constant current output can be adjusted
to 64 steps. 1 step of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an
external resistor at 111111h of the latched value and the lower 6 bits of the brightness control register. By using
thisfunction, thebrightnessdeviationduetoLEDbrightnessvariationcanbeminimized. WhenDCENAispulled
low, the output current is set to 100% without dot correction.
Table 4. Relative Current Ratio By Constant Current Output
CODE
CURRENT RATIO (%)
I
=40 (mA)
OLC
MSB 000000 LSB
50.8
20.3
.
.
.
.
.
.
.
.
.
.
.
.
111110
99.2
100
39.7
40
†
111111
DCENA is low.
†
clock edge selection
The high speed clock signal is delayed due to the duty ratio change through multiple stages of an IC or through
the module stages shown in Figure 6.
IN
IN
A
OUT
IN
A
A’
OUT
OUT’
IN’
A
A’
OUT
OUT
a) Propagate through multiple stages buffer
with slow falling edge
b) Insert inverter between buffers
Figure 6. Clock Edge Selection
As shown in Figure 6 a), if the falling at the internal buffer is behind the rising, the clock will disappear as multiple
cascade connections are made. To resolve this problem, the duty ratio can be held unchanged using the
connection as shown in Figure 6 b) if the valid clock edge can be selected (arrow in Figure 6). Note that the clock
delay is not avoided even in this case.
The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,
the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL.
Thus the degradation for the duty ratio can be reduced. The relation between each signals is shown in
Table 5.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
clock edge selection (continued)
Table 5. Valid Edge For DCLK and GSCLK
DPOL
DCLK valid edge
DCLK↑
Operation at XENABLE = H
H
L
Pull DCLK to low level
Pull DCLK to high level
DCLK↓
GSPOL
GSCLK valid edge
GSCLK↑
PLL operation
H
L
Synchronize to the high level of DCLK
Synchronize to the low level of DCLK
GSCLK↓
The device supplies XPOUT and XGSOUT output terminals for the cascade operation which invert GSPOL and
GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make easy timing with
GSCLK and XGSOUT.
gray scale clock generation
When MAG<0:2> are all low, the clock input from GSCLK terminal is used as the gray scale clock with no
change, and except for this case internal PLL generates the clock for the gray scale control clock. When using
the PLL, the gray scale clock is generated by adjusting the clock having the same number of pulses as the
multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are keeping the same level). Note that
the reference period is required above 40% of the GSCLK period. The ratio in this case is determined depending
on MAG 0 to MAG 2 as shown in Table 6.
When using PLL, internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, this clock can be utilized
for other devices on the same print-circuit board. Note that the number of ICs connected is limited depending
on the frequency.
Table 6. PLL Multiple Ratio
MAG2
MAG1
MAG0
MULTIPLE RATIO
XGSOUT
L
L
L
L
L
H
L
1 (Signal to control GSCLK by GSPOL)
Inverted GSCLK
8
2 +6(=262)
9
2 +10(=522)
L
H
H
L
10
2
L
H
L
+18(=1042)
+34(=2082)
+66(=4162)
+130(=8322)
+258(=16642)
PLLCLK
11
12
H
H
H
H
2
(Gray scale clock internally generated)
L
H
L
2
13
2
H
H
14
2
H
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
gray scale clock generation (continued)
MAG<0–2>
GSPOL
Except all low level
Except all low level
GSCLK
XGSOUT
PLLCLK
Same number of pulse as ratio
a) GSPOL is low
Same number of pulse as ratio
a) GSPOL is high
Figure 7. Gray Scale Clock Generation
The oscillation frequency bandwidth as referenced for PLL can be set by an external resistor connected
between RBIAS and GND. The relation between the external resistor and oscillation frequency is shown in
Table 7.
Table 7. PLL Oscillation Frequency
RBIAS
22 kΩ
30 kΩ
62 kΩ
120 kΩ
FREQUENCY
13 to 20 MHz
8 to 14 MHz
4 to 9 MHz
3 to 5 MHz
To make PLL stabilization, a resistor and acapacitor connection is required between VCOIN, PDOUT, and GND.
The recommended value is shown in the following table in Figure 8.
PDOUT
VCOIN
C
R
pd
VCO
Recommeded Value
0.1 to 1 µF 22 to 62 kΩ
R
pd
C
VCO
Figure 8. Resistor and Capacitor Connection
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
protection
This device incorporates WDT and TSD functions. If WDT or TSD functions, the constant current output is
stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be
detected immediately. Since the XDOWN1 output is configured as an open collector, outputs of multiple ICs are
brought together.
WDT (watchdog timer)
The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapses after the
signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (signal to control line
displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned
off. This prevents the LED from burning and damage caused by continuous LED turnon at the dynamic scanning
operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately
10 ms without a capacitor, 160 ms with a 1000 pF capacitor, and 1500 ms with a0.01 µF capacitor. During static
operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to
WDTRG). Note that normal operations will resume changing the WDTRG level when WDT functions.
WDT operational time: T (ms) 10 + 0.15 × Cext (pF)
TLC5910
Scan Signal
Cext
WDTRG
WDCAP
1500
160
10
0
0.001
0.01
Cext – External Capacitor – µF
Figure 9. WDT Operational Time and Usage Example
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD starts to function and turns constant current output off,
and XDOWN1 goes low. When TSD is used, TSENA should be pulled high. When TSD is not used, TSENA
should be pulled low. To recover from constant current output off-state to normal operation, the power supply
should be turned off or TSENA should be pulled low once.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
LOD function (LED open detection)
When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a
high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and
XDOWN2 goes low if any LED is disconnected monitoring OUTn terminals to be turned on. This function is
operational for sixteen OUTn terminals individually. To know which constant current output is disconnected, the
level of XDOWN2 is repeatedly checked 16 times from OUT0 to OUT15 turning one constant current output on.
The power supply voltage should be set so the constant current output is applied to above 0.4 V when the LED
is lighting normally. Also, since the time of approximately 1000 ns is required from turning the constant current
output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied.
Table 8 is an example for XDOWN2 output status using four LEDs .
Table 8. XDOWN2 Output Example
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
ON
NG
ON
GOOD
ON
NG
ON
XDOWN2
LOW (by case 2, 4)
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
ON
NG
ON
NG
GOOD
OFF
NG
OFF
GOOD
DETECTION RESULT
XDOWN2
GOOD
GOOD
LOW (by case 2)
LED NUMBER
LED STATUS
OUTn
1
2
3
4
GOOD
OFF
NG
GOOD
OFF
NG
OFF
GOOD
OFF
GOOD
DETECTION RESULT
XDOWN2
GOOD
GOOD
HIGH–IMPEDANCE
noise reduction
concurrent switching noise reduction
Concurrent switching noise has the potential to occur when multiple outputs turn on or off at the same time. To
prevent this noise, the device has a delay output terminal such as XGSOUT and BOUT for GSCLK (gray scale
clock)andBLANK(blankingsignal)respectively. ConnectingtheseoutputstotheGSCLKandBLANKterminals
ofnextstageICallowsdifferencesoftheswitchingtimebetweenICs. WhenGSCLKisoutputtoGSOUTthrough
the device, duty will be changed between input and output. The number of stages to be connected will be limited
depending on frequency.
delay between constant current output
The constant current output has a delay time of approximately 20 ns between outputs. This means
approximately 300 ns delay time exists between OUT0 and OUT15. This time differences by delay reduces the
concurrent switching noise.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
power supply
The followings should be taken into consideration:
VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage
differences between these terminals.
The bypass capacitor should be located between the power supply and GND to eliminate the variation of
power supply voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
thermal pad
The thermal pad should be connected to GND to eliminate the noise influence when it is connected to the bottom
side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with
better thermal conductivity.
power rating – free-air temperature
3.2
4.7
2.4
1.48
0
0
–20
0
25
85
T
A
– Free–Air Temperature – °C
†
VCCLOG=VCCANA=VCCLED=5.0V, I
OLC
= 80mA, I
is typical value.
CC
NOTES: A. IC is mounted on PCB.
3
PCB size: 102 × 76 x 1.6 [mm ], four layers with the internal two layer being plane. The thermal pad is soldered to the PCB pattern
2
of 10 × 10 [mm ]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
B. The thermal impedance will be varied depending on mounting conditions. Since the PZP package established low thermal
impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance.
C. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.
Figure 10. Power Rating
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
PRINCIPLES OF OPERATION
constant output current
90
80
70
60
50
40
30
20
10
0
0.1
1.0
10.0
R
– kΩ
IREF
Conditions: V
= 1.0V, V = 1.21V
IREF
OUT
VIREF(V)
RIREF(k
I
OLC(mA)
38
)
47
IOLC(mA)
RIREF (k
)
NOTE: The brightness control and dot corrected value are 100%. The resistor, R
, should be located as close to the IREF terminal as possible
IREF
to avoid the noise influence.
Figure 11. Current on Constant Current Output vs External Resistor
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DPOL
XOE
XENABLE
1/f
t
t
(XENABLE–DCLK)
(DIN–DCLK)
DCLK
t (XENABLE–DCLK)
h
su
DCLK
t
t
(DCLK)
(DCLK)
su
wl
wh
DIN0
DIN9
D00_A
D90_A
D01_A
D02_A
D0E_A
D0F_A D00_B
D0D_B D0E_B
D9D_B D9E_B
D0F_B
D9F_B
D00_C
D90_C
D01_C
D91_C
D91_A
D92_A
D9E_A
(XLATCH–DCLK)
D9F_A D90_B
t
t
(DIN–DCLK)
t
(XLATCH–DCLK)
su
h
h
XLATCH
t
(XLATCH)
wh
Hi-Z
Hi-Z
DOUT0
DOUT9
D00_A
D90_A
D01_A
D91_A
D0E_A
D9E_A
D0F_A
D00_B
D9F_A
D90_B
t
(XOE↓–DOUT)
t
(DCLK–DOUT)
t
(XOE↑–DOUT)
d
d
d
DPOL
DCLK
DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted with each other).
Figure 12. Timing Diagram (Shift Register for Gray Scale Data)
BCENA
RSEL0
RSEL1
t
(RSEL–XLATCH)
t (RSEL–XLATCH)
h
su
XOE
t
(XOE↓–DOUT)
d
DPOL
XENABLE
t
(RSEL–DCLK)
t
(RSEL–DCLK)
su
su
DCLK
DIN0
D0_A
D9_A
D0_B
D9_B
D0_C
D0_J
D9_J
D0_K
D9_K
D0_L
D9_L
D0_M
D9_M
D0_N
D9_N
D0_O
D9_O
D9_C
DIN9
t
(XLATCH–DCLK)
h
XLATCH
t
(XLATCH)
wh
Default Value “1”
Default Value “1”
Default Value “0”
D<5:0>_A
D<9:6>_A
BCL_0–5
(Brightness Control Latch: Internal Signal)
BCL_6–9
Default Value “0”
t
(DCLK–DOUT)
t (XOE↑–DOUT)
d
d
t
(RSEL–DOUT)
su
Hi-Z
DOUT0
DOUT9
D0_A
D0_C
D9_C
D0_E
D0_F
D0_G
D9_G
D0_H
D0_I
Hi-Z
D9_A
D9_E
D9_F
D9_H
D9_I
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
Figure 13. Timing Diagram (Shift Register for Brightness Control)
DCENA
RSEL0
RSEL1
t
(XENABLE–DCLK)
su
t
(RSEL–XDCLAT)
t
(RSEL–XDCLAT)
h
su
t
(RSEL–DCCLK)
t
(RSEL–DCCLK)
su
su
DCCLK
DCDIN0
DCDIN5
D0_A
D5_A
D0_B
D0_C
D0_J
D5_J
D0_K
D0_L
D5_L
D0_M
D5_M
D0_N
D0_O
D5_O
D5_B
D5_C
D5_K
D5_N
t
(XDCLAT–DCCLK)
h
XDCLAT
t
(XDCLAT)
wh
Dx<15:0>_A
DCL_0–15
Default Value “1”
(Note)
Default Value “1”
(Dot Correction Latch: Internal Signal: 6 bit x 16)
t
(DCCLK–DCDOUT)
d
D0_A
D0_C
D0_E
D0_F
D5_F
D0_G
D0_H
D5_H
D0_I
DCDOUT0
DCDOUT5
D5_A
D5_C
D5_E
D5_G
D5_I
NOTE: Register value is immediately before DCLAT↓.
Figure 14. Timing Diagram (Shift Register for Dot Correction : Using Port B)
RSEL0
RSEL1
XOE
t
(RSEL–XLATCH)
t (RSEL–XLATCH)
h
su
t
(XOE↓–DOUT)
d
DPOL
XENABLE
t
(RSEL–DCLK)
t
(RSEL–DCLK)
su
su
DCLK
DIN0
DIN9
D0_A
D9_A
D0_B
D9_B
D0_C
D0_J
D9_J
D0_K
D9_K
D0_L
D9_L
D0_M
D9_M
D0_N
..
D0_O
D9_O
D9_C
D9_N
.
t
t
(XLATCH–DCLK)
h
XLATCH
t
(DCLK–DOUT)
d
(XLATCH)
D0_C
wh
t
(XOE↑–DOUT)
t
(RSEL–DOUT)
d
su
Hi-Z
DOUT0
DOUT5
D0_A
D0_E
D0_F
D5_F
D0_G
D5_G
D0_H
D0_I
D5_I
Hi-Z
D5_A
D5_C
D5_E
D5_H
t
(XOE↓–DOUT)
d
DOUT
<9:6>
Hi-Z
t
(DCLK–DCDOUT)
d
DCDOUT0
DCDOUT5
D0_A
D0_C
D0_E
D5_E
D0_F
D5_F
D0_G
D5_G
D0_H
D5_H
D0_I
..
D5_A
D5_C
D5_I
DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.
Figure 15. Timing Diagram (Shift Register for Dot Correction : Using Port A)
XLATCH
BLANK
t
(XLATCH–GSCLK)
(BLANK–GSCLK)
su
GSPOL
GSCLK
1/f
GSCLK
t
t
(BLANK–OUT0)
su
d
t
(GSCLK)
wl
1/f
WDT
t
(GSCLK)
wh
WDTRG
(WDTRG)
t
t
(WDTRG)
wl
wh
t
(GSCLK–OUT0)
d
t
wdt
t
(BLANK–OUT0)
t
(GSCLK–OUT0)
OFF
d
d
ON(Note A)
(Note A)
(Note A)
OFF
OFF
OUT0
t
(OUTn+1–OUTn)
d
t
(OUTn+1–OUTn)
d
ON(Note A)
(Note A)
(Note A)
OFF
OFF
OFF
OUT1
(Note A)
(Note A)
OUT15
OFF
OFF
OFF
ON(Note A)
NOTE A: ON or OFF, or ON time is varied depend on the gray scale data and BLANK.
HI–Z
XDOWN1
XDOWN2
(Note B)
(Note B)
(Note B)
t
(GSCLK–XDOWN2)
d
NOTE B: When LED is disconnected.
t
(BLANK–BOUT)
d
BOUT
t
(GSCLK–XGSOUT)
d
XGSOUT
LEDCHK
t
(LEDCHK–XDOWN2)
d
t
(LEDCHK–XDOWN2)
d
GSPOL, GSCLK and XGSOUT can be replaced with signals inverted with each other.
Figure 16. Timing Diagram (Constant Current Output) – MAG0 to MAG2 are all zero
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
M
0,50
75
0,08
0,17
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
0,15
15,80
0°–7°
0,05
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.. The demensions of the
thermal pad are 2 mm x 2 mm. The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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