TLC549MD [TI]
8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8;
| 型号： | TLC549MD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 转换器 |
| 文件： | 总12页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
D OR P PACKAGE
(TOP VIEW)
Microprocessor Peripheral or Standalone
Operation
8-Bit Resolution A/D Converter
Differential Reference Input Voltages
Conversion Time . . . 17 µs Max
REF+
ANALOG IN
REF–
V
CC
1
2
3
4
8
7
6
5
I/O CLOCK
DATA OUT
CS
GND
Total Access and Conversion Cycles Per
Second
– TLC548 . . . up to 45 500
– TLC549 . . . up to 40 000
On-Chip Software-Controllable
Sample-and-Hold Function
Total Unadjusted Error . . . ±0.5 LSB Max
4-MHz Typical Internal System Clock
Wide Supply Range . . . 3 V to 6 V
Low Power Consumption . . . 15 mW Max
Ideal for Cost-Effective, High-Performance
Applications including Battery-Operated
Portable Instrumentation
Pinout and Control Signals Compatible
With the TLC540 and TLC545 8-Bit A/D
Converters and with the TLC1540 10-Bit
A/D Converter
CMOS Technology
description
The TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bit
switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a
microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use
only the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. The
maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of the
TLC549 is specified up to 1.1 MHz.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
TLC548CD
TLC549CD
TLC548CP
TLC549CP
0°C to 70°C
TLC548ID
TLC549ID
TLC548IP
TLC549IP
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
description (continued)
Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz
and requires no external components. The on-chip system clock allows internal device operation to proceed
independentlyof serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired
forawiderangeofsoftwareandhardwarerequirements. TheI/OCLOCKtogetherwiththeinternalsystemclock
allow high-speed data transfer and conversion rates of 45 500 conversions per second for the TLC548, and
40 000 conversions per second for the TLC549.
Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that
can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from
logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit
allows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 µs.
The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I are
characterized for operation from –40°C to 85°C.
functional block diagram
1
REF+
8-Bit
Analog-to
Digital
Converter
(Switched-
Capacitors)
3
2
REF–
8
Sample
and
Hold
8
Output
Data
Regiser
ANALOG IN
8-to-1 Data
Selector
and
4
6
DATA
OUT
Driver
Internal
System
Clock
Control
Logic and
Output Counter
5
7
CS
I/O CLOCK
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
ANALOG IN
ANALOG IN
C = 60 pF TYP
i
(equivalent input
capacitance)
5 MΩ TYP
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
operating sequence
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Don’t
Care
I/O
CLOCK
Access
Cycle C
Access
Cycle B
Sample
Cycle C
t
conv
(see Note A)
Sample
Cycle B
t
su(CS)
t
su(CS)
CS
t
wH(CS)
Hi-Z State
Hi-Z State
DATA
OUT
A7
A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
Conversion Data B
B7
A7
Previous Conversion Data A
LSB
MSB
(see Note B)
MSB
MSB
LSB
MSB
t
en
t
en
NOTES: A. The conversion cycle, which requires 36 internal system clock periods (17 µs maximum), is initiated with the eighth I/O clock pulse
trailing edge after CS goes low for the channel whose address exists in memory at the time.
B. Themostsignificantbit(A7)isautomaticallyplacedontheDATA OUT bus after CS is brought low. Theremainingsevenbits(A6–A0)
are clocked out on the first seven I/O clock falling edges. B7–B0 follows in the same manner.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range at any input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
CC
CC
Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Peak total input current range (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, T (see Note 2): TLC548C, TLC549C . . . . . . . . . . . . . 0°C to 70°C
A
TLC548I, TLC549I . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
NOTES: 1. All voltage values are with respect to the network ground terminal with the REF– and GND terminals connected together, unless
otherwise noted.
2. The D package is not recommended below –40°C.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
recommended operating conditions
TLC548
MIN NOM
TLC549
MIN NOM
UNIT
MAX
MAX
Supply voltage, V
3
2.5
–0.1
1
5
6
3
2.5
–0.1
1
5
6
V
V
CC
Positive reference voltage, V
(see Note 3)
(see Note 3)
, V (see Note 3)
V
V
V
V
+0.1
CC
2.5
V
V
V
V
+0.1
ref+
CC
0
CC
0
CC
2.5
+0.2
Negative reference voltage, V
V
ref–
Differential reference voltage, V
+0.2
V
ref+ ref–
Analog input voltage (see Note 3)
High-level control input voltage, V (for V
CC
CC
CC
CC
0
V
0
V
V
CC
CC
= 4.75 V to 5.5 V)
2
2
V
IH
Low-level control input voltage, V (for V
CC
= 4.75 V to 5.5 V)
0.8
0.8
1.1
V
IL
clock(I/O)
(for V
CC
(for V
Input/output clock frequency, f
Input/output clock high, t
= 4.75 V to 5.5 V)
0
200
200
2.048
0
404
404
MHz
ns
ns
CC
= 4.75 V to 5.5 V)
wH(I/O)
(for V
CC
= 4.75 V to 5.5 V)
CC
Input/output clock low, t
wL(I/O)
Input/output clock transition time, t
t(I/O)
= 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)
100
100
ns
µs
µs
(for V
CC
Duration of CS input high state during conversion, t
wH(CS)
= 4.75 V to 5.5 V) (see Operating Sequence)
17
17
(for V
CC
Setup time, CS low before first I/O CLOCK, t
su(CS)
1.4
1.4
(for V
= 4.75 V to 5.5 V) (see Note 5)
CC
TLC548C, TLC549C
TLC548I, TLC549I
0
70
85
0
70
85
°C
–40
–40
NOTES: 3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied
to REF– convert to all zeros (00000000). For proper operation, the positive reference voltage V , must be at least 1 V greaterthan
ref+
thenegativereferencevoltage,V
falls below 4.75 V.
. Inaddition, unadjustederrorsmayincreaseasthedifferentialreferencevoltage,V
–V ,
ref– ref+
ref–
4. ThisisthetimerequiredfortheI/OCLOCKinputsignaltofallfromV mintoV maxortorisefromV maxtoV min. Inthevicinity
IH IL IL IH
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.
5. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal
system clock after CS↓ before responding to control input signals. This CS setup time is given by the t and t
specifications.
en
su(CS)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
electrical characteristics over recommended operating free-air temperature range,
= V = 4.75 V to 5.5 V, f = 2.048 MHz for TLC548 or 1.1 MHz for TLC549
V
CC
ref+
clock(I/O)
(unless otherwise noted)
†
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
I
I
= –360 µA
2.4
OH
CC
OH
= 3.2 mA
0.4
10
V
OL
CC
OL
= V
CC
= 0,
,
CS at V
O
O
CC
CC
I
High-impedance off-state output current
µA
OZ
CS at V
–10
2.5
–2.5
1
I
I
High-level input current, control inputs
Low-level input current, control inputs
V = V
CC
0.005
–0.005
0.4
µA
µA
IH
I
V = 0
IL
I
Analog input at V
Analog channel on-state input current during sample
cycle
CC
I
µA
I(on)
Analog input at 0 V
CS at 0 V
–0.4
1.8
–1
2.5
3
I
I
Operating supply current
mA
mA
CC
+ I
CC ref
Supply and reference current
V
ref+
= V
1.9
CC
Analog inputs
Input capacitance
7
55
C
pF
i
Control inputs
5
15
operating characteristics over recommended operating free-air temperature range,
= V = 4.75 V to 5.5 V, f = 2.048 MHz for TLC548 or 1.1 MHz for TLC549
V
CC
ref+
clock(I/O)
(unless otherwise noted)
TLC548
TLC549
†
PARAMETER
TEST CONDITIONS
See Note 6
UNIT
†
TYP
MIN
MAX
±0.5
±0.5
±0.5
±0.5
17
MIN TYP
MAX
±0.5
±0.5
±0.5
±0.5
17
E
E
E
Linearity error
LSB
LSB
LSB
LSB
µs
L
Zero-scale error
See Note 7
ZS
FS
Full-scale error
See Note 7
Total unadjusted error
Conversion time
See Note 8
t
See Operating Sequence
See Operating Sequence
8
12
19
conv
Total access and conversion time
12
22
25
µs
I/O
clock
cycles
t
t
Channel acquisition time (sample cycle) See Operating Sequence
4
4
a
Time output data remains
valid after I/O CLOCK↓
10
10
ns
v
t
t
t
t
t
Delay time to data output valid
Output enable time
Output disable time
Data bus rise time
I/O CLOCK↓
200
1.4
400
1.4
ns
µs
ns
ns
ns
d
en
150
300
300
150
300
300
dis
See Figure 1
r(bus)
f(bus)
Data bus fall time
†
All typicals are at V
= 5 V, T = 25°C.
A
CC
NOTES: 6. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
8. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
PARAMETER MEASUREMENT INFORMATION
V
CC
1.4 V
3 kΩ
3 kΩ
Test
Test
Output
Under Test
Point
Output
Under Test
Point
Test
Point
Output
Under Test
3 kΩ
C
L
C
L
(see Note A)
C
(see Note A)
L
(see Note A)
See Note B
See Note B
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
t , t , AND t
LOAD CIRCUIT FOR
AND t
t
d
r
f
PZH
PHZ
t
AND t
PLZ
PZL
V
CC
50%
50%
t
CS
0 V
t
PZL
PLZ
V
CC
Output Waveform 1
(see Note C)
50%
50%
10%
90%
0 V
t
PZH
t
PHZ
V
OH
Output Waveform 2
(see Note C)
0 V
See Note B
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
I/O CLOCK
0.8 V
2.4 V
0.4 V
Output
t
d
t
t
r(bus)
f(bus)
2.4 V
0.8 V
DATA OUT
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
= 50 pF for TLC548 and 100 pF for TLC549; C includes jig capacitance.
NOTES: A.
B.
C
L
L
t = t
en PZH
or t
, t
= t
or t
.
PZL dis PHZ
PLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by
–t /R C
c
t i
(1)
V = V 1–e
(
)
C
S
where
R = R + r
i
t
s
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /512)
(2)
(3)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t /R C
c
t i
V –(V /512) = V 1–e
(
)
S
S
S
and
t (1/2 LSB) = R × C × ln(512)
(4)
(5)
c
t
i
Therefore, with the values given the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(512)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLC548/9
R
r
i
s
V
I
V
S
V
C
1 kΩ MAX
C
i
55 pF MAX
V
V
= Input Voltage at ANALOG IN
= External Driving Source Voltage
I
S
s
R = Source Resistance
r
= Input Resistance
i
C = Input Capacitance
i
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 2. Equivalent Input Circuit Including the Driving Source
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
PRINCIPLES OF OPERATION
The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibility
and access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a
TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion
can be completed in 17 µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for the
TLC548 and in 25 µs for the TLC549.
The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Due to this independence and the internal generation of the system clock, the control hardware and software need
only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In
this manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware and
software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function
allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and
TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple
TLC548 and TLC549 devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the internal system clock after a CS↓ before the transition is recognized. However,
upon a CS rising edge, DATA OUT goes to a high-impedance state within the specified t even though the
dis
su(CS)
rest of the integrated circuitry does not recognize the transition until the specified t
has elapsed. This
techniqueprotectsthedeviceagainstnoisewhenusedinanoisyenvironment. Themostsignificantbit(MSB)
of the previous conversion result initially appears on DATA OUT when CS goes low.
2. The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant
bits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog
input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the
charging of internal capacitors to the level of the analog input voltage.
3. Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth
conversion bits are shifted out on the falling edges of these clock cycles.
4. The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins the
hold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next four
internal system clock cycles, after which the holding function terminates and the conversion is performed
during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must
go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion
of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When
keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise
glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the
microprocessor/controller and the device loses synchronization. When CS is taken high, it must remain high
until the end of conversion. Otherwise, a valid high-to-low transition of CS causes a reset condition, which
aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversion
and not the ongoing conversion.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996
PRINCIPLES OF OPERATION
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample-and-hold function begins sampling
upon the high-to-low transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-low
transition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must be
converted. The TLC548 and TLC549 continue sampling the analog input until the high-to-low transition of the eighth
I/OCLOCKpulse. ThecontrolcircuitryorsoftwarethenimmediatelylowersI/OCLOCKandstartstheholdingfunction
to hold the analog signal at the desired point in time and starts the conversion.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
TLC548CD
TLC548CDR
TLC548CP
TLC548ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
75
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
D
P
D
D
P
D
D
P
D
D
P
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC548IDR
TLC548IP
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC549CD
TLC549CDR
TLC549CP
TLC549ID
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC549IDR
TLC549IP
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLC549IPS
TLC549IPSR
TLC549MP
ACTIVE
ACTIVE
SO
SO
PS
PS
P
8
8
8
80
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
OBSOLETE
PDIP
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
TLC5502-5MJ
1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24, 0.600 INCH, HERMETIC SEALED, CERAMIC, MO-015AA, DIP-24
TI
©2020 ICPDF网 联系我们和版权申明