TLC5502-5M [TI]
8-BIT ANALOG-TO-DIGITAL CONVERTER; 8位模拟数字转换器
| 型号： | TLC5502-5M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总11页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢃ ꢄꢅ ꢆꢃ ꢇ
ꢈ ꢆꢉꢊ ꢀ ꢋꢌꢋ ꢁꢍ ꢎ ꢆꢀꢍ ꢆꢏꢊꢎ ꢊ ꢀꢋꢁ ꢂꢍ ꢌ ꢐꢑ ꢒꢀ ꢑꢒ
SGLS067 − MARCH 1992
• LinEPIC 1-µm CMOS Process
• 8-Bit Resolution
J PACKAGE
(TOP VIEW)
• Differential Linearity Error . . . 0.2% Max
DGTL GND1
ANLG GND
1
24
23
22
21
20
19
18
17
16
15
14
13
• Maximum Conversion Rate . . . 20 MHz Typ
(LSB) D0
DGTL V
ANLG V
REFB
1
2
DD
DD
. . . 10 MHz Min
D1
D2
D3
D4
D5
3
• Analog Input Voltage Range . . . 0 V to V
DD
4
ANLG INPUT
ANLG INPUT
REFM
• TTL Digital I/O Level
5
6
• Low Power Consumption . . . 150 mW Typ
• 5-V Single-Supply Operation
7
D6
REFT
8
(MSB) D7
CLK
DGTL GND2
NC
ANLG V
9
DD
description
DGTL V
2
10
11
12
DD
ANLG GND
NC
The TLC5502-5M is a low-power ultra-high-speed
8-bit analog-to-digital converter that uses the
LinEPIC CMOS process. It utilizes the full parallel comparison (flash method) for high-speed conversion.
Because of such high-speed capability, the TLC5502-5M is suitable for motor control, high-speed signal
NC−No internal connection
processing, and video or radar signal processing.
Separate analog and digital supply pins are provided to reduce coupling between the high-speed digital
switching sections and the lower-frequency analog signal comparators. This pin partitioning minimizes crosstalk
and unwanted spurious signals.
The TLC5502-5M is characterized for operation from −55°C to 125°C.
During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit,
unused inputs should always be connected to an appropriated logic voltage level, preferably either V
CC
or ground. Specific guidelines
for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies available from Texas Instruments.
LinEPIC is a trademark of Texas Instruments Incorporated.
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ꢞ ꢘꢖ ꢗꢘ ꢙ ꢚ ꢜ ꢘ ꢝ ꢡꢠ ꢞ ꢕ ꢗꢕ ꢞ ꢛ ꢜ ꢕꢘ ꢖꢝ ꢡꢠ ꢙ ꢜꢦ ꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢀꢠꢧ ꢛ ꢝ ꢊꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ ꢝꢜ ꢛꢖ ꢤꢛꢙ ꢤ
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Copyright 1992, Texas Instruments Incorporated
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS067 − MARCH 1992
functional block diagram
10
CLK
19, 20
17
ANLG INPUT
REFT
1
2
EN
R1
9
8
7
6
5
4
3
2
D7 (MSB)
D6
R
R
127
128
D5
Latch
and
Buffer
255-to-8
Encoder
D4
R/2
R/2
18
REFM
D3
D2
254
255
D1
R
D0 (LSB)
R
R2
21
REFB
operating sequence
CLK
Sample
N
Sample
N + 1
Sample
N + 2
ANALOG
INPUT
t
d
Data
N−1
Data
N
Data
N+1
D0−D7
Following the operating sequence above, the rising edge of the clock samples the analog input (sample N) at
time t and latches sample N−1 at the output. Sample N is encoded to eight digital lines on the next falling edge
N
of the clock and then the following high clock level latches these eight bits to the outputs (with a delay t ) and
d
acquires sample N + 1. Conversion is completed in one clock cycle and continues the sequence for the next
cycle.
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SGLS067 − MARCH 1992
equivalents of analog input circuit
ANALOG INPUT
SAMPLE AND HOLD
S
ANLG
H
V
DD
REFT
ANLG INPUT
Out 1
ANLG
C
C
Sample-
INPUT
and-
†
mR
V
†
mR
Hold
Circuit
‡
ref′
REFT
REFB
Out 2
(256−m)R
ANLG
GND
(256−m)R
REFB
†
‡
m = comparator position along the resistor string
M
ƪ
ƫ
ƪ1 * ƫ ) V
V
Ȁ + V
* V
ref
refT refB
refB
256
equivalent of digital input circuit
DGTL V
DD
CLK
ANLG
GND
DGTL
GND
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SGLS067 − MARCH 1992
FUNCTION TABLE
ANALOG INPUT
VOLTAGE
DIGITAL OUTPUT
CODE
STEP
†
0
1
.
.
.
0.000 V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0.019 V
H
.
.
.
.
.
.
127
128
129
.
.
.
2.413 V
2.432 V
2.451 V
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
H
H
H
.
.
.
.
.
.
254
4.826 V
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
255
4.845 V
H
†
These values are based on the assumption that V
and V
have
been adjusted so that the voltage at the transition from digital 0 to 1
refB
refT
(V ) is 0 V and the transition to full scale (V ) is 4.8545 V. 1 LSB
ZT
= 19 mV.
FT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, ANLG V
Supply voltage range, DGTL V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
DD
DD
Input voltage range at CLK, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DGTL V
+ 0.3 V
+ 0.5 V
+ 0.5 V
I
DD
DD
DD
Input voltage range at analog input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to ANLG V
I
Analog reference voltage range, V
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to ANLG V
ref
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: Voltages at analog inputs and ANLG V
are with respect to the ANLG GND terminals. Voltages at the digital outputs and DGTL V
DD
DD
are with respect to the DGTL GND terminals.
recommended operating conditions
MIN NOM
MAX
5.25
5.25
UNIT
Supply voltage, ANLG V
Supply voltage, DGTL V
4.75
4.75
2
5
5
V
V
V
V
V
DD
DD
High-level input voltage, V , CLK
IH
Low-level input voltage V , CLK
IL
0.8
5
Input voltage at analog input, V
0
I
ANLG
Analog reference voltage (top side), V
refT
V
V
V
DD
V
* V
refT
refB
Analog reference voltage (midpoint), V
refM
2
Analog reference voltage (bottom side), V
refB
0
V
V
Differential reference voltage, V
refT
− V
refB
5
High-level output current, I
−400
4
µA
mA
ns
°C
OH
Low-level output current, I
OL
Clock pulse duration, high or low, t
wH
Operating free-air temperature, T
or t
wL
50
−55
125
A
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SGLS067 − MARCH 1992
electrical characteristics over operating supply voltage range, T = 25°C
A
PARAMETER
High-level output voltage
Low-level output voltage
Analog input current
TEST CONDITIONS
= −400 µA
MIN
TYP
MAX
UNIT
V
V
V
I
I
2.4
OH
OL
OH
= 4 mA
0.4
V
OL
I
I
I
I
I
V = 0 to 5 V,
f = 10 MHz
clock
0.5
mA
µA
µA
mA
mA
pF
I
I
Digitial high-level input current
Digital low-level input current
Reference current
V = 5 V
1
−1
IH
I
V = 0
IL
I
V
= 0
−10
10
−20
20
refB
refT
refB
Reference current
V
= 5 V
refT
C
Analog input capacitance
Supply current
50
i
I
f
= 10 MHz
30
60
mA
DD
clock
operating characteristics over operating supply voltage range, T = 25°C
A
PARAMETER
Maximum conversion rate
Linearity error, differential
Linearity error, best straight line
Signal to noise ratio
TEST CONDITIONS
MIN
TYP
20
MAX
UNIT
f
10
MHz
c(max)
E
V = 0 to 5 V
0.1
0.2 %FSR
0.4 %FSR
dB
D
L
I
E
V = 0 to 5 V
I
†
SNR
THD
BW
f
= 9.9 MHz,
f
IN
= 97 kHz,
−50
51
5
clock
BW = 5 MHz
= 10 MHz
Total harmonic distortion
Analog input bandwidth (3 dB)
Delay time, digital output
dB
f
MHz
clock
= 15 pF
t
d
C
10
30
ns
L
†
SNR is total noise without THD.
timing diagram
t
t
wL
wH
1.4 V
CLK
Sample
N
Sample
N+1
Sample
N+2
Analog
Input
t
d
Data
N−1
Data
N
Data
N+1
D0−D7
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SGLS067 − MARCH 1992
TYPICAL CHARACTERISTICS
255
254
11111111
11111110
See Note A
11111101
253
V
FS
10000001
10000000
129
128
127
V
ZT
V
ZS
=
V
FT
V
FS
=
+ 1/2 LSB
− 1/2 LSB
01111111
V
ZS
00000010
00000001
00000000
2
1
0
V − Analog Input Voltage − V
I
NOTE A: This curve is based on the assumption that V
refB
and V have been adjusted so that the voltage at the transition from digital 0 to 1
refT
(V ) is 0 and the transition to full scale (V ) is 4.8545 V. 1 LSB = 19 mV.
ZT
FT
Figure 1. Ideal Conversion Characteristics
SUPPLY CURRENT
vs
OPERATING FREE-AIR TEMPERATURE
REFERENCE CURRENT
vs
OPERATING FREE-AIR TEMPERATURE
40
35
30
25
20
15
10
14
12
10
8
V
= 5 V
= 5 V
= 0
DD
V
= 5 V
= 8 MHz
DD
V
V
refT
f
clock
refB
6
4
2
5
0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
T
A
− Operating Free-Air Temperature − °C
T
A
− Operating Free-Air Temperature − °C
Figure 2
Figure 3
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SGLS067 − MARCH 1992
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
OPERATING FREE-AIR TEMPERATURE
OPERATING FREE-AIR TEMPERATURE
0
− 10
− 20
− 30
− 40
− 50
− 60
0
− 10
− 20
− 30
− 40
V
= 5 V
= 1.25 MHz
= 10 MHz
DD
V
= 5 V
DD
= 100 kHz
f
f
IN
clock
f
f
IN
clock
= 10 MHz
− 50
− 60
− 70
− 80
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
T
A
− Operating Free-Air Temperature − °C
T
A
− Operating Free-Air Temperature − °C
Figure 4
Figure 5
DIFFERENTIAL LINEARITY ERROR
vs
DIFFERENTIAL LINEARITY ERROR
vs
OPERATING FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
0.4
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1.5
0.1
0.05
0
0.1
0.05
0
T
= 25°C
V
= 5 V
A
I
DD
V = 0 to 5 V
V = 0 to 5 V
I
4.75
4.875
V
5.0
5.125
5.25
0
10
20
30
40
50
60
70
− Supply Voltage − V
T
− Operating Free-Air Temperature − °C
DD
A
Figure 6
Figure 7
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SGLS067 − MARCH 1992
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0
− 10
− 20
− 30
− 40
0
− 10
− 20
− 30
− 40
T
f
= 25°C
T
= 25°C
= 100 kHz
= 10 MHz
A
IN
A
= 97 kHz
f
f
IN
clock
f
= 9.9 MHz
clock
− 50
− 60
− 50
− 60
4.75
4.875
5.0
5.125
5.25
4.75
4.875
5.0
5.125
5.25
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
Figure 8
Figure 9
PARAMETER MEASUREMENT INFORMATION
Measurement
Point
5 V
R
= 2 kΩ
L
To
Digital
Output
(D5)
C
= 15 pF
L
Figure 10. Load Circuit
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SGLS067 − MARCH 1992
APPLICATION INFORMATION
The following design recommendations will benefit the TLC5502-5M user:
1. External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
2. RF breadboarding or PCB techniques should be used throughout the evaluation and production process.
Breadboards should be copper clad for bench evaluation.
3. Since the ANLG GND, DGTL GND1, and DGTL GND2 are not connected internally, these pins need to be
connected externally. With breadboards, these ground lines should be connected through separate leads
with proper supply bypassing. A good method to use is a separate twisted-pair cable for the supply lines
to minimize noise pickup. An analog and digital ground plane should be used on PCB layouts.
4. Since the ANLG V , DGTL V 1, and DGTL V 2 are not connected internally, these pins also need to
DD
DD
DD
be connected externally. To connect ANLG V , DGTL V 1, and DGTL V 2, a 50-Ω resistor should be
DD
DD
DD
placed in series with DGTL V 1 and then a 0.1-µF capacitor to ground before being connected to
DD
ANLG V
and DGTL V
.
DD
DD2
5. ANLG V
to ANLG GND, DGTL V 1 to DGTL GND1, and DGTL V 2 to DGTL GND2 should be
DD DD
DD
decoupled with 1-µF and 0.01-µF capacitors, respectively, as close as possible to the appropriate device
pins. A ceramic-chip capacitor is recommended for the 0.01-µF capacitor. Care should be exercised to
assure a solid noise free ground connection for the analog and digital grounds.
6. The no connection (NC) pins on the J package should be connected to ground.
7. ANLG V , ANLG GND, and ANLG INPUT should be shielded from the higher-frequency pins, CLK and
DD
D0−D7. If possible, ANLG GND traces should be placed on both sides of the ANLG INPUT traces on the
PCB.
8. In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Ω or less within the analog frequency range of interest.
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SGLS067 − MARCH 1992
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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Applications
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Medical
Amplifiers
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Clocks and Timers
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amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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