TLC0834I [TI]
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL; 8位模拟数字转换器带串行控制
| 型号： | TLC0834I |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| 文件： | 总15页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
TLC0834 . . . D OR N PACKAGE
(TOP VIEW)
8-Bit Resolution
Easy Microprocessor Interface or
Stand-Alone Operation
NC
CS
V
DI
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
Operates Ratiometrically or With 5-V
Reference
CH0
CLK
4- or 8-Channel Multiplexer Options With
Address Logic
CH1
CH2
SARS
DO
Input Range 0 to 5 V With Single 5-V Supply
Remote Operation With Serial Data Link
CH3
REF
DGTL GND
ANLG GND
8
Inputs and Outputs Are Compatible With
TTL and MOS
TLC0838 . . . DW OR N PACKAGE
(TOP VIEW)
Conversion Time of 32 µs at
f
= 250 kHz
clock
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
V
CC
NC
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Functionally Equivalent to the ADC0834
and ADC0838 Without the Internal Zener
Regulator Network
Total Unadjusted Error . . . ±1 LSB
description
These
approximation analog-to-digital converters, each
with an input-configurable multichannel
devices
are
8-bit
successive-
DGTL GND
multiplexer and serial input/output. The serial
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing with most
popular microprocessors is readily available from
the factory.
The TLC0834 (4-channel) and TLC0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TLC0834C and TLC0838C are characterized for operation from 0°C to 70°C. The TLC0834I and TLC0838I
are characterized for operation from –40°C to 85°C. The TLC0834Q is characterized for operation from –40°C
to 125°C.
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(DW)
T
A
PLASTIC DIP
(N)
0°C to 70°C
–40°C to 85°C
–40°C to 125°C
TLC0834CD
TLC0834ID
—
TLC0838CDW
TLC0838IDW
—
TLC0834CN TLC0838CN
TLC0834IN
TLC0834QN
TLC0838IN
—
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Start
Flip-Flop
16
CS
18
CLK
18
CLK
CS
15
17
DI
R
D
SARS
(see Note A)
S
R
5-Bit Shift Register
CLK
START
SGL\DIF
ODD\EVEN
SELECT0 SELECT1
TLC0838
Only
SE
To Internal
Circuits
CLK
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
TLC0834
S
R
Analog
MUX
Time
Delay
TLC0838
18
EN
CS
Comparator
Bits 0–7
CS
18
CS
18
CS
18
CS
18
EN
R
R
R
CLK
12
CLK
REF
SAR
14
Ladder
and
Decoder
EOC
Logic
DO
9-Bit
Shift
Register
Bits 0–7
Bit 1
and
D
Latch
LSB
First
MSB
First
One
Shot
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
B: Terminal numbers shown are for the DW or N package.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
functional description
The TLC0834 and TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. Thecomparatoroutputindicateswhethertheanaloginputisgreaterthanorlessthantheresistive-ladder
output. Astheconversionproceeds, conversiondataissimultaneouslyoutputfromDO, withthemostsignificant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLC0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go tothehigh-impedancestate. Ifanotherconversionisdesired, CSmustmakeahigh-to-lowtransitionfollowed
by address information.
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
sequence of operation
TLC0834
1
2
3
4
5
6
7
10
11
12
13
14
15
18
19
20
21
CLK
t
conv
CS
t
su
+Sign
Bit
SELECT
Bit 1
Start
Bit SGL ODD
Don’t Care
DI
DIF EVEN
1
Hi-Z
SARS
Mux Settling Time
MSB-First Data
LSB-First Data
Hi-Z
Hi-Z
MSB
LSB
MSB
7
DO
7
6
2
1
0
1
2
6
TLC0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
ODD/EVEN
CHANNEL NUMBER
SELECT BIT 1
CH0 CH1 CH2 CH3
SGL/DIF
+
–
–
+
L
L
L
L
L
L
H
H
L
H
L
+
–
–
+
H
+
H
H
H
H
L
L
H
H
L
H
L
+
+
+
H
H = high level, L = low level, – or + = terminal polarity for the selected
input channel
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
sequence of operation
TLC0838
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLK
t
t
su
conv
CS
Mux
Addressing
t
su
+
Sign
Bit
SEL SEL
Start
Bit
1
Bit
0
Bit SGL ODD
Don’t Care
DI
DIF EVEN
1
0
Hi-Z
Hi-Z
SARS
SE
LSB-First Data
MSB-First Data
Hi-Z
Hi-Z
LSB
0
MSB
7
MSB
DO
7
6
2
1
1
2
3
4
5
6
SE Used to Control LSB-First Data
SE
Mux Settling
Time
MSB-First Data
LSB Held
LSB
LSB-First Data
MSB
7
DO
MSB
7
6
2
1
0
1
2
3
4
5
6
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
TLC0838 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SELECTED CHANNEL NUMBER
SELECT
0
1
2
3
COM
SGL/DIF
ODD/EVEN
1
L
0
L
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
L
L
L
L
+
–
+
–
L
H
L
+
–
+
–
+
L
L
H
H
L
+
–
+
–
+
L
L
H
L
+
–
+
–
+
L
H
H
H
H
L
+
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
–
–
–
–
–
–
–
–
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
+
L
H
L
+
H
H
+
H
+
H = high level, L = low level, – or + = polarity of external input
absolute maximum ratings over recommended operating free-air temperature range (unless
†
otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.5
2
5
5.5
CC
High-level input voltage, V
V
IH
Low-level input voltage, V
0.8
600
V
IL
Clock frequency, f
10
40%
220
350
90
kHz
clock
Clock duty cycle (see Note 2)
Pulse duration, CS high, t
60%
ns
ns
ns
wH(CS)
Setup time, CS low, SE low, or data valid before CLK↑, t (see Figures 1 and 2)
su
Hold time, data valid after CLK↑, t (see Figure 1)
h
C suffix
I suffix
0
70
85
Operating free-air temperature, T
°C
A
–40
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature, V
clock
= 5 V,
CC
f
= 250 kHz (unless otherwise noted)
digital section
C SUFFIX
I SUFFIX
†
PARAMETER
UNIT
TEST CONDITIONS
‡
TYP
‡
TYP
MIN
2.8
MAX
MIN
2.4
MAX
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 5.25 V,
I
I
I
= –360 µA
= –10 µA
= 1.6 mA
= 5 V
CC
CC
CC
OH
OH
OL
V
V
High-level output voltage
V
OH
4.6
4.5
Low-level output voltage
0.34
1
0.4
1
V
OL
I
I
I
I
High-level input current
= 5 V
= 0
V
0.005
–0.005
–24
0.005
–0.005
–24
26
µA
µA
mA
mA
IH
IH
IH
IL
Low-level input current
V
= 0
–1
–1
IL
IL
High-level output (source) current
Low-level output (sink) current
= 0,
T
A
= 25°C
= 25°C
= 25°C
= 25°C
–6.5
8
–6.5
8
OH
OL
OH
OL
= V
,
T
A
26
CC
= 5 V,
= 0,
T
A
0.01
3
0.01
–0.01
5
3
High-impedance-state output
current (DO or SARS)
O
O
I
µA
OZ
T
A
–0.01
–3
–3
C
C
Input capacitance
Output capacitance
pF
pF
i
5
o
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
All typical values are at V = 5 V, T = 25°C.
CC
A
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
analog and converter section
†
‡
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
–0.05
to
V
IC
Common-mode input voltage
See Note 3
V
V
+0.05
CC
On channel
Off channel
On channel
Off channel
V = 5 V
1
I
V = 0
I
–1
–1
1
I
Standby input current (see Note 4)
Input resistance to REF
µA
kΩ
I(stdby)
V = 0
I
V = 5 V
I
r
1.3
2.4
5.9
i(REF)
total device
‡
PARAMETER
MIN TYP
MAX
UNIT
I
Supply current
0.6
1.25
mA
CC
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at V
= 5 V, T = 25°C.
A
CC
NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog input voltages one diode drop above V .Care must be taken during
CC
levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause the input
testing at low V
CC
diodeto conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed thesupply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 5-V input range requires a minimum V
4.950 V for all variations of temperature and load.
of
CC
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state condition.
operating characteristics, V
(unless otherwise noted)
= 5 V, f
= 250 kHz, t = t = 20 ns, T = 25°C
clock r f A
CC
§
PARAMETER
Supply-voltage variation error
TEST CONDITIONS
MIN
TYP
MAX
±1/4
±1
UNIT
LSB
LSB
LSB
V
= 4.75 V to 5.25 V
±1/16
CC
Total unadjusted error (see Note 5)
Common-mode error
V
= 5 V,
T
= MIN to MAX
ref
Differential mode
A
±1/16
±1/4
1500
600
MSB-first data
LSB-first data
Propagation delay time, output
data after CLK↓ (see Note 6) (see Figure 2)
t
pd
C
= 100pF
ns
ns
L
C
C
= 10 pF,
R
R
= 10 kΩ
= 2 kΩ
250
L
L
L
L
t
Output disable time, DO or SARS after CS↑ (see Figure 3)
dis
= 100 pF,
500
clock
periods
t
Conversion time (multiplexer-addressing time not included)
8
conv
§
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
CLK
CS
50%
50%
GND
t
su
t
su
V
CC
0.4 V
2 V
GND
t
t
h
h
V
CC
2 V
DI
0.4 V
0.4 V
GND
Figure 1. Data-Input Timing
V
CC
50%
50%
CLK
DO
GND
t
pd
t
pd
V
CC
50%
50%
GND
t
su
V
CC
50%
SE
GND
Figure 2. Data-Output Timing
2–9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
S1
S2
R
L
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
t
r
t
r
V
V
CC
CC
90%
90%
10%
50%
CS
CS
50%
10%
GND
GND
t
t
dis
dis
V
CC
–V
CC
S1 Closed
S2 Open
90%
S1 Open
S2 Closed
DO and SARS
DO and SARS
10%
GND
GND
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
2–10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
LINEARITY ERROR
vs
REFERENCE VOLTAGE
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
1.5
16
14
V
= 5 V
= 250 kHz
V
I(+)
= V
= 0 V
I(–)
CC
f
clock
= 25°C
T
A
1.25
12
1
10
8
0.75
6
4
0.5
0.25
2
0
0
0
1
2
3
4
5
0.01
0.1
1
10
V
ref –
Reference Voltage – V
V
ref
– Reference Voltage – V
Figure 5
Figure 4
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
LINEARITY ERROR
vs
CLOCK FREQUENCY
0.5
3
V
= 5 V
= 5 V
ref
V
= 5 V
= 250 kHz
ref
V
CC
f
clock
2.5
0.45
2
0.4
1.5
85°C
0.35
1
25°C
0.3
–40°C
0.5
0.25
0
– 50
– 25
0
25
50
75
100
0
100
f
200
300
400
500
600
T
A
– Free-Air Tempertature – °C
– Clock Frequency – kHz
clock
Figure 6
Figure 7
2–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
CLOCK FREQUENCY
FREE-AIR TEMPERATURE
1.5
1.5
f
= 250 kHz
clock
CS = High
V
T
A
= 5 V
= 25°C
CC
V
= 5.5 V
= 5 V
CC
1
V
CC
1
0.5
V
CC
= 4.5 V
0
0.5
– 50
0
100
f
200
300
400
500
– 25
T
0
25
50
75
100
– Clock Frequency – kHz
– Free-Air Temperature — °C
clock
A
Figure 8
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
25
V
CC
= 5 V
20
15
10
5
I
(V = 5 V)
OL OL
–I = 0 V)
OH OH
(V
–I = 2.4 V)
(V
OH OH
I
(V
= 0.4 V)
0
OL OL
0
–50
–25
25
50
75
100
T
A
– Free-Air Temperature – °C
Figure 10
2–12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
1
0.5
0
V
= 5 V
ref
= 25°C
–0.5
–1
T
A
FCLK = 250 kHz
= 5 V
V
DD
0
32
64
96
128
160
192
224
256
Output Code
Figure 11. Differential Nonlinearity With Output Code
1
V
T
A
= 5 V
ref
= 25°C
FCLK = 250 kHz
= 5 V
0.5
0
V
DD
–0.5
–1
0
32
64
96
128
160
192
224
256
Output Code
Figure 12. Integral Nonlinearity With Output Code
1
V
T
A
= 5 V
ref
= 25°C
0.5
0
FCLK = 250 kHz
= 5 V
V
DD
–0.5
–1
0
32
64
96
128
160
192
224
256
Output Code
Figure 13. Total Unadjusted Error With Output Code
2–13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–14
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