TL751M12QKVURQ1 [TI]
AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS; 汽车低压差稳压器
| 型号： | TL751M12QKVURQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS |
| 文件： | 总23页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS
Check for Samples: TL750Mxx-Q1, TL751Mxx-Q1
1
FEATURES
•
Qualified for Automotive Applications
Low Dropout Voltage, Less Than 0.6 V at
750 mA
Low Quiescent Current
TTL- and CMOS-Compatible Enable on
TL751M Series
•
•
•
•
Load-Dump Protection
Overvoltage Protection
Internal Thermal Overload Protection
Internal Overcurrent-Limiting Circuitry
•
•
•
DESCRIPTION
The TL750M and TL751M series are low-dropout positive voltage regulators specifically designed for automotive
applications. The TL750M and TL751M series incorporate onboard overvoltage and current-limiting protection
circuitry to protect the devices and the regulated system. Both series are fully protected against load-dump and
reverse-battery conditions. Load-dump protection is up to a maximum of 60 V at the input of the device. Low
quiescent current, even during full-load conditions, makes the TL750M and TL751M series ideal for use in
applications that are permanently connected to the vehicle battery.
The TL750M and TL751M series offers 5-V, 8-V, and 12-V options. The TL751M series has the addition of an
enable (ENABLE) input. The ENABLE input gives complete control over power up, allowing sequential power up
or shutdown. When ENABLE is high, the regulator output is placed in the high-impedance state. The ENABLE
input is TTL and CMOS compatible.
The TL750Mxx and TL751Mxx are characterized for operation over the virtual junction temperature range –40°C
to 125°C.
AVAILABLE OPTIONS(1)
VO
NOM (V)
TJ
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TL750M05Q1
TO-263-3 – KTT
Reel of 500
Reel of 2500
Reel of 500
Reel of 2500
Reel of 500
Reel of 2500
Reel of 500
Reel of 2500
Reel of 500
Reel of 2500
Reel of 500
Reel of 2500
TL750M05QKTTRQ1
TL750M05QKVURQ1
TL750M08QKTTRQ1
TL750M08QKVURQ1
TL750M12QKTTRQ1
TL750M12QKVURQ1
TL751M05QKTTRQ1
TL751M05QKVURQ1
TL751M08QKTTRQ1
TL751M08QKVURQ1
TL751M12QKTTRQ1
TL751M12QKVURQ1
5 V
TO-252-3 – KVU
TO-263-3 – KTT
TO-252-3 – KVU
TO-263-3 – KTT
TO-252-3 – KVU
TO-263-5 – KTT
TO-252-5 – KVU
TO-263-5 – KTT
TO-252-5 – KVU
TO-263-5 – KTT
TO-252-5 – KVU
750M05Q
TL750M08Q1
750M08Q
8 V
12 V
5 V
TL750M12Q1
750M12Q
–40°C to 125°C
TL751M05Q1
751M05Q
TL751M08Q1
751M08Q
8 V
TL751M12Q1
751M12Q
12 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TL750Mxx-Q1, TL751Mxx-Q1
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
www.ti.com
TL750M
KTT (TO-263-3) PACKAGE
(TOP VIEW)
TL751M
KTT (TO-263-5) PACKAGE
(TOP VIEW)
NC
OUTPUT
COMMON
INPUT
OUTPUT
COMMOM
INPUT
ENABLE
TL750M
KVU (TO-252-3) PACKAGE
(TOP VIEW)
TL751M
KVU (TO-252-5) PACKAGE
(TOP VIEW)
NC
OUTPUT
COMMON
INPUT
OUTPUT
COMMON
INPUT
ENABLE
NOTE: The COMMON terminal is in electrical contact with the mounting base.
NC – No internal connection
TL751Mxx FUNCTIONAL BLOCK DIAGRAM
INPUT
ENABLE
Enable
Current
Limiting
28 V
_
+
OUTPUT
Bandgap
Overvoltage/
Thermal
Shutdown
COMMON
2
Copyright © 2005–2011, Texas Instruments Incorporated
TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
Continuous input voltage
26 V
60 V
Transient input voltage (see Figure 4)
Continuous reverse input voltage
–15 V
Transient reverse input voltage
t = 100 ms
–50 V
KTT package (3 pin)
KTT package (5 pin)
KVU package
26.9°C/W
26.5°C/W
38.6°C/W
–40°C to 150°C
–65°C to 150°C
θJA
Package thermal impedance(2) (3)
TJ
Virtual junction temperature range
Storage temperature range
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. Due to variation in
individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power
levels slightly above or below the rated dissipation.
(3) The package thermal impedance is calculated in accordance with JESD 51.
THERMAL INFORMATION
TL750M05
THERMAL METRIC(1)
KTT
3 PINS
27.5
43.2
17.3
2.8
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
ψJB
9.3
θJCbot
0.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
6
MAX
26
UNIT
TL75xM05
TL75xM08
TL75xM12
TL751Mxx
TL751Mxx
TL75xMxx
TL75xMxx
VI
Input voltage
9
26
V
13
2
26
VIH
VIL
IO
High-level ENABLE input voltage
Low-level ENABLE input voltage
Output current
15
V
V
0
0.8
750
125
mA
°C
TJ
Operating virtual junction temperature
–40
Copyright © 2005–2011, Texas Instruments Incorporated
3
TL750Mxx-Q1, TL751Mxx-Q1
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
www.ti.com
TL751Mxx ELECTRICAL CHARACTERISTICS
VI = 14 V, IO = 300 mA, TJ = 25°C
TL751Mxx
TYP
PARAMETER
UNIT
Response time, ENABLE to output (start-up)
50
µs
TL750M05/TL751M05 ELECTRICAL CHARACTERISTICS
VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M05, TJ = –40°C to 125°C (unless otherwise noted)(1)
TL750M05
TL751M05
PARAMETER
TEST CONDITIONS
UNIT
MIN
4.85
TYP
5
MAX
5.15
25
Output voltage
Line regulation
VI = 6 V to 26 V
V
VI = 9 V to 16 V,
VI = 6 V to 26 V,
VI = 8 V to 18 V,
IO = 5 mA to 750 mA
IO = 250 mA
IO = 250 mA
f = 120 Hz
10
12
55
20
mV
50
Power-supply ripple rejection
Load regulation
dB
50
0.5
0.65
75
mV
IO = 500 mA, TJ = 25°C
IO = 750 mA, TJ = 25°C
IO = 750 mA
Dropout voltage(2)
V
60
Current consumption
Iq = II – IO
mA
IO = 10 mA
5
Shutdown current (TL751M05 only)
ENABLE VIH ≥ 2 V
200
µA
(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be
taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor
on the output, with equivalent series resistance within the guidelines shown in Figure 4.
(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V.
TL750M08/TL751M08 ELECTRICAL CHARACTERISTICS
VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M08, TJ = –40°C to 125°C (unless otherwise noted)(1)
TL750M08
TL751M08
PARAMETER
TEST CONDITIONS
UNIT
MIN
7.76
TYP
8
MAX
8.24
40
Output voltage
Line regulation
VI = 6 V to 26 V
V
VI = 10 V to 17 V,
VI = 9 V to 26 V,
IO = 250 mA
IO = 250 mA
f = 120 Hz
12
15
55
24
mV
68
Power-supply ripple rejection
Load regulation
VI = 11 V to 21 V,
IO = 5 mA to 750 mA
dB
80
0.5
0.65
75
mV
IO = 500 mA, TJ = 25°C
IO = 750 mA, TJ = 25°C
IO = 750 mA, TJ = 25°C
IO = 10 mA
Dropout voltage(2)
V
60
Current consumption
Iq = II – IO
mA
5
Shutdown current (TL751M08 only)
ENABLE VIH ≥ 2 V
200
µA
(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be
taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor
on the output, with equivalent series resistance within the guidelines shown in Figure 4.
(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V.
4
Copyright © 2005–2011, Texas Instruments Incorporated
TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
TL750M12/TL751M12 ELECTRICAL CHARACTERISTICS
VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M12, TJ = –40°C to 125°C (unless otherwise noted)(1)
TL750M12
TL751M12
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP
MAX
Output voltage
Line regulation
VI = 13 V to 26 V
11.76
50
12 12.24
V
VI = 14 V to 19 V,
VI = 13 V to 26 V,
VI = 13 V to 23 V,
IO = 5 mA to 750 mA
IO = 250 mA
IO = 250 mA
f = 120 Hz
15
20
55
30
43
78
mV
Power-supply ripple rejection
Load regulation
dB
120
0.5
0.6
75
mV
IO = 500 mA, TJ = 25°C
IO = 750 mA, TJ = 25°C
IO = 750 mA, TJ = 25°C
IO = 10 mA
Dropout voltage(2)
V
60
Current consumption
Iq = II – IO
mA
5
Shutdown current (TL751M12 only)
ENABLE VIH ≥ 2 V
200
µA
(1) Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be
taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor
on the output, with equivalent series resistance within the guidelines shown in Figure 4.
(2) Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V.
Copyright © 2005–2011, Texas Instruments Incorporated
5
TL750Mxx-Q1, TL751Mxx-Q1
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
The TL750Mxx and TL751Mxx are low-dropout regulators. The output capacitor value and the parasitic
equivalent series resistance (ESR) affect the bandwidth and stability of the control loop for these devices. For
this reason, the capacitor and ESR must be carefully selected for a given operating temperature and load range.
Figure 2 and Figure 3 can be used to establish the appropriate capacitance value and ESR for the best regulator
transient response.
Figure 2 shows the recommended range of ESR for a given load with a 10-µF capacitor on the output. Figure 2
also shows a maximum ESR limit of 2 Ω and a load-dependent minimum ESR limit.
For applications with varying loads, the lightest load condition should be chosen because it is the worst case.
Figure 3 shows the relationship of the reciprocal of ESR to the square root of the capacitance, with a minimum
capacitance limit of 10 µF and a maximum ESR limit of 2 Ω. This figure establishes the amount that the minimum
ESR limit shown in Figure 2 can be adjusted for different capacitor values. For example, where the minimum
load needed is 200 mA, Figure 2 suggests an ESR range of 0.8 Ω to 2 Ω for 10 µF. Figure 3 shows that
changing the capacitor from 10 µF to 400 µF can change the ESR minimum by greater than 3/0.5 (or 6).
Therefore, the new minimum ESR value is 0.8/6 (or 0.13 Ω). This allows an ESR range of 0.13 Ω to 2 Ω,
achieving an expanded ESR range by using a larger capacitor at the output. For better stability in low-current
applications, a small resistance placed in series with the capacitor (see Table 1) is recommended, so that ESRs
better approximate those shown in Figure 2 and Figure 3.
Table 1. Compensation for Increased Stability at Low Currents
MANUFACTURER
AVX
CAPACITANCE
15 µF
ESR TYP
0.9 Ω
PART NUMBER
TAJB156M010S
T491D336M010AS
ADDITIONAL RESISTANCE
1 Ω
KEMET
33 µF
0.6 Ω
0.5 Ω
∆I
L
Applied Load
Current
Load
Voltage
∆V = ∆I × ESR
∆V
L
L
L
Figure 1.
6
Copyright © 2005–2011, Texas Instruments Incorporated
TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
OUTPUT CAPACITOR EQUIVALENT
SERIES RESISTANCE (ESR)
vs
STABILITY
vs
LOAD CURRENT RANGE
EQUIVALENT SERIES RESISTANCE (ESR)
0.04
0.035
0.03
C = 10 µF
Not Recommended
Recommended Min ESR
Potential Instability
1000 µF
L
This Region Not
Recommended for
Operation
C = 0.1 µF
I
f = 120 Hz
2.5
Region of
Best Stability
0.025
0.02
0.5
0.4
0.3
0.2
0.1
0
Max ESR Boundary
400 µF
Region of Best Stability
200 µF
100 µF
0.015
0.01
Min ESR
Boundary
0.005
0
22 µF
10 µF
Potential Instability Region
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I - Load Current Rang e - A
L
1/ESR
Figure 2.
Figure 3.
Copyright © 2005–2011, Texas Instruments Incorporated
7
TL750Mxx-Q1, TL751Mxx-Q1
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS
Table 2. Table of Graphs
FIGURE
Transient input voltage
Output voltage
vs Time
4
5
vs Input voltage
IO = 10 mA
6
Input current
vs Input voltage
IO = 100 mA
7
Dropout voltage
vs Output current
vs Output current
8
Quiescent current
9
Load transient response
Line transient response
10
11
TRANSIENT INPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME
INPUT VOLTAGE
60
50
14
12
I
= 10 mA
O
T = 25°C
V = 14 V + 46e
I
for t ≥ 5 ms
J
(−t/0.230)
T = 25°C
J
10
40
30
8
6
TL75xM08
TL75xM05
t = 1 ms
r
20
10
4
2
0
0
0
100
200
300
400
500
600
0
2
4
6
8
10
12
14
t − Time − ms
V − Input Voltage − V
I
Figure 4.
Figure 5.
8
Copyright © 2005–2011, Texas Instruments Incorporated
TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
INPUT CURRENT
vs
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT VOLTAGE
200
180
160
350
300
I
= 10 mA
O
I
= 100 mA
O
T = 25°C
J
T = 25°C
J
250
140
120
100
200
150
80
60
100
50
40
20
0
0
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 6.
Figure 7.
DROPOUT VOLTAGE
vs
QUIESCENT CURRENT
vs
OUTPUT CURRENT
OUTPUT CURRENT
250
225
12
T = 25°C
J
T = 25°C
V = 14 V
I
J
10
8
200
175
150
125
6
4
100
75
2
0
50
0
50
100
150
200
250
300
0
20
40
60
80
100 150 250 350
I
O
− Output Current − mA
I
O
− Output Current − mA
Figure 8.
Figure 9.
Copyright © 2005–2011, Texas Instruments Incorporated
9
TL750Mxx-Q1, TL751Mxx-Q1
SGLS312J –SEPTEMBER 2005–REVISED JUNE 2011
www.ti.com
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
200
V
I(NOM)
= V + 1 V
O
ESR = 2
I = 20 mA
100
0
L
C = 10 µF
L
T = 25°C
J
− 100
V
I(NOM)
= V + 1 V
O
ESR = 2
C = 10 µF
T = 25°C
J
− 200
150
100
50
L
0
0
50
100 150 200 250 300 350
0
20
40
60
80
100 150 250 350
t − Time − µs
t − Time − µs
Figure 10.
Figure 11.
10
Copyright © 2005–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TL750M05QKTTRQ1
TL750M05QKVURQ1
TL750M08QKVURQ1
TL750M12QKTTRQ1
TL750M12QKVURQ1
TL751M05QKTTRQ1
TL751M05QKVURQ1
TL751M08QKTTRQ1
TL751M08QKVURQ1
TL751M12QKTTRQ1
TL751M12QKVURQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
KVU
KVU
KTT
KVU
KTT
KVU
KTT
KVU
KTT
KVU
3
3
3
3
3
5
5
5
5
5
5
500
2500
2500
500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-260C-168 HR
PFM
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
PFM
Green (RoHS
& no Sb/Br)
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
PFM
2500
500
Green (RoHS
& no Sb/Br)
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
PFM
2500
500
Green (RoHS
& no Sb/Br)
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
PFM
2500
500
Green (RoHS
& no Sb/Br)
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
PFM
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2012
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL750M05-Q1, TL750M08-Q1, TL750M12-Q1, TL751M05-Q1 :
Catalog: TL750M05, TL750M08, TL750M12, TL751M05
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL750M05QKVURQ1
TL750M08QKVURQ1
TL750M12QKTTRQ1
PFM
PFM
KVU
KVU
KTT
3
3
3
2500
2500
500
330.0
330.0
330.0
16.4
16.4
24.4
6.9
6.9
10.5
10.5
15.8
2.7
2.7
4.9
8.0
8.0
16.0
16.0
24.0
Q2
Q2
Q2
DDPAK/
TO-263
10.6
16.0
TL750M12QKVURQ1
TL751M05QKVURQ1
TL751M08QKTTRQ1
PFM
PFM
KVU
KVU
KTT
3
5
5
2500
2500
500
330.0
330.0
330.0
16.4
16.4
24.4
6.9
6.9
10.5
10.5
15.8
2.7
2.7
4.9
8.0
8.0
16.0
16.0
24.0
Q2
Q2
Q2
DDPAK/
TO-263
10.6
16.0
TL751M08QKVURQ1
TL751M12QKTTRQ1
PFM
KVU
KTT
5
5
2500
500
330.0
330.0
16.4
24.4
6.9
10.5
15.8
2.7
4.9
8.0
16.0
24.0
Q2
Q2
DDPAK/
TO-263
10.6
16.0
TL751M12QKVURQ1
PFM
KVU
5
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL750M05QKVURQ1
TL750M08QKVURQ1
TL750M12QKTTRQ1
TL750M12QKVURQ1
TL751M05QKVURQ1
TL751M08QKTTRQ1
TL751M08QKVURQ1
TL751M12QKTTRQ1
TL751M12QKVURQ1
PFM
PFM
KVU
KVU
KTT
KVU
KVU
KTT
KVU
KTT
KVU
3
3
3
3
5
5
5
5
5
2500
2500
500
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
340.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
DDPAK/TO-263
PFM
2500
2500
500
PFM
DDPAK/TO-263
PFM
2500
500
DDPAK/TO-263
PFM
2500
Pack Materials-Page 2
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