TCAN1046V-Q1 [TI]

具有待机和 1.8V IO 支持的汽车类高速双 CAN 收发器;


型号：	TCAN1046V-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有待机和 1.8V IO 支持的汽车类高速双 CAN 收发器
文件：	总40页 (文件大小：2346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCAN1046V-Q1

ZHCSIR6C –SEPTEMBER 2018 –REVISED FEBRUARY 2022

TCAN1046V-Q1 双路汽车类故障保护CAN 收发器

1 特性

3 说明

TCAN1046A-Q1 是一款双路高速控制器局域网 (CAN)

收发器，满足 ISO 11898-2:2016 高速 CAN 规范对物

理层的要求。

• AEC-Q100 标准：符合汽车应用要求

– 温度等级1：–40°C 至125°C T_A

• 两个具有独立模式控制功能的高速CAN 收发器

• 符合ISO 11898-2:2016 和ISO 11898-5:2007 物理

层标准中的要求

TCAN1046V-Q1 收发器支持传统 CAN 和 CAN FD 网

络，数据速率高达8 兆位/秒(Mbps)。TCAN1046V-Q1

包括通过V_IO端子实现的内部逻辑电平转换功能，允许

将收发器 IO 直接连接到 1.8V、2.5V、3.3V 或 5V 逻

辑IO。两个CAN 通道通过待机引脚支持独立的模式控

制。这提供了在不影响其他 CAN 通道状态的情况下将

每个收发器置于其低功耗状态、待机模式的功能。在待

机模式下，TCAN1046V-Q1 可通过 ISO 11898-2:2016

定义的唤醒模式 (WUP) 实现远程唤醒。此类

TCAN1046V-Q1 收发器还包括很多保护和诊断功能，

支持热关断 (TSD)、TXD 显性超时 (DTO)、电源欠压

检测和高达±58V 的总线故障保护。

• 提供功能安全

– 可帮助进行功能安全系统设计的文档

• 支持传统CAN 和经优化的CAN FD 性能（数据速

率为2、5 和8Mbps）

– 具有较短的对称传播延迟时间，可增加时序裕量

– 在负载型CAN 网络中实现更快的数据速率

• I/O 电压范围支持1.7V 至5.5V

– 支持1.8V、2.5V、3.3V 和5V 应用

• 保护特性：

– 总线故障保护：±58V

– 欠压保护

器件信息

– TXD 显性超时(DTO)

封装⁽¹⁾

VSON (14)

SOIC (14)

封装尺寸（标称值）

4.50mm x 3.00mm

8.95mm x 3.91mm

器件型号

• 数据速率低至9.2kbps

– 热关断保护(TSD)

• 工作模式：

– 正常模式

– 支持远程唤醒请求功能的低功耗待机模式

• 优化了未上电时的性能

TCAN1046V-Q1

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_IN

V_OUT

1.8 V, 2.5 V, 3.3

Regulator

(e.g. TPSxxxx)

– 总线和逻辑引脚为高阻抗（运行总线或应用上无

负载）

– 支持热插拔：在总线和RXD 输出上可实现上电/

断电无干扰运行

V_OUT

V Voltage

Regulator

(e.g. TPSxxxx)

V_IN

V_IO

V_CC

CANH1

STB1

Port

RXD1

TXD1

RXD1

TXD1

• 结温范围：–40°C 至150°C

• 接收器共模输入电压：±12V

• 采用SOIC (14) 封装和无引线VSON (14) 封装

(4.5mm x 3.0mm)，具有改进的自动光学检查(AOI)

功能

CANL1

CAN FD Controller

Optional:

Terminating

Node

Optional:

Filtering,

Transient and

ESD

TCAN1046V

Dual CAN FD

Transceiver

STB2

Port

CANH2

RXD2

TXD2

RXD2

TXD2

CANL2

2 应用

Optional:

Terminating

Node

GND1

GND2

Optional:

Filtering,

Transient and

ESD

• 汽车和运输

– 车身控制模块

– 汽车网关

简化版原理图

– 高级驾驶辅助系统(ADAS)

– 信息娱乐系统

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSF70

TCAN1046V-Q1

ZHCSIR6C –SEPTEMBER 2018 –REVISED FEBRUARY 2022

www.ti.com.cn

Table of Contents

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

9.3 System Examples..................................................... 26

10 Power Supply Recommendations..............................26

11 Layout...........................................................................27

11.1 Layout Guidelines................................................... 27

11.2 Layout Example...................................................... 28

12 Device and Documentation Support..........................29

12.1 接收文档更新通知................................................... 29

12.2 支持资源..................................................................29

12.3 Trademarks.............................................................29

12.4 Electrostatic Discharge Caution..............................29

12.5 术语表..................................................................... 29

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 ESD Ratings - IEC Ratings.........................................4

6.4 Recommended Operating Conditions.........................4

6.5 Thermal Characteristics..............................................5

6.6 Supply Characteristics................................................ 5

6.7 Dissipation Ratings..................................................... 6

6.8 Electrical Characteristics.............................................7

6.9 Switching Characteristics............................................8

6.10 Typical Characteristics............................................10

7 Parameter Measurement Information.......................... 11

8 Detailed Description......................................................14

8.1 Overview...................................................................14

Information.................................................................... 29

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (December 2019) to Revision C (February 2022)

Page

• 从数据表中删除了TCAN1048V-Q1....................................................................................................................1

• 将所有TCAN104xV-Q1 更改为TCAN1046V-Q1 .............................................................................................. 1

• 添加了特性“提供功能安全”............................................................................................................................1

• Deleted nSTB1 and nSTB2 pin from the Pin Configuration and Functions and throughout this document........3

• Changed the Test Conditions for I_{OS(SS_DOM)}in the Electrical Characteristics table.......................................... 7

• Deleted the "EMC requirements:" from the Overview secton...........................................................................14

• Added footnotes to 表8-1 ................................................................................................................................19

• Removed section Related Links from the ........................................................................................................29

Changes from Revision A (August 2019) to Revision B (December 2019)

Page

• 首次公开发布数据表........................................................................................................................................... 1

• Changed 图9-2 ............................................................................................................................................... 24

Changes from Revision * (September 2018) to Revision A (August 2019)

Page

• 将数据表从预告信息更改为量产数据................................................................................................................ 1

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5 Pin Configuration and Functions

TXD1

GND1

STB1

TXD1

GND1

STB1

CANH1

CANL1

CANH1

CANL1

RXD1

GND2

TXD2

RXD2

Thermal

Pad

RXD1

GND2

TXD2

RXD2

CANH2

CANL2

STB2

CANH2

CANL2

STB2

Not to scale

图5-1. D (SOIC) Package, 14 Pin

Not to scale

(Top View)

图5-2. DMT (VSON) Package, 14 Pin

(Top View)

表5-1. Pin Functions

Pins

Type

No.

Description

Name

TXD1

GND1

V_CC

Digital Input CAN transmit data input 1, integrated pull-up

GND

Ground connection

5-V supply voltage

Supply

RXD1

GND2

TXD2

RXD2

STB2

CANL2

CANH2

V_IO

Digital Output CAN receive data output 1, tri-state when V_IO< UV_VIO

GND Ground connection

Digital Input CAN transmit data input 2, integrated pull-up

Digital Output CAN receive data output 2, tri-state when V_IO< UV_VIO

Digital Input Standby input 2 for mode control, integrated pull-up

Bus IO

Supply

Bus IO

Low-level CAN bus 2 input or output line

High-level CAN bus 2 input or output line

IO supply voltage

CANL1

CANH1

STB1

Low-level CAN bus 1 input or output line

High-level CAN bus 1 input or output line

Digital Input Standby input 1 for mode control, integrated pull-up

Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB)

ground plane for thermal relief

Thermal Pad (VSON only)

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

–58

–45

–0.3

–8

MAX

UNIT

V_CC

Supply voltage

V_IO

Supply voltage I/O level shifter

V_BUS

V_DIFF

V_{Logic_Input}

V_RXD

I_O(RXD)

T_J

CAN Bus IO voltage CANH1, CANL1 & CANH2, CANL2

Max differential voltage between CANH1, CANL1 & CANH2, CANL2

Logic input terminal voltage

RXD output terminal voltage range (V_RXD1, V_RXD2

)

RXD output current (I_ORXD1, I_ORXD2

)

°C

Operating virtual junction temperature range

Storage temperature

150

–40

–65

T_STG

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values, except differential IO bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

VALUE

UNIT

HBM classification level 3A for

all pins

±3000

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM classification level 3B for

global pins CANH & CANL

V_ESD

Electrostatic discharge

±10000

±750

Charged-device model (CDM), per AEC Q100-011

CDM classification level C5 for all pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings - IEC Ratings

VALUE

UNIT

Pulse 1

–100

Pulse 2a

ISO 7637-2 Transients immunity⁽¹⁾

CAN bus terminals (CANH1, CANL1 and

CANH2, CANL2) to GND

V_Tran

Pulse 3a

–150

100

Pulse 3b

ISO 7637-3 DCC transient immunity⁽²⁾

DCC slow transient pulse

±85

(1) Tested according to IEC 62228-3

(2) Tested according to ISO 7637-3 (2017); Electrical transient transmission by capacitive and inductive coupling via lines other than

supply lines

6.4 Recommended Operating Conditions

MIN

4.5

NOM

MAX

5.5

UNIT

V_CC

Supply voltage

V_IO

Supply voltage for I/O level shifter

1.7

5.5

I_OH(RXD)

I_OL(RXD)

T_A

RXD terminal high level output current –I_OH(RXD1)& I_OH(RXD2)

RXD terminal low level output current –I_OL(RXD1)& I_OL(RXD2)

Operating ambient temperature

–2

125

–40

℃

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6.5 Thermal Characteristics

TCAN1046V-Q1

UNIT

THERMAL METRIC⁽¹⁾

D (SOIC)

DMT (VSON)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

70.8

34.8

38.2

12.8

2.0

℃/W

R_θJC(top)

R_θJB

32.9

5.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

32.5

–

12.8

3.1

Ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Supply Characteristics

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TXDx = 0 V, TXDy = V_IO

STB1 = STB2 = 0 V

R_L= 60 Ω, C_L= open

See 图7-1

77.5

Dominant

One channel⁽¹⁾

TXDx = 0 V, TXDy = V_IO

STB1 = STB2 = 0 V

R_L= 50 Ω, C_L= open

See 图7-1

87.5

140

160

TXD1 = TXD2 = 0 V

STB1 = STB2 = 0 V

R_L= 60 Ω, C_L= open

See 图7-1

Dominant

Two channels

TXD1 = TXD2 = 0 V

STB1 = STB2 = 0 V

R_L= 50 Ω, C_L= open

See 图7-1

100

TXD1 = TXD2 = V_IO

STB1 = STB2 = 0 V

R_L= 50 Ω, C_L= open

See 图7-1

Supply current normal

mode

Recessive

Two channels

I_CC

TXDx = 0 V, TXDy = V_IO

STB1 = STB2 = 0 V

CANHx = CANLx = ±25 V

R_Lx= open, R_Ly= 50 Ω, C_L= open

See 图7-1

Dominant with

bus fault CANx,

CANy

137.5

210

recessive^{(1) (2)}

TXD1 = TXD2 = 0 V

STB1 = STB2 = 0 V

CANHx = CANLx = ±25 V

R_Lx= open, R_Ly= 50 Ω, C_L= open

See 图7-1

Dominant with

bus fault CANx,

CANy

135

dominant⁽²⁾

TXD1 = TXD2 = 0 V

STB1 = STB2 = 0 V

CANH1 = CANL1 = ±25 V

CANH2 = CANL2 = ±25 V

R_Lx= R_Ly= open, C_L= open

See 图7-1

Dominant with

bus fault CANx

and CANy⁽²⁾

170

0.4

260

µA

TXD1 = TXD2 = V_IO

STB1 = STB2 = V_IO

R_L= 60 Ω, C_L= open

See 图7-1

Supply current standby mode

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6.6 Supply Characteristics (continued)

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

TXDx = 0 V & TXDy = V_IO

STB1 = STB2 = 5 V

RXD floating

Dominant

150

348

600

µA

One channel⁽¹⁾

TXD1 = TXD2 = 0 V

STB1 = STB2 = 5 V

RXD floating

IO supply current normal

mode

Dominant

Two channels

255

µA

I_IO

TXD1 = TXD2 = V_IO

STB1 = STB2 = 5 V

RXD floating

Recessive

Two channels

TXD1 = TXD2 = V_IO

STB1 = STB2 = V_IO

RXD1 = RXD2 = floating

IO supply current standby mode

UV_VCC

UV_VIO

Rising under voltage detection on V_CCfor protected mode

Falling under voltage detection on V_CCfor protected mode

Rising under voltage detection on V_IO

4.2

4.4

4.25

1.65

1.59

3.5

1.4

1.56

1.51

Falling under voltage detection on V_IO

(1) TXD1 and TXD2 are interchangeable for TXDx and TXDy

(2) CAN1 and CAN2 are interchangeable for CANx and CANy

6.7 Dissipation Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CC= 5 V, V_IO= 1.8 V, T_J= 27°C, R_L= 60Ω,

TXD input = 250 kHz 50% duty cycle square

wave, C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

P_D

130

V_CC= 5 V, V_IO= 3.3 V, T_J= 27°C, R_L= 60Ω,

TXD input = 250 kHz 50% duty cycle square

wave, C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

130

140

V_CC= 5 V, V_IO= 5 V, T_J= 27°C, R_L= 60Ω, TXD

input = 250 kHz 50% duty cycle square wave,

C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

V_CC= 5.5 V, V_IO= 1.8 V, T_J= 150°C, R_L= 60Ω,

TXD input = 2.5 MHz 50% duty cycle square

wave, C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

V_CC= 5.5 V, V_IO= 3.3 V, T_J= 150°C, R_L= 60Ω,

TXD input = 2.5 MHz 50% duty cycle square

wave, C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

V_CC= 5.5 V, V_IO= 5 V, T_J= 150°C, R_L= 60Ω,

TXD input = 2.5 MHz 50% duty cycle square

wave, C_{L_RXD}= 15 pF

Average power dissipation one channel

Normal mode

P_D

°C

T_TSD

Thermal shutdown temperature

192

T_{TSD_HYS}Thermal shutdown hysteresis

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6.8 Electrical Characteristics

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted); CAN electrical parameters apply

to both channels

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Driver Electrical Characteristics

CANH

CANL

2.75

0.5

4.5

TXD = 0 V, STB = 0 V, 50 Ω ≤R_L≤65

Ω, C_L= open, R_CM= open

See 图7-2 and 图8-3,

Dominant output voltage

Normal mode

V_O(DOM)

2.25

TXD = V_IO, STB = 0 V, R_L= open (no

load), R_CM= open

See 图7-2 and 图8-3

Recessive output voltage

Normal mode

V_O(REC)

CANH and CANL

0.5 V_CC

STB = 0 V, R_L= 60 Ω, C_SPLIT= 4.7 nF, C_L

= open, R_CM= open, TXD = 250 kHz, 1

MHz, 2.5 MHz

Driver symmetry

(V_O(CANH)+ V_O(CANL))/V_CC

V_SYM

0.9

1.1 V/V

400 mV

See 图7-2 and 图9-2

DC output symmetry

(V_CC- V_O(CANH)- V_O(CANL)

STB = 0 V, R_L= 60 Ω, C_L= open

See 图7-2 and 图8-3

V_{SYM_DC}

–400

)

TXD = 0 V, STB = 0 V, 50 Ω ≤R_L≤65

Ω, C_L= open

See 图7-2 and 图8-3

1.5

3.3

Differential output voltage

Normal mode

TXD = 0 V, STB = 0 V, 45 Ω ≤R_L≤70

Ω, C_L= open

See 图7-2 and 图8-3

V_OD(DOM)

CANH - CANL

1.4

1.5

Dominant

TXD = 0 V, STB = 0 V, R_L= 2240 Ω, C_L

open

See 图7-2 and 图8-3

TXD = V_IO, STB = 0 V, R_L= 60 Ω, C_L

open

See 图7-2 and 图8-3

12 mV

50 mV

–120

–50

Differential output voltage

Normal mode

Recessive

V_OD(REC)

CANH - CANL

TXD = V_IO, STB = 0 V, R_L= open, C_L

open

See 图7-2 and 图8-3

CANH

-0.1

-0.2

0.1

0.2

STB = V_IO, R_L= open (no load)

See 图7-2 and 图8-3

Bus output voltage

Standby mode

V_O(STB)

CANL

CANH - CANL

STB = 0 V, V_(CANH)= -15 V to 40 V, CANL

= open, TXD = 0 V

See 图7-7 and 图8-3

–115

Short-circuit steady-state output current,

dominant

Normal mode

I_{OS(SS_DOM)}

STB = 0 V, V_{(CAN_L)}= -15 V to 40 V, CANH

= open, TXD = 0 V

115 mA

See 图7-7 and 图8-3

Short-circuit steady-state output current,

recessive

Normal mode

STB = 0 V, –27 V ≤V_BUS≤32 V, where

V_BUS= CANH = CANL, TXD = V_IO

See 图7-7 and 图8-3

I_{OS(SS_REC)}

–5

Receiver Electrical Characteristics

Input threshold voltage

Normal mode

STB = 0 V, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

V_IT

500

400

0.9

-4

900 mV

Input threshold

V_IT(STB)

STB = V_IO, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

1150 mV

Standby mode

Dominant state differential input voltage range

Normal mode

STB = 0 V, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

V_DOM

0.5

Recessive state differential input voltage range

Normal mode

STB = 0 V, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

V_REC

Dominant state differential input voltage range

Standby mode

STB = V_IO, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

V_DOM(STB)

V_REC(STB)

V_HYS

1.15

-4

Recessive state differential input voltage range

Standby mode

STB = V_IO, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

0.4

Hysteresis voltage for input threshold

Normal mode

STB = 0 V, -12 V ≤V_CM≤12 V

See 图7-3, 表7-1, and 表8-5

100

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6.8 Electrical Characteristics (continued)

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted); CAN electrical parameters apply

to both channels

PARAMETER

TEST CONDITIONS

See 图7-3 and 表8-5 表8-5

MIN

TYP

MAX UNIT

Common mode range

Normal and standby modes

V_CM

–12

I_LKG(IOFF)

C_I

Unpowered bus input leakage current

Input capacitance to ground (CANH or CANL)

Differential input capacitance

CANH = CANL = 5 V, V_CC= V_IO= GND

µA

20 pF

10 pF

(1)

TXD = V_IO

C_ID

R_ID

Differential input resistance

kΩ

TXD = V_IO⁽¹⁾, STB = 0 V, -12 V ≤V_CM

12 V

≤

Single ended input resistance

(CANH or CANL)

R_IN

TXD Terminal (CAN Transmit Data Input)

V_IH

High-level input voltage

0.7 V_IO

V_IL

Low-level input voltage

0.3 V_IO

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

TXD = V_CC= V_IO= 5.5 V

-100

–20

µA

–2.5

–200

–1

I_IL

TXD = 0 V, V_CC= V_IO= 5.5 V

TXD = 5.5 V, V_CC= V_IO= 0 V

I_LKG(OFF)

RXD Terminal (CAN Receive Data Output)

I_O= –2 mA,

See 图7-3

V_OH

High-level output voltage

Low-level output voltage

0.8 V_IO

I_O= –2 mA,

See 图7-3

V_OL

0.2 V_IO

STB Terminal (Standby Mode Input)

V_IH

High-level input voltage

0.7 V_IO

V_IL

Low-level input voltage

0.3 V_IO

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

V_CC= V_IO= STB = 5.5 V

–2

µA

–2

–20

–1

I_IL

V_CC= V_IO= 5.5 V, STB = 0 V

STB = 5.5V, V_CC= V_IO= 0 V

I_LKG(OFF)

(1) V_IO= V_CCin non-V variants of device

6.9 Switching Characteristics

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted); Timing parameters apply to both

CAN channels

PARAMETER

TEST CONDITIONS

MIN

TYP

125

165

150

180

MAX

210

255

210

UNIT

Device Switching Characteristics

Normal mode, R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF

V_IO= 2.8 V to 5.5 V

Total loop delay, driver input (TXD) to receiver

output (RXD), recessive to dominant

t_PROP(LOOP1)

t_PROP(LOOP2)

See 图7-4

Normal mode, R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF

V_IO= 1.7 V

Total loop delay, driver input (TXD) to receiver

output (RXD), recessive to dominant

See 图7-4

Normal mode, R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF

V_IO= 2.8 V to 5.5 V

Total loop delay, driver input (TXD) to receiver

output (RXD), dominant to recessive

See 图7-4

Normal mode, R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF

V_IO= 1.7 V

Total loop delay, driver input (TXD) to receiver

output (RXD), dominant to recessive

t_PROP(LOOP2)

255

µs

See 图7-4

Mode change time, from normal to standby or from

standby to normal

t_MODE

See 图7-5

t_{WK_FILTER}

Filter time for a valid wake-up pattern

Bus wake-up timeout

0.5

0.8

1.8

µs

See 图8-5

t_{WK_TIMEOUT}

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6.9 Switching Characteristics (continued)

Over recommended operating conditions with T_A= -40℃to 125℃(unless otherwise noted); Timing parameters apply to both

CAN channels

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Driver Switching Characteristics

Propagation delay time, high TXD to driver

recessive (dominant to recessive)

t_pHR

t_pLD

Propagation delay time, low TXD to driver dominant

(recessive to dominant)

STB = 0 V, R_L= 60 Ω, C_L= 100 pF

See 图7-2 and 图7-6

t_sk(p)

Pulse skew (|tpHR - tpLD|)

Differential output signal rise time

Differential output signal fall time

Dominant timeout

t_R

t_F

t_{TXD_DTO}

1.2

4.0

Receiver Switching Characteristics

Propagation delay time, bus recessive input to high

t_pRH

output (dominant to recessive)

Propagation delay time, bus dominant input to low

output (recessive to dominant)

STB = 0 V, C_L(RXD)= 15 pF

See 图7-3

t_pDL

t_R

t_F

RXD output signal rise time

RXD output signal fall time

FD Timing Characteristics

Bit time on CAN bus output pins

t_BIT(BUS)

t_BIT(RXD)

t_REC

450

155

400

120

-50

530

210

550

220

t_BIT(TXD)= 500 ns

Bit time on CAN bus output pins

t_BIT(TXD)= 200 ns

Bit time on RXD output pins

t_BIT(TXD)= 500 ns

STB = 0 V, R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

See 图7-4

Bit time on RXD output pins

t_BIT(TXD)= 200 ns

Receiver timing symmetry

t_BIT(TXD)= 500 ns

Receiver timing symmetry

t_BIT(TXD)= 200 ns

t_REC

-45

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6.10 Typical Characteristics

2.5

1.5

0.5

4.5

4.6

4.7

4.8

4.9

5.1

5.2

5.3

5.4

5.5

-40

-25

-10

110

125

V_CC(V)

Temperature (èC)

TCAN

Temp = 25 °C

V_CC= 5 V

V_IO= 3.3 V

R_L= 60 Ω

图6-2. V_OD(DOM)Over V_CCV_OD(DOM)vs V_CC

图6-1. V_OD(DOM)Over Temperature V_OD(DOM)vs V_CC

Transceiver 1 and Transceiver 2

1.5

0.5

-40

-25

-10

110

125

-40

-25

-10

110

125

Temperature (èC)

ICC_

TCAN

V_CC= 5 V

V_IO= 3.3 V

V_CC= 5 V

V_IO= 3.3 V

R_L= 60 Ω

图6-3. I_CCStandby vs Temperature

图6-4. I_IOStandby vs Temperature

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7 Parameter Measurement Information

CANH

TXD

R_L

C_L

CANL

图7-1. I_CCTest Circuit

R_CM

CANH

50%

TXD

R_L

C_L

V_OD

V_CM

V_CC

V_O(CANH)

t_pLD

t_pHR

90%

10%

CANL

R_CM

0.9V

V_O(CANL)

V_OD

0.5V

t_R

t_F

图7-2. Driver Test Circuit and Measurement

CANH

1.5V

0.9V

V_ID

I_O

RXD

0.5V

V_ID

t_pDL

t_pRH

V_OH

V_O

C_{L_RXD}

CANL

90%

V_O(RXD)

50%

10%

V_OL

t_F

t_R

图7-3. Receiver Test Circuit and Measurement

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表7-1. Receiver Differential Input Voltage Threshold Test

Output

Input (See 图7-3)

V_CANH

-11.5 V

12.5 V

-8.55 V

9.45 V

-8.75 V

9.25 V

-11.8 V

12.2 V

Open

V_CANL

|V_ID

RXD

-12.5 V

11.5 V

1000 mV

900 mV

500 mV

400 mV

Low

V_OL

-9.45 V

8.55 V

-9.25 V

8.75 V

-12.2 V

11.8 V

High

V_OH

Open

TXD

V_I

70%

t_LOOP2

30%

CANH

TXD

5 x t_BIT(TXD)

t_BIT(TXD)

V_I

R_L

C_L

CANL

STB

t_BIT(BUS)

900mV

500mV

RXD

V_DIFF

V_O

C_{L_RXD}

RXD

V_OH

70%

30%

t_BIT(RXD)

V_OL

t_LOOP1

图7-4. Transmitter and Receiver Timing Test Circuit and Measurement

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CANH

V_IH

TXD

STB

C_L

R_L

STB

50%

CANL

V_I

t_MODE

RXD

V_OH

V_O

C_{L_RXD}

RXD

50%

V_OL

图7-5. TCAN1046V-Q1 t_MODETest Circuit and Measurement

V_IH

CANH

TXD

R_L

C_L

V_OD

V_OD(D)

CANL

0.9V

V_OD

0.5V

t_{TXD_DTO}

图7-6. TXD Dominant Timeout Test Circuit and Measurement

200 ꢀs

I_OS

CANH

TXD

V_BUS

I_OS

CANL

V_BUS

图7-7. Driver Short-Circuit Current Test and Measurement

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8 Detailed Description

8.1 Overview

The TCAN1046V-Q1 meets or exceeds the specifications of the ISO 11898-2:2016 high speed CAN (Controller

Area Network) physical layer standard. The device has been certified to the requirements of ISO 11898-2:2016

and ISO 11898-5:2007 physical layer requirements according to the GIFT/ICT high speed CAN test specification.

The transceiver provides a number of different protection features making it ideal for the stringent automotive

system requirements while also supporting CAN FD data rates up to 8 Mbps.

The TCAN1046V-Q1 conforms to the following CAN standards:

• CAN transceiver physical layer standards:

– ISO 11898-2:2016 High speed medium access unit

– ISO 11898-5:2007 High speed medium access unit with low-power mode

– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps

– SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps

– SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps

– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps

– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps

– ARINC 825-4 General Standardization of CAN (Controller Area Network) Bus Protocol For Airborne Use

• Conformance test requirements:

– ISO 16845-2 Road vehicles –Controller area network (CAN) conformance test plan Part 2: High-speed

medium access unit conformance test plan

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8.2 Functional Block Diagram

V_CC

V_IO

V_CC

V_IO

13 CANH1

TSD

Dominant

time-out

TXD1

12 CANL1

V_IO

STB1 14

Mode Select

UVP

V_IO

MUX

Logic Output

RXD1

V_IO

WUP Monitor

Low Power Receiver

V_CC

V_IO

10 CANH2

TSD

Dominant

time-out

TXD2

STB2

CANL2

V_IO

Mode Select

UVP

V_IO

MUX

RXD2

Logic Output

V_IO

WUP Monitor

Low Power Receiver

GND1

GND2

图8-1. Block Diagram

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8.3 Feature Description

8.3.1 Pin Description

8.3.1.1 TXD1 and TXD2

TXD1 and TXD2 are the logic-level signals, referenced to either V_CCor V_IO, from a CAN controller to the device.

8.3.1.2 GND1 and GND2

GND1 and GND2 are ground pins of the transceiver, both must be connected to the PCB ground.

8.3.1.3 V_CC

V_CCprovides the 5-V power supply to the CAN transceiver.

8.3.1.4 RXD1 and RXD2

RXD1 and RXD2 are the logic-level signals, referenced to V_IO, from the TCAN1046V-Q1 to a CAN controller.

This pin is only driven once V_IOis present.

8.3.1.5 V_IO

The V_IOpin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement for

a level shifter. It supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.

8.3.1.6 CANH and CANL

These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver

and the low-voltage WUP CAN receiver.

8.3.1.7 STB1 and STB2 (Standby)

The STB1 and STB2 pins are input pins used for mode control of the transceiver.

The TCAN1046V-Q1 implements STB1 and STB2 which can be supplied from either the system processor or

from a static system voltage source. If normal mode is the only intended mode of operation than the STB pins

can be tied directly to GND.

8.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See 图8-2 and 图8-3.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD1,

TXD2, RXD1 and RXD2 pins. A recessive bus state occurs when the bus is biased to V_CC/2 via the high-

resistance internal input resistors R_IN) of the receiver and corresponds to a logic high on the TXD1, TXD2, RXD1

and RXD2 pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a

dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than

the differential voltage of a single driver.

The TCAN1046V-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state

where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See 图

8-2 and 图8-3.

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Normal Mode

Standby Mode

CANH

V_DIFF

CANL

Recessive

Dominant

Recessive

Time, t

图8-2. Bus States

CANH

2.5V

GND

RXD

Bias

Unit

CANL

A. Normal Mode

B. Standby Mode

图8-3. Simplified Recessive Common Mode Bias Unit and Receiver

8.3.3 TXD Dominant Timeout (DTO)

During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node

from blocking network communication in the event of a hardware or software failure where TXD is held dominant

longer than the timeout period t_{TXD_DTO}. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising

edge is seen before the timeout period of the circuit, t_{TXD_DTO}, the CAN driver is disabled. This frees the bus for

communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is

seen on the TXD pin, thus clearing the dominant timeout. The receiver remains active and biased to V_CC/2 and

the RXD output reflects the activity on the CAN bus during the TXD DTO fault.

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data

rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the

worst case, where five successive dominant bits are followed immediately by an error frame. The minimum

transmitted data rate may be calculated using 方程式1.

Minimum Data Rate = 11 bits / t_{TXD_DTO}= 11 bits / 1.2 ms = 9.2 kbps

(1)

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Fault is repaired & transmission capability

restored

TXD fault stuck dominant: example PCB failure or bad software

t_{TXD_DTO}

TXD (driver)

Driver disabled freeing bus for other nodes

Normal CAN communication

Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO

prevents this and frees the bus for communication after the time t_{TXD_DTO}

CAN Bus Signal

t_{TXD_DTO}

Communication from other bus node(s)

Communication from repaired node

RXD (receiver)

Communication from local node

Communication from other bus node(s)

Communication from repaired local node

图8-4. Example Timing Diagram for TXD Dominant Timeout

8.3.4 CAN Bus Short Circuit Current Limiting

The TCAN1046V-Q1 has several protection features that limit the short circuit current when a CAN bus line is

shorted. These include CAN driver current limiting in the dominant and recessive states and TXD dominant state

timeout which prevents permanently having the higher short circuit current of a dominant state in case of a

system fault. During CAN communication the bus switches between the dominant and recessive states, thus the

short circuit current may be viewed as either the current during each bus state or as a DC average current.

When selecting termination resistors or a common mode choke for the CAN design the average power rating,

I_OS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has

forced state changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure

there is a minimum amount of recessive time on the bus even if the data field contains a high percentage of

dominant bits.

The average short circuit current of the bus depends on the ratio of recessive to dominant bits and their

respective short circuit currents. The average short circuit current may be calculated using 方程式2.

I_OS(AVG)= % Transmit x [(% REC_Bits x I_{OS(SS)_REC}) + (% DOM_Bits x I_{OS(SS)_DOM})] + [% Receive x I_{OS(SS)_REC}

]

(2)

Where:

• I_OS(AVG)is the average short circuit current

• % Transmit is the percentage the node is transmitting CAN messages

• % Receive is the percentage the node is receiving CAN messages

• % REC_Bits is the percentage of recessive bits in the transmitted CAN messages

• % DOM_Bits is the percentage of dominant bits in the transmitted CAN messages

• I_{OS(SS)_REC}is the recessive steady state short circuit current

• I_{OS(SS)_DOM}is the dominant steady state short circuit current

This short circuit current and the possible fault cases of the network should be taken into consideration when

sizing the power supply used to generate the transceivers V_CCsupply.

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8.3.5 Thermal Shutdown (TSD)

If the junction temperature of the TCAN1046V-Q1 exceeds the thermal shutdown threshold, T_TSD, the device

turns off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is

cleared when the junction temperature of the device drops below T_TSD. The CAN bus pins are biased to V_CC/2

during a TSD fault and the receiver to RXD path remains operational. The TCAN1046V-Q1 TSD circuit includes

hysteresis which prevents the CAN driver output from oscillating during a TSD fault.

8.3.6 Undervoltage Lockout

The supply pins, V_CCand V_IO, have undervoltage detection that places the device into a protected state. This

protects the bus during an undervoltage event on either supply pin.

表8-1. Undervoltage Lockout - TCAN1046V-Q1

V_CC

V_IO

DEVICE STATE

BUS

RXD PIN

Mirrors bus

> UV_VCC

> UV_VIO

Normal

Per TXD

STB = V_IO: Standby mode

STB = GND: Protected mode

Protected

V_IO: Remote wake request⁽²⁾

< UV_VCC

> UV_VIO

High impedance

Weak pull-down to

ground⁽¹⁾

Recessive

> UV_VCC

< UV_VCC

< UV_VIO

High impedance

Protected

(1) V_CC= GND, see I_LKG(OFF)

(2) See 节8.4.3.1

Once the undervoltage condition is cleared and t_MODEhas expired the TCAN1046V-Q1 transitions to normal

mode and the host controller can send and receive CAN traffic again.

8.3.7 Unpowered Device

The TCAN1046V-Q1 is designed to be an ideal passive or no load to the CAN bus if the device is unpowered.

The bus pins were designed to have low leakage currents when the device is unpowered, so they do not load

the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains

operational.

The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits

which may remain powered.

8.3.8 Floating pins

The TCAN1046V-Q1 has internal pull-ups or pull-downs on critical pins which place the device into known states

if the pin floats. This internal bias should not be relied upon by design though, especially in noisy environments,

but instead should be considered a failsafe protection feature.

When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be

chosen. This ensures that the TXD output of the CAN controller maintains acceptable bit time to the input of the

CAN transceiver. See 表8-2 for details on pin bias conditions.

表8-2. Pin Bias

Pull-up or Pull-down

Comment

Weakly biases TXD1 and TXD2 towards recessive to prevent bus

blockage or TXD DTO triggering

TXD1 and TXD2

Pull-up

Weakly biases STB1 and STB2 towards low-power standby mode to

prevent excessive system power

STB1 and STB2

Pull-up

8.4 Device Functional Modes

8.4.1 Operating Modes

The TCAN1046V-Q1 has two main operating modes; normal mode and standby mode. Operating mode

selection is made by applying a high or low level to the STB pin on the device.

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表8-3. Operating Modes

STB

High

Low

Device Mode

Standby mode

Normal Mode

Driver

Disabled

Enabled

Receiver

RXD Pin

High (recessive) until valid WUP

is received

Low-power receiver with bus

monitor enable

See section 8.3.3.1

Enabled

Mirrors bus state

8.4.2 Normal Mode

This is the normal operating mode of the TCAN1046V-Q1. The CAN driver and receiver are fully operational and

CAN communication is bi-directional. The driver is translating a digital input on the TXD1 and TXD2 inputs to a

differential output on the CANH1, CANL1 and CANH2, CANL2 bus pins. The receiver is translating the

differential signal from CANH1, CANL1 and CANH2, CANL2 to a digital output on the RXD1 and RXD2 outputs.

8.4.3 Standby Mode

This is the low-power mode of the TCAN1046V-Q1. The CAN driver and main receiver are switched off and bi-

directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled to

allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD1 or RXD2 depending on

the channel which received the WUP as shown in 图 8-5. The local CAN protocol controller should monitor

RXD1 and RXD2 for transitions (high-to-low) and reactivate the device to normal mode by pulling the STB1 and

STB2 pin low. The CAN bus pins are weakly pulled to GND in this mode; see 图8-2 and 图8-3.

In standby mode, only the V_IOsupply is required therefore the V_CCmay be switched off for additional system

level current savings.

8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode

The TCAN1046V-Q1 supports a remote wake-up request that is used to indicate to the host controller that the

bus is active and the node should return to normal operation.

The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to

qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a

falling edge and low period corresponding to a filtered dominant on the RXD1 or RXD2 output of the

TCAN1046V-Q1.

The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second

filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered

recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor

is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon

reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD1 or RXD2

output low every time an additional filtered dominant signal is received from the bus.

For a dominant or recessive to be considered filtered, the bus must be in that state for more than the t_{WK_FILTER}

time. Due to variability in t_{WK_FILTER}the following scenarios are applicable. Bus state times less than

t_{WK_FILTER(MIN)}are never detected as part of a WUP and thus no wake request is generated. Bus state times

between t_{WK_FILTER(MIN)}and t_{WK_FILTER(MAX)}may be detected as part of a WUP and a wake-up request may be

generated. Bus state times greater than t_{WK_FILTER(MAX)}are always detected as part of a WUP, and thus a wake

request is always generated. See 图8-5 for the timing diagram of the wake-up pattern.

The pattern and t_{WK_FILTER}time used for the WUP prevents noise and bus stuck dominant faults from causing

false wake-up requests while allowing any valid message to initiate a wake-up request.

The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The t_{WK_FILTER}timing

for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing

has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the

filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.

For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout

feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout

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value t ≤ t_{WK_TIMEOUT}. If not, the internal logic is reset and the transceiver remains in its current state without

waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this

section. See 图8-5 for the timing diagram of the wake-up pattern with wake timeout feature.

Bus Wake via RXD

Wake-Up Pattern (WUP) received in t < t_{WK_Timeout}

Request

Filtered

Dominant

Filtered

Dominant

Filtered

Recessive

Waiting for

Filtered

Waiting for

Filtered

Dominant

Recessive

Bus

Bus V_Diff

RXD

t_{WK_FILTER}

Filtered Dominant RXD Output

Bus Wake Via RXD Requests

图8-5. Wake-Up Pattern (WUP) with t_{WK_TIMEOUT}

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8.4.4 Driver and Receiver Function

The digital logic input and output levels for the TCAN1046V-Q1 are CMOS levels with respect to V_IOfor

compatibility with protocol controllers having 1.8 V, 2.5 V, 3.3 V, or 5 V I/O levels.

表8-4. Driver Function Table

Bus Outputs

Device Mode

TXD Input⁽¹⁾

Driven Bus State⁽²⁾

CANH

High

CANL

Low

High or open

Dominant

Normal

High impedance

Biased recessive

Biased to ground

Standby

(1) X = irrelevant

(2) For bus state and bias see 图8-2 and 图8-3

表8-5. Receiver Function Table Normal and Standby Mode

CAN Differential Inputs

V_ID= V_CANH–V_CANL

Device Mode

Bus State

RXD Pin

Dominant

Undefined

Recessive

Dominant

Undefined

Recessive

Open

Low

Undefined

High

V_ID≥0.9 V

0.5 V < V_ID< 0.9 V

V_ID≤0.5 V

Normal

High

Low if a remote wake event

occurred

V_ID≥1.15 V

Standby

Any

0.4 V < V_ID< 1.15 V

V_ID≤0.4 V

See 图8-5

High

Open (V_ID≈0 V)

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

9.2 Typical Application

The TCAN1046V-Q1 transceiver can be used in applications with a host controller or FPGA that includes the link

layer portion of the CAN protocol. 图 9-1 shows a typical configuration for 5 V controller applications. The bus

termination is shown for illustrative purposes.

V_IN

V_OUT

V_IN

5V Voltage

Regulator

(e.g. TPSxxxx)

V_CC

V_IO

V_CC

CANH1

STB1

Port x

RXD1

TXD1

RXD1

TXD1

CANL1

CAN FD Controller

Optional:

Terminating

Node

Optional:

Filtering,

TCAN1046V-Q1

Transient and

ESD

Dual CAN FD

Transceiver

STB2

Port x

CANH2

RXD2

TXD2

RXD2

TXD2

CANL2

Optional:

Terminating

Node

GND1

GND2

Optional:

Filtering,

Transient and

ESD

图9-1. Transceiver Application Using 5 V I/O Connections

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9.2.1 Design Requirements

9.2.1.1 CAN Termination

Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.

If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used,

see 图 9-2. Split termination improves the electromagnetic emissions behavior of the network by filtering higher-

frequency common-mode noise that may be present on the differential signal lines.

Standard Termination

Split Termination

CANH

R_TERM/2

R_TERM

TCAN Transceiver

C_SPLIT

R_TERM/2

CANL

图9-2. CAN Bus Termination Concepts

9.2.2 Detailed Design Procedures

9.2.2.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.

However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a

bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1046V-Q1.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO

11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading

of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE

J2284, SAE J1939, and NMEA 2000.

A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver

differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output

must be greater than 1.5 V. The TCAN1046V-Q1 family is specified to meet the 1.5 V requirement down to 50 Ω

and is specified to meet 1.4 V differential output at 45Ω bus load. The differential input resistance of the

TCAN1046V-Q1 is a minimum of 40 kΩ. If 100 TCAN1046V-Q1 transceivers are in parallel on a bus, this is

equivalent to a 400-Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus

load of approximately 52 Ω. Therefore, the TCAN1046V-Q1 family theoretically supports over 100 transceivers

on a single bus segment. However, for a CAN network design margin must be given for signal loss across the

system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a

practical maximum number of nodes is often lower. Bus length may also be extended beyond 40 meters by

careful system design and data rate tradeoffs. For example, CANopen network design guidelines allow the

network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes and

significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional

standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility,

the CAN network system designer must take the responsibility of good network design to ensure robust network

operation.

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Node 1

Node 2

Node 3

Node n

(with termination)

System Controller

CAN FD

Controller

CAN FD

Controller

TCAN1046V-Q1

TCAN1044-Q1

TCAN1145-Q1

R_TERM

图9-3. Typical CAN Bus

9.2.3 Application Curves

V_CC= 5 V

V_IO= 3.3 V

V_CC= 5 V

V_IO= 3.3 V

R_L= 60 Ω

图9-4. t_PROP(LOOP1)TRX1 & TRX2

图9-5. t_PROP(LOOP2)TRX1 & TRX2

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9.3 System Examples

The TCAN1046V-Q1 CAN transceiver is typically used in applications with a host controller or FPGA that

includes the link layer portion of the CAN protocol. A 1.8 V, 2.5 V, or 3.3 V application is shown in 图 9-6. The

bus termination is shown for illustrative purposes.

V_IN

V_OUT

1.8 V, 2.5 V, 3.3 V

Regulator

(e.g. TPSxxxx)

V_OUT

5 V Voltage

V_IN

Regulator

(e.g. TPSxxxx)

V_IO

V_CC

CANH1

STB1

Port x

RXD1

TXD1

RXD1

TXD1

CANL1

CAN FD Controller

Optional:

Terminating

Node

Optional:

Filtering,

TCAN1046V

Transient and

ESD

Dual CAN FD

Transceiver

STB2

Port x

CANH2

RXD2

TXD2

RXD2

TXD2

CANL2

Optional:

Terminating

Node

GND1

GND2

Optional:

Filtering,

Transient and

ESD

图9-6. Transceiver Application Using 1.8 V, 2.5 V, 3.3 V I/O Connections

10 Power Supply Recommendations

The TCAN1046V-Q1 device is designed to operate with a main V_CCinput voltage supply range between 4.5 V

and 5.5 V. The device has an IO level shifting supply input, V_IO, designed for a range between 1.8 V and 5.5 V.

Both supply inputs must be well regulated. A decoupling capacitor, typically 100 nF, should be placed near the

CAN transceiver's main V_CCand V_IOsupply pins in addition to bypass capacitors.

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11 Layout

Robust and reliable CAN node design may require special layout techniques depending on the application and

automotive design requirements. Since transient disturbances have high frequency content and a wide

bandwidth, high-frequency layout techniques should be applied during PCB design.

11.1 Layout Guidelines

• Place the protection and filtering circuitry close to the bus connectors, J1 and J2, to prevent transients, ESD,

and noise from propagating onto the board. This layout example shows optional transient voltage

suppression (TVS) diodes, D1 and D2, which may be implemented if the system-level requirements exceed

the specified rating of the transceiver. This example also shows optional bus filter capacitors C6, C8, C9, and

C11.

• Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device.

• Use at least two vias for supply and ground connections of bypass capacitors and protection devices to

minimize trace and via inductance.

备注

High frequency current follows the path of least impedance and not the path of least resistance.

• This layout example shows how split termination could be implemented on the CAN node. The termination is

split into two pairs of resistors, R8, R9, R10, and R11, with the center or split tap of the termination connected

to ground via capacitors C7 and C10. Split termination provides common mode filtering for the bus. See 节

9.2.1.1, 节8.3.4, and 方程式2 for information on termination concepts and power ratings needed for the

termination resistor(s).

• To limit current of digital lines series resistors may be used. Examples are R2, R3, R5, R6, R7, and R12.

• Pin 1 and pin 6 are shown for the TXD1 and TXD2 inputs of the device with R1 and R4 as optional pull-up

resistors. If an open drain host controller is used this is mandatory to ensure the bit timing into the device is

met.

• Pin 8 and 14 are shown assuming the mode pin STB is used. If the device is only used in normal mode then

only a pull-down resistor is needed.

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11.2 Layout Example

STB1

GND

V_CC

TXD1

GND1

V_CC

STB1

CANH1

CANL1

TXD1

GND

V_CC

GND

TCAN1046V

V_IO

RXD1

GND2

RXD1

R10

R11

CANH2

V_CC

C10

TXD2

RXD2

CANL2

STB2

GND

RXD2

GND

STB2

图11-1. Example Layout

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12 Device and Documentation Support

12.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCAN1046VDMTRQ1

ACTIVE

VSON

DMT

3000 RoHS & Green

NIPDAU | SN

Level-2-260C-1 YEAR

-40 to 125

1046V

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCAN1046VDMTRQ1

VSON

DMT

3000

330.0

12.4

3.3

4.8

1.2

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON DMT 14

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TCAN1046VDMTRQ1

3000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DMT 14

3 x 4.5, 0.65 mm pitch

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225088/A

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PACKAGE OUTLINE

DMT0014A

VSON - 0.9 mm max height

SCALE 3.200

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

4.6

4.4

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

0.9 MAX

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

3.9

SYMM

4.2 0.1

12X 0.65

0.35

0.25

14X

0.45

0.35

14X

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

4223033/B 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DMT0014A

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

14X (0.6)

14X (0.3)

SYMM

(1.85)

12X (0.65)

SYMM

(4.2)

(0.69)

TYP

(

0.2) VIA

TYP

(R0.05) TYP

(0.55) TYP

(2.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223033/B 10/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DMT0014A

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.47)

14X (0.6)

14X (0.3)

(1.18)

12X (0.65)

SYMM

(1.38)

(R0.05) TYP

METAL

TYP

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15

77.4% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4223033/B 10/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE OUTLINE

DMT0014B

VSON - 1 mm max height

SCALE 3.200

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

4.6

4.4

0.1 MIN

(0.13)

1.0

0.8

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

(0.19) TYP

3.9

SYMM

4.2 0.1

12X 0.65

0.35

0.25

14X

0.45

0.35

PIN 1 ID

14X

0.1

C A B

(OPTIONAL)

0.05

4225087/B 01/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DMT0014B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

14X (0.6)

14X (0.3)

SYMM

(1.85)

12X (0.65)

SYMM

(4.2)

(0.69)

TYP

(

0.2) VIA

TYP

(R0.05) TYP

(0.55) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225087/B 01/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DMT0014B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.47)

14X (0.6)

14X (0.3)

(1.18)

12X (0.65)

SYMM

(1.38)

(R0.05) TYP

METAL

TYP

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15

77.4% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4225087/B 01/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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