TCAN104XAV-Q1 [TI]
TCAN104xAV-Q1 Automotive Dual CAN FD Transceiver with 1.8-V I/O Support and Standby Mode;型号: | TCAN104XAV-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TCAN104xAV-Q1 Automotive Dual CAN FD Transceiver with 1.8-V I/O Support and Standby Mode |
文件: | 总41页 (文件大小:2671K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TCAN1046AV-Q1, TCAN1048AV-Q1
SLLSFL8A – JULY 2021 – REVISED DECEMBER 2021
TCAN104xAV-Q1 Automotive Dual CAN FD Transceiver with 1.8-V I/O Support and
Standby Mode
1 Features
3 Description
•
•
•
•
AEC-Q100 (Grade 1): Qualified for automotive
applications
Two high-speed CAN transceivers with
independent mode control
Meets the requirements of ISO 11898-2:2016
physical layer standard
Functional Safety-Capable
– Documentation available to aid in functional
safety system design
Support of classical CAN and optimized CAN FD
performance at 2, 5, and 8 Mbps
– Short and symmetrical propagation delays for
enhanced timing margin
I/O voltage range supports 1.7 V to 5.5 V
Support for 12-V and 24-V battery applications
Receiver common-mode input voltage: ±12 V
Protection features:
The
TCAN1046AV-Q1
and
TCAN1048AV-Q1
(TCAN104xAV-Q1) are dual, high-speed controller
area network (CAN) transceivers that meet the
physical layer requirements of the ISO 11898-2:2016
high-speed CAN specification.
The TCAN104xAV-Q1 transceivers support both
classical CAN and CAN FD networks up to 8
megabits per second (Mbps). The device includes
internal logic level translation via the VIO terminal to
allow for interfacing the transceiver I/O's directly to
1.8-V, 2.5-V, 3.3-V, or 5-V logic levels.
•
The two CAN channels support independent mode
control through the standby pins. Therefore, each
transceiver can be placed into a low-power state,
standby mode, without impacting the state of the other
CAN channel. While in standby mode, the device
supports remote wake-up pattern via the CAN bus
which is compliant to the ISO 11898-2:2016 defined
wake-up pattern (WUP).
•
•
•
•
– Bus fault protection: ±58 V
– Undervoltage protection
– TXD-dominant time-out (DTO)
•
Data rates down to 9.2 kbps
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
4.50 mm x 3.00 mm
8.65 mm x 3.91 mm
4.20 mm × 2 mm
– Thermal-shutdown protection (TSD)
Operating modes:
•
•
VSON (14)
– Normal mode
– Low power standby mode supporting remote
wake-up request
Optimized behavior when unpowered
– Bus and logic pins are high impedance (no load
to operating bus or application)
– Hot-plug capable: power-up and power-down
glitch-free operation on bus and RXD output
Junction temperatures from: –40°C to 150°C
Available in space-saving SOT-23, SOIC (14) and
leadless VSON (14) packages (4.5 mm x 3.0 mm)
with improved automated optical inspection (AOI)
capability
TCAN1046AV-Q1
SOIC (14)
SOT-23 (14)
VSON (14)
SOIC (14)
4.50 mm x 3.00 mm
8.95 mm x 3.91 mm
TCAN1048AV-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN
VOUT
1.8
V
/
2.5
Regulator
(e.g. TPSxxxx)
V / 3.3 V
•
•
VOUT
V Voltage
VIN
VIN
5
Regulator
(e.g. TPSxxxx)
VIO
11
VCC
VCC
3
CANH1
13
STB1/nSTB1
Port
x
14
RXD1
TXD1
RXD1
TXD1
4
1
CANL1
2 Applications
12
CAN FD Controller
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
TCAN1046AV-Q1
TCAN1048AV-Q1
•
Automotive and Transportation
– Body control modules
– Automotive gateway
Dual CAN FD
Transceiver
STB2/nSTB2
Port
x
8
CANH2
RXD2
TXD2
10
7
6
RXD2
TXD2
– Advanced driver assistance system (ADAS)
– Infotainment
CANL2
9
5
2
Optional:
Terminating
Node
GND1
GND2
Optional:
Filtering,
Transient and
ESD
Simplified Schematics
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN1046AV-Q1, TCAN1048AV-Q1
SLLSFL8A – JULY 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description Continued....................................................3
6 Device Comparison.........................................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings ....................................... 6
8.2 ESD Ratings .............................................................. 6
8.3 ESD Ratings — IEC Specifications ............................6
8.4 Recommended Operating Conditions ........................7
8.5 Thermal Characteristics .............................................7
8.6 Supply Characteristics ............................................... 8
8.7 Dissipation Ratings .................................................... 9
8.8 Electrical Characteristics ..........................................10
8.9 Switching Characteristics .........................................12
8.10 Typical Characteristics............................................14
9 Parameter Measurement Information..........................15
10 Detailed Description....................................................18
10.1 Overview.................................................................18
10.2 Functional Block Diagram.......................................19
10.3 Feature Description.................................................20
10.4 Device Functional Modes........................................24
11 Application and Implementation................................ 26
11.1 Application Information............................................26
11.2 Typical Application.................................................. 26
11.3 System Examples................................................... 29
12 Power Supply Recommendations..............................29
13 Layout...........................................................................30
13.1 Layout Guidelines................................................... 30
13.2 Layout Example...................................................... 30
14 Device and Documentation Support..........................31
14.1 Receiving Notification of Documentation Updates..31
14.2 Support Resources................................................. 31
14.3 Trademarks.............................................................31
14.4 Electrostatic Discharge Caution..............................31
14.5 Glossary..................................................................31
15 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (July 2021) to Revision A (December 2021)
Page
•
Changed the document status from: Advanced Information to: Production data............................................... 1
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5 Description Continued
The transceivers also include many protection and diagnostic features including thermal-shutdown (TSD), TXD-
dominant time-out (DTO), supply undervoltage detection, and bus fault protection up to ±58 V. The devices have
defined failsafe behavior in supply undervoltage or floating pin scenarios.
6 Device Comparison
Table 6-1. Device Comparison Table
Bus Fault Protection on both
Part Number
Low Voltage I/O Logic Support Standby (STB) Pin Mode
CAN Channels
±58 V
±58 V
TCAN1046AV-Q1
TCAN1048AV-Q1
Yes
Yes
Active-high
Active-low
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7 Pin Configuration and Functions
TXD1
GND1
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
STB1 / nSTB1
CANH1
CANL1
RXD1
GND2
TXD2
RXD2
VIO
CANH2
CANL2
8
STB2 / nSTB2
Not to scale
Figure 7-2. DYY Package, 14 Pin SOT-23, Top View
Figure 7-1. D Package, 14 Pin SOIC, Top View
TXD1
GND1
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
STB1 / nSTB1
CANH1
CANL1
Thermal
Pad
RXD1
GND2
TXD2
RXD2
VIO
CANH2
CANL2
8
STB2 / nSTB2
Not to scale
Figure 7-3. DMT Package, 14 Pin VSON, Top View
Table 7-1. Pin Functions
Pins
Type
Description
Name
TXD1
GND1
VCC
No.
1
Digital Input CAN transmit data input channel 1; integrated pull-up
2
GND
Ground connection
5-V supply voltage
3
Supply
RXD1
GND2
TXD2
RXD2
STB2
4
Digital Output CAN receive data output channel 1; tri-state when VIO < UVVIO
GND Ground connection
5
6
Digital Input CAN transmit data input channel 2; integrated pull-up
7
Digital Output CAN receive data output channel 2; tri-state when VIO < UVVIO
Standby input of channel 2 for mode control; integrated pull-up (TCAN1046AV–Q1)
8
Digital Input
Standby input of channel 2 for mode control; inverse logic with integrated pull-down
(TCAN1048AV–Q1)
nSTB2
CANL2
CANH2
VIO
9
Bus IO
Bus IO
Supply
Bus IO
Low-level CAN bus channel 2 input/output line
High-level CAN bus channel 2 input/output line
I/O supply voltage
10
11
12
CANL1
Low-level CAN bus channel 1 input/output line
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Table 7-1. Pin Functions (continued)
Pins
Type
Description
Name
CANH1
STB1
No.
13
Bus IO
High-level CAN bus channel 1 input/output line
Standby input of channel 1 for mode control; integrated pull-up (TCAN1046AV–Q1)
14
Digital Input
—
Standby input of channel 1 for mode control; inverse logic with integrated pull-down
(TCAN1048AV–Q1)
nSTB1
Thermal Pad (VSON only)
Connect the thermal pad to the printed circuit board (PCB) ground plane for thermal relief
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8 Specifications
8.1 Absolute Maximum Ratings
(1) (2)
MIN
–0.3
–0.3
MAX
UNIT
V
VCC
VIO
Supply voltage
6
6
Supply voltage I/O level shifter
V
CAN Bus I/O voltage
CANH1, CANL1, CANH2, CANL2
VBUS
–58
58
V
VDIFF
Max differential voltage between CANHx and CANLx
Logic input terminal voltage
RXDx output terminal voltage range
RXDx output current
–45
–0.3
–0.3
–8
45
6
V
V
VLogic_Input
VRXDx
IO(RXDx)
TJ
6
V
8
mA
°C
°C
Junction temperature
–40
–65
165
150
TSTG
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
8.2 ESD Ratings
VALUE
UNIT
HBM classification level 3A for
all pins
±4000
V
Human-body model (HBM), per AEC Q100-002(1)
HBM classification level 3B
for global pins CANHx and
CANLx with respect to GND
VESD
Electrostatic discharge
±10000
±750
V
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 ESD Ratings — IEC Specifications
VALUE
UNIT
Unpowered contact discharge
per ISO 10605 (1)
±8000
±8000
V
V
V
SAE J2962-2 per ISO 10605
VESD System level Electrostatic discharge
Powered Contact Discharge
(2)
SAE J2962-2 per ISO 10605
Powered Air Discharge (2)
±15000
CAN bus terminals to GND
CANH1, CANL1, CANH2, CANL2
Pulse 1
–100
75
V
V
V
V
V
Pulse 2a
Transient voltage per ISO 7637-2(3)
VTran
Pulse 3a
–150
100
±30
Pulse 3b
Transient voltage per ISO 7637-3(4)
DCC slow transient pulse
(1) Tested according to IEC 62228-3:2019 CAN Transceivers
(2) Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent 3rd party, EMC report available upon request.
(3) Tested according to IEC 62228-3:2019 CAN Transceivers
(4) Tested according to SAE J2962-2
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8.4 Recommended Operating Conditions
MIN
4.5
NOM
MAX
5.5
UNIT
V
VCC
Supply voltage
5
VIO
Supply voltage for I/O level shifter
RXDx terminal high-level output current
RXDx terminal low-level output current
Operating junction temperature
1.7
5.5
V
IOH(RXDx)
IOL(RXDx)
TJ
–1.5
mA
mA
℃
1.5
-40
150
8.5 Thermal Characteristics
TCAN1046AV-Q1 / TCAN1048AV-Q1
DYY (SOT)
THERMAL METRIC(1)
UNIT
D (SOIC)
DMT (VSON)
RθJA
Junction-to-ambient thermal resistance
75.8
35.8
37.4
6.6
87.2
35.2
31.6
11.2
31.5
–
38.1
38.7
15.0
2.0
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
37.0
–
15.0
5.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.6 Supply Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = 0 V, TXDy = VIO
50
77.5
mA
RL1 = RL2 = 60 Ω, CL = open;
See Figure 9-1
Dominant
One Channel(1)
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = 0 V, TXDy = VIO
55
95
87.5
140
160
15
mA
mA
mA
mA
RL1 = RL2 = 50 Ω, CL = open;
See Figure 9-1
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = TXDy = 0 V
RL1 = RL2 = 60 Ω, CL = open;
See Figure 9-1
Dominant
Two channels(1)
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = TXDy = 0 V
RL1 = RL2 = 50 Ω, CL = open;
See Figure 9-1
Dominant
100
10
Two channels(1)
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = TXDy = VIO
RL1 = RL2 = 50 Ω, CL = open;
See Figure 9-1
Supply current
Normal mode
Recessive
Two channels
ICC
TCAN1046AV: STB1 = STB2 = 0 V
CANx dominant TCAN1048AV: nSTB1 = nSTB2 = VIO
with bus fault
CANy
TXDx = TXDy = VIO
90
137.5
210
mA
mA
CANHx = CANLx = ±25 V
RLx = open, RLy = 50 Ω, CL = open;
See Figure 9-1
recessive(1) (2)
TCAN1046AV: STB1 = STB2 = 0 V
CANx dominant TCAN1048AV: nSTB1 = nSTB2 = VIO
with bus fault
CANy
TXDx = TXDy = 0 V
135
CANHx = CANLx = ±25 V
RLx = open, RLy = 50 Ω, CL = open;
See Figure 9-1
dominant(1) (2)
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
CANx and CANy TXDx = TXDy = 0 V
dominant with
CANH1 = CANL1 = ±25 V
CANH2 = CANL2 = ±25 V
RLx = RLy = open, CL = open;
See Figure 9-1
170
0.4
260
mA
µA
bus fault(1) (2)
TCAN1046AV: STB1 = STB2 = VIO
TCAN1048AV: nSTB1 = nSTB2 = 0 V
TXDx = TXDy = VIO
Supply current
Standby mode
3
RLx = RLy = 60 Ω, CL = open
See Figure 9-1
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8.6 Supply Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = 0 V, TXDy = VIO
RLx = RLy = 60 Ω, CL = open
RXD1 and RXD2 floating
Dominant
150
350
µA
One channel(1)
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = TXDy = 0 V
RLx = RLy = 60 Ω, CL = open
RXD1 and RXD2 floating
I/O supply current
Normal mode
Dominant
255
50
600
100
30
µA
µA
µA
Two channels(1)
IIO
TCAN1046AV: STB1 = STB2 = 0 V
TCAN1048AV: nSTB1 = nSTB2 = VIO
TXDx = TXDy = VIO
RLx = RLy = 60 Ω, CL = open
RXD1 and RXD2 floating
Recessive
Two channels(1)
TCAN1046AV: STB1 = STB2 = VIO
TCAN1048AV: nSTB1 = nSTB2 = 0 V
TXDx = TXDy = VIO
RLx = RLy = 60 Ω, CL = open
RXD1 and RXD2 floating
I/O supply current
Standby mode
17
Rising undervoltage detection on VCC
Falling undervoltage detection on VCC
4.2
4
4.4
V
V
UVCC
3.5
1.4
4.25
VHYS(UVCC) Hysteresis voltage on UVCC
200
1.56
1.51
40
mV
V
Rising undervoltage detection on VIO
UVVIO
1.65
1.59
Falling undervoltage detection on VIO
V
VHYS(UVIO)
Hysteresis voltage on UVIO
mV
(1) TXD1 and TXD2 are interchangeable for TXDx and TXDy
(2) CAN1 and CAN2 are interchangeable for CANx and CANy
8.7 Dissipation Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 5 V, VIO = 1.8 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
95
95
mW
VCC = 5 V, VIO = 3.3 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
mW
mW
mW
mW
VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD
input = 250 kHz 50% duty cycle square wave,
CL_RXD = 15 pF
95
One channel average power dissipation
Normal mode
PD
VCC = 5.5 V, VIO = 1.8 V, TJ= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
120
120
120
VCC = 5.5 V, VIO = 3.3 V, TJ= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
VCC = 5.5 V, VIO = 5 V, TJ= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
mW
°C
TTSD
Thermal shutdown temperature
175
195
12
210
TTSD(HYS) Thermal shutdown hysteresis
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8.8 Electrical Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted), CAN electrical parameters apply
to both channels
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Driver Electrical Characteristics
CANH
CANL
STB = 0 V / nSTB = VIO
TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open;
See Figure 9-2 and Figure 10-3
2.75
0.5
4.5
V
V
Dominant output voltage
Normal mode
VO(DOM)
2.25
STB = 0 V / nSTB = VIO
TXD = VIO
RL = open (no load);
See Figure 9-2 and Figure 10-3
Recessive output voltage
Normal mode
VO(REC)
CANH and CANL
2
0.5 VCC
3
V
STB = 0 V / nSTB = VIO
Driver symmetry
(VO(CANH) + VO(CANL))/VCC
TXD = 250 kHz, 1 MHz, 2.5 MHz
RL = 60 Ω, CSPLIT = 4.7 nF, CL = open;
See Figure 9-2 and Figure 10-3
VSYM
0.9
–400
1.5
1.1 V/V
400 mV
STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = open;
See Figure 9-2 and Figure 10-3
DC output symmetry
(VCC - VO(CANH) - VO(CANL)
VSYM_DC
)
STB = 0 V / nSTB = VIO
TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open;
See Figure 9-2 and Figure 10-3
3
3.3
5
V
V
V
STB = 0 V / nSTB = VIO
TXD = 0 V
45 Ω ≤ RL ≤ 70 Ω, CL = open;
See Figure 9-2 and Figure 10-3
Differential output voltage
Normal mode
Dominant
VOD(DOM)
CANH - CANL
1.4
1.5
STB = 0 V / nSTB = VIO
TXD = 0 V
RL = 2240 Ω, CL = open;
See Figure 9-2 and Figure 10-3
STB = 0 V / nSTB = VIO
TXD = VIO
RL = 60 Ω, CL = open;
See Figure 9-2 and Figure 10-3
–120
–50
12 mV
50 mV
Differential output voltage
Normal mode
VOD(REC)
CANH - CANL
STB = 0 V / nSTB = VIO
TXD = VIO
RL = open, CL = open;
See Figure 9-2 and Figure 10-3
Recessive
CANH
-0.1
-0.1
-0.2
0.1
0.1
0.2
V
V
V
STB = VIO / nSTB = 0 V
RL = open;
See Figure 9-2 and Figure 10-3
Bus output voltage
Standby mode
VO(STB)
CANL
CANH - CANL
STB = 0 V / nSTB = VIO
TXD = 0 V
V(CANH) = -15 V to 40 V, CANL = open;
See Figure 9-8 and Figure 10-3
–115
mA
Short-circuit steady-state output current,
IOS(SS_DOM)
dominant
Normal mode
STB = 0 V / nSTB = VIO
TXD = 0 V
V(CAN_L) = -15 V to 40 V, CANH = open;
See Figure 9-8 and Figure 10-3
115 mA
STB = 0 V / nSTB = VIO
TXD = VIO
–27 V ≤ VBUS ≤ 32 V, where VBUS = CANH
= CANL;
Short-circuit steady-state output current,
recessive
Normal mode
IOS(SS_REC)
–5
5
mA
See Figure 9-8 and Figure 10-3
Receiver Electrical Characteristics
STB = 0 V / nSTB = VIO
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Input threshold voltage
Normal mode
VIT
500
400
900 mV
STB = VIO / nSTB = 0 V
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Input threshold
VIT(STB)
1150 mV
Standby mode
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8.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted), CAN electrical parameters apply
to both channels
PARAMETER
TEST CONDITIONS
STB = 0 V / nSTB = VIO
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
MIN
TYP
MAX UNIT
Dominant state differential input voltage range
Normal mode
VDOM
0.9
9
0.5
9
V
V
STB = 0 V / nSTB = VIO
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Recessive state differential input voltage range
Normal mode
VREC
-4
1.15
-4
STB = VIO / nSTB = 0 V
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Dominant state differential input voltage range
Standby mode
VDOM(STB)
VREC(STB)
VHYS
V
STB = VIO / nSTB = 0 V
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Recessive state differential input voltage range
Standby mode
0.4
V
STB = 0 V / nSTB = VIO
-12 V ≤ VCM ≤ 12 V;
See Figure 9-3 and Table 10-5
Hysteresis voltage for input threshold
Normal mode
115
mV
Common mode range
Normal and standby modes
VCM
See Figure 9-3 and Table 10-5
–12
12
5
V
Unpowered bus input leakage current
(measured individually for each channel)
ILKG(IOFF)
CANH = CANL = 5 V, VCC = VIO = GND
µA
CI
Input capacitance to ground (CANH or CANL)
Differential input capacitance
20 pF
10 pF
90 kΩ
TXD = VIO
CID
RID
Differential input resistance
40
20
STB = 0 V / nSTB = VIO
TXD = VIO
-12 V ≤ VCM ≤ 12 V
Single ended input resistance
(CANH or CANL)
RIN
45 kΩ
Input resistance matching
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
RIN(M)
V(CAN_H) = V(CAN_L) = 5 V
–1
1
%
TXD Terminal (CAN Transmit Data Input)
VIH
VIL
IIH
High-level input voltage
0.7 VIO
V
V
Low-level input voltage
0.3 VIO
1
High-level input leakage current
TXD = VCC = VIO = 5.5 V
–2.5
0
µA
TXD = 0 V
VCC= VIO = 5.5 V
IIL
Low-level input leakage current
–200
-100
–20 µA
TXD = 5.5 V
VCC= VIO = 0 V
ILKG(OFF)
CI
Unpowered leakage current
Input capacitance
–1
0
5
1
µA
pF
VIN = 0.4×sin(2×π×2×106×t)+2.5 V
RXD Terminal (CAN Receive Data Output)
IO = –1.5 mA
See Figure 9-3
VOH
High-level output voltage
Low-level output voltage
Unpowered leakage current
0.8 VIO
V
V
IO = 1.5mA
See Figure 9-3
VOL
0.2 VIO
1
RXD = 5.5 V
VCC = VIO = 0 V
ILKG(OFF)
–1
0
µA
STB / nSTB Terminal (Standby Mode Input)
VIH
VIL
High-level input voltage
Low-level input voltage
0.7 VIO
V
V
0.3 VIO
2
TCAN1046AV high-level input leakage current
STB
IIH
IIL
IIH
IIL
STB = VCC = VIO = 5.5 V
–2
–20
2
µA
TCAN1046AV low-level input leakage current
STB
STB = 0 V
VCC = VIO = 5.5 V,
–2 µA
25 µA
TCAN1048AV high-level input leakage current
nSTB
nSTB = VCC = VIO = 5.5 V
TCAN1048AV low-level input leakage current
nSTB
nSTB = 0 V
VCC = VIO = 5.5 V,
-2
2
µA
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8.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted), CAN electrical parameters apply
to both channels
PARAMETER
TEST CONDITIONS
STB = 5.5V
MIN
TYP
MAX UNIT
TCAN1046AV unpowered leakage current
–1
1
1
µA
µA
VCC = VIO = 0 V
ILKG(OFF)
nSTB = 0 V
VCC = VIO = 0 V
TCAN1048AV unpowered leakage current
–1
8.9 Switching Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted); Parameters apply to both CAN
channels
PARAMETER
TEST CONDITIONS
MIN
TYP
125
165
150
180
MAX
210
255
210
UNIT
Device Switching Characteristics
STB = 0 V / nSTB = VIO
VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant
tPROP(LOOP1)
tPROP(LOOP1)
tPROP(LOOP2)
ns
STB = 0 V / nSTB = VIO
VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant
ns
STB = 0 V / nSTB = VIO
VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive
ns
STB = 0 V / nSTB = VIO
VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive
tPROP(LOOP2)
255
20
ns
µs
Mode change time, from normal to standby or from
standby to normal
tMODE
See Figure 9-5 and Figure 9-6
See Figure 10-5
tWK_FILTER
Filter time for a valid wake-up pattern
Bus wake-up timeout
0.5
0.8
1.8
6
µs
tWK_TIMEOUT
ms
Driver Switching Characteristics
Propagation delay time, high TXD to driver
tpHR
80
70
ns
ns
recessive (dominant to recessive)
Propagation delay time, low TXD to driver dominant
(recessive to dominant)
tpLD
STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF;
See Figure 9-2
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
14
28
50
ns
ns
ns
Differential output signal rise time
Differential output signal fall time
tF
STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF;
See Figure 9-7
tTXD_DTO
Dominant timeout
1.2
4.0
ms
Receiver Switching Characteristics
Propagation delay time, bus recessive input to high
tpRH
81
66
ns
ns
output (dominant to recessive)
STB = 0 V / nSTB = VIO
CL(RXD) = 15 pF
See Figure 9-3
Propagation delay time, bus dominant input to low
output (recessive to dominant)
tpDL
tR
tF
RXD output signal rise time
RXD output signal fall time
10
10
ns
ns
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8.9 Switching Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted); Parameters apply to both CAN
channels
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FD Timing Characteristics
Bit time on CAN bus output pins
tBIT(TXD) = 500 ns
450
160
85
525
205
130
540
210
135
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bit time on CAN bus output pins
tBIT(TXD) = 200 ns
tBIT(BUS)
tBIT(RXD)
tREC
Bit time on CAN bus output pins
tBIT(TXD) = 125 ns(1)
Bit time on RXD output pins
tBIT(TXD) = 500 ns
410
130
75
STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
Bit time on RXD output pins
tBIT(TXD) = 200 ns
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-4
;
Bit time on RXD output pins
tBIT(TXD) = 125 ns(1)
Receiver timing symmetry
tBIT(TXD) = 500 ns
-50
-40
-40
Receiver timing symmetry
tBIT(TXD) = 200 ns
10
Receiver timing symmetry
tBIT(TXD) = 125 ns(1)
10
(1) Measured during characterization and not an ISO 11898-2:2016 parameter.
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8.10 Typical Characteristics
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
VCC (V)
Temperature (èC)
TCAN
TCAN
A.
Temp = 25 °C
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 8-2. VOD(DOM) Over VCC VOD(DOM) vs VCC Channel 1 &
Channel 2
Figure 8-1. VOD(DOM) Over Temperature VOD(DOM) vs VCC Channel
1 & Channel 2
2
1.5
1
20
18
16
14
12
10
0.5
0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (èC)
Temperature (èC)
ICC_
TCAN
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 8-3. ICC Standby vs Temperature
Figure 8-4. IIO Standby vs Temperature
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9 Parameter Measurement Information
CANH
TXD
RL
CL
CANL
Figure 9-1. ICC Test Circuit
RCM
CANH
50%
50%
TXD
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpLD
tpHR
90%
10%
0V
CANL
RCM
0.9V
VO(CANL)
VOD
0.5V
tR
tF
Figure 9-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
VO
CL_RXD
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
Figure 9-3. Receiver Test Circuit and Measurement
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TXD
VI
70%
tLOOP1
30%
30%
CANH
0 V
TXD
STB
VI
RL
CL
tBIT(TXD)
5 x tBIT(TXD)
CANL
tBIT(BUS)
0 V
900 mV
500 mV
RXD
+
VDIFF
VO
CL_RXD
œ
RXD
VOH
70%
30%
VOL
tBIT(RXD)
tLOOP2
Figure 9-4. Transmitter and Receiver Timing Test Circuit and Measurement
CANH
VIH
TXD
CL
0V
RL
STB
50%
CANL
STB
VI
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
Figure 9-5. TCAN1046AV tMODE Test Circuit and Measurement
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CANH
VIH
TXD
CL
0V
RL
nSTB
50%
CANL
0V
nSTB
VI
tMODE
VOH
RXD
RXD
50%
VO
CL_RXD
VOL
Figure 9-6. TCAN1048AV tMODE Test Circuit and Measurement
VIH
0V
CANH
TXD
TXD
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 9-7. TXD Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 9-8. Driver Short-Circuit Current Test and Measurement
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10 Detailed Description
10.1 Overview
The TCAN104xAV-Q1 devices meet or exceed the specifications of the ISO 11898-2:2016 high speed CAN
(Controller Area Network) physical layer standard. The devices have been certified to the requirements of ISO
11898-2:2016 physical layer requirements according to the GIFT/ICT high speed CAN test specification. The
transceivers provide a number of different protection features making them ideal for the stringent automotive
system requirements while also supporting CAN FD data rates up to 8 Mbps.
The TCAN104xAV-Q1 support the following CAN standards:
•
CAN transceiver physical layer standards:
– ISO 11898-2:2016 High speed medium access unit
– ISO 11898-5:2007 High speed medium access unit with low-power mode
– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps
– SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps
– SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps
– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps
– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps
•
•
EMC requirements:
– IEC 62228-3 EMC evaluation of transceivers - CAN transceivers
– VeLIO (Vehicle LAN Interoperability and Optimization) CAN and CAN-FD Transceiver Requirements
– SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
Conformance test requirements:
– ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed
medium access unit conformance test plan
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10.2 Functional Block Diagram
VCC
VIO
VCC
3
VIO
11
3
11
VCC
VCC
VIO
VIO
13 CANH1
13 CANH1
TSD
TSD
Dominant
time-out
Dominant
time-out
TXD1
1
TXD1
1
12 CANL1
12 CANL1
VIO
STB1 14
Mode Select
nSTB1 14
Mode Select
UVP
UVP
VIO
VIO
MUX
MUX
4
Logic Output
4
Logic Output
RXD1
RXD1
VIO
VIO
WUP Monitor
WUP Monitor
Low Power Receiver
Low Power Receiver
VCC
VCC
VIO
VIO
10 CANH2
10 CANH2
TSD
TSD
Dominant
time-out
Dominant
time-out
TXD2
STB2
6
8
TXD2
6
8
9
CANL2
9
CANL2
VIO
Mode Select
nSTB2
Mode Select
UVP
UVP
VIO
VIO
MUX
MUX
RXD2
7
Logic Output
RXD2
7
Logic Output
VIO
VIO
WUP Monitor
WUP Monitor
Low Power Receiver
Low Power Receiver
2
5
2
5
GND1
GND2
GND1
GND2
Figure 10-1. TCAN1046AV-Q1 (left image with pull-up on STB) and TCAN1048AV-Q1 (right image with
pull-down on nSTB) Block Diagrams
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10.3 Feature Description
10.3.1 Pin Description
10.3.1.1 TXD1 and TXD2
TXD1 and TXD2 are the logic-level signals, referenced to VIO, from a CAN controller to the device.
10.3.1.2 GND1 and GND2
GND1 and GND2 are ground pins of the transceiver, both must be connected to the PCB ground.
10.3.1.3 VCC
VCC provides the 5-V power supply to both the CAN channels.
10.3.1.4 RXD1 and RXD2
RXD1 and RXD2 are the logic-level signals, referenced to VIO, from the TCAN104xAV-Q1 to a CAN controller.
These pins are only driven once VIO is present.
10.3.1.5 VIO
The VIO pin provides the digital I/O voltage to match the CAN controller voltage thus avoiding the requirement for
a level shifter. The VIO pin supports voltages from 1.7 V to 5.5 V providing the widest range of controller support.
10.3.1.6 CANH and CANL
The CAN high and CAN low are differential bus pins of the two integrated CAN channels. The CANH and CANL
pins are connected to the CAN transceiver and the low-voltage WUP CAN receiver.
10.3.1.7 STB1, STB2, nSTB1, and nSTB2 (Standby)
The STB1, STB2, nSTB1, and nSTB2 pins are input pins used for mode control of the transceiver.
The TCAN1046AV-Q1 implements STB1 and STB2 which can be supplied from either the system processor or
from a static system voltage source. If normal mode is the only intended mode of operation than the STB pins
can be tied directly to GND.
The TCAN1048AV-Q1 implements nSTB1 and nSTB2 which can be supplied from either the system processor
or from a static system voltage source. If normal mode is the only intended mode of operation, the nSTB pins
can be tied directly to the VIO voltage source.
10.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 10-2 and Figure 10-3.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the
TXD1, TXD2, RXD1 and RXD2 pins. A recessive bus state occurs when the bus is biased to VCC/2 via the
high-resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the TXD1, TXD2,
RXD1 and RXD2 pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
The TCAN104xAV-Q1 transceiver implements a low-power standby (STB or nSTB) mode which enables a third
bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the
receiver. See Figure 10-2 and Figure 10-3.
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Normal Mode
Standby Mode
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
Figure 10-2. Bus States
CANH
2.5V
GND
A
B
RXD
Bias
Unit
CANL
A. Normal Mode
B. Standby Mode
Figure 10-3. Simplified Recessive Common Mode Bias Unit and Receiver
10.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin which clears the dominant time out. The receiver remains active and biased to VCC/2. The
RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using Equation 1.
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
Figure 10-4. Example Timing Diagram for TXD Dominant Timeout
10.3.4 CAN Bus Short Circuit Current Limiting
The TCAN104xAV-Q1 has several protection features that limit the short circuit current when a CAN bus line
is shorted. The features include CAN driver current limiting in the dominant and recessive states and TXD
dominant state timeout which prevents permanently having the higher short-circuit current of a dominant state
in case of a system fault. During CAN communication, the bus switches between the dominant and recessive
states, thus the short-circuit current may be viewed as either the current during each bus state or as a DC
average current. When selecting termination resistors or a common-mode choke for the CAN design the average
power rating, IOS(AVG), should be used. The percentage dominant is limited by the TXD DTO and the CAN
protocol which has forced state changes and recessive bits due to bit stuffing, control fields, and interframe
space. These provides for a minimum amount of recessive time on the bus even if the data field contains a high
percentage of dominant bits.
The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short-circuit currents. The average short-circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC
]
(2)
Where:
•
•
•
•
•
•
•
IOS(AVG) is the average short-circuit current
% Transmit is the percentage the node is transmitting CAN messages
% Receive is the percentage the node is receiving CAN messages
% REC_Bits is the percentage of recessive bits in the transmitted CAN messages
% DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short-circuit current
IOS(SS)_DOM is the dominant steady state short- circuit current
The short-circuit current and the possible fault cases of the network should be considered when sizing the power
supply used to generate the transceivers VCC supply.
10.3.5 Thermal Shutdown (TSD)
If the junction temperature of the TCAN104xAV-Q1 exceeds the thermal shutdown threshold, TTSD, the device
turns off the CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is
cleared when the junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2
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during a TSD fault and the receiver to RXD path remains operational. The TCAN104xAV-Q1 TSD circuit includes
hysteresis which prevents the CAN driver output from oscillating during a TSD fault.
10.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 10-1. Undervoltage Lockout - TCAN104xAV-Q1
VCC
VIO
DEVICE STATE
BUS
RXD PIN
> UVVCC
> UVVIO
Normal
Per TXD
Mirrors bus
High impedance
Weak pull-down to
ground
STB = VIO: Standby mode;
TCAN1046AV-Q1
VIO: Remote wake request(1)
STB = GND: Protected mode;
TCAN1046AV-Q1
High impedance
High impedance
Recessive
Recessive
< UVVCC
> UVVIO
nSTB = VIO: Protected mode;
TCAN1048AV-Q1
High impedance
Weak pull-down to
ground
nSTB = GND: Standby mode;
TCAN1048AV-Q1
VIO: Remote wake request(1)
> UVVCC
< UVVCC
< UVVIO
< UVVIO
Protected
Protected
High impedance
High impedance
High impedance
High impedance
(1) See Section 10.4.3.1
Once the undervoltage condition is cleared and tMODE has expired, the TCAN104xAV-Q1 transitions to normal
mode and the host controller can send and receive CAN traffic.
10.3.7 Unpowered Device
The TCAN104xAV-Q1 is designed to be an ideal passive or no load to the CAN bus if the device is unpowered.
The bus pins were designed to have low leakage currents when the device is unpowered, and do not load
the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational.
The logic pins also have low leakage currents when the device is unpowered, and do not load other circuits
which may remain powered.
10.3.8 Floating pins
The TCAN104xAV-Q1 has internal pull-ups or pull-downs on critical pins which place the device into known
states if the pin floats. This internal bias should not be relied upon by design though, especially in noisy
environments, but instead should be considered a failsafe protection feature.
When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be
chosen. This specifies that the TXD output of the CAN controller maintains acceptable bit time to the input of the
CAN transceiver. See Table 10-2 for details on pin bias conditions.
Table 10-2. Pin Bias
Pin
Pull-up or Pull-down
Comment
Weakly biases TXD1 and TXD2 towards recessive to prevent bus
blockage or TXD DTO triggering
TXD1 and TXD2
Pull-up
Weakly biases STB1 and STB2 towards low-power standby mode to
prevent excessive system power; TCAN1046AV-Q1 only
STB1 and STB2
Pull-up
Weakly biases nSTB1 and nSTB2 towards low-power standby mode
to prevent excessive system power; TCAN1048AV-Q1 only
nSTB1 and nSTB2
Pull-down
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10.4 Device Functional Modes
10.4.1 Operating Modes
The TCAN104xAV-Q1 has two main operating modes; normal mode and standby mode. Operating mode
selection is made by applying a high or low level to the STB or nSTB pins on the TCAN1046A or TCAN1048A
device respectively.
Table 10-3. Operating Modes
STB
nSTB
Low
Device Mode
Standby mode
Normal Mode
Driver
Disabled
Enabled
Receiver
RXD Pin
High (recessive) until valid
WUP is received
See section Section
10.4.3.1
Low-power receiver with
bus monitor enable
High
Low
High
Enabled
Mirrors bus state
10.4.2 Normal Mode
This is the normal operating mode of the TCAN104xAV-Q1. The CAN driver and receiver are fully operational
and CAN communication is bi-directional. The driver is translating a digital input on the TXD1 and TXD2 inputs
to a differential output on the CANH1, CANL1 and CANH2, CANL2 bus pins. The receiver is translating the
differential signal from CANH1, CANL1 and CANH2, CANL2 to a digital output on the RXD1 and RXD2 outputs.
10.4.3 Standby Mode
This is the low-power mode of the TCAN104xAV-Q1. The CAN driver and main receiver are switched off and
bi-directional CAN communication is not possible. The low-power receiver and bus monitor circuits are enabled
to allow for RXD wake-up requests via the CAN bus. A wake-up request is output to RXD1 or RXD2 depending
on the channel which receives the WUP as shown in Figure 10-5. The local CAN protocol controller should
monitor RXD1 and RXD2 for transitions (high-to-low) and reactivate the device to normal mode by pulling the
STB1 and STB2 pins low or the nSTB1 and nSTB2 pins high. The CAN bus pins are weakly pulled to GND in
this mode; see Figure 10-2 and Figure 10-3.
In standby mode, only the VIO supply is required; therefore. the VCC may be switched off for additional system
level current savings.
10.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
The TCAN104xAV-Q1 supports a remote wake-up request that is used to indicate to the host controller that the
bus is active and the node should return to normal operation.
The device uses the multiple filtered dominant wake-up pattern (WUP) from the ISO 11898-2:2016 standard to
qualify bus activity. Once a valid WUP has been received, the wake request is indicated to the controller by a
falling edge and low period corresponding to a filtered dominant on the RXD output of the TCAN104xAV-Q1.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and drives the RXD output low
every time an additional filtered dominant signal is received from the bus.
For a dominant or recessive to be considered filtered, the bus must be in that state for more than the
tWK_FILTER time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake-up request may be
generated. Bus state times greater than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is always generated. See Figure 10-5 for the timing diagram of the wake-up pattern.
The pattern and tWK_FILTER time used for the WUP prevents noise and bus stuck dominant faults from causing
false wake-up requests while allowing any valid message to initiate a wake-up request.
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The ISO 11898-2:2016 standard has defined times for a short and long wake-up filter time. The tWK_FILTER timing
for the device has been picked to be within the minimum and maximum values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back-to-back bit times at 1 Mbps triggers the
filter in either bus state. Any CAN frame at 500 kbps or less would contain a valid WUP.
For an additional layer of robustness and to prevent false wake-ups, the device implements a wake-up timeout
feature. For a remote wake-up event to successfully occur, the entire WUP must be received within the timeout
value t ≤ tWK_TIMEOUT. If not, the internal logic is reset and the transceiver remains in its current state without
waking up. The full pattern must then be transmitted again, conforming to the constraints mentioned in this
section. See Figure 10-5 for the timing diagram of the wake-up pattern with wake timeout feature.
Bus Wake via RXD
Wake Up Pattern (WUP) received in t < tWK_Timeout
Request
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
RXD
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
Figure 10-5. Wake-Up Pattern (WUP) with tWK_TIMEOUT
10.4.4 Driver and Receiver Function
Table 10-4. Driver Function Table
Bus Outputs
Device Mode
TXD Input
Driven Bus State(2)
CANH
CANL
Low
High or open
X(1)
High
Low
Dominant
Normal
High impedance
High impedance
High impedance
High impedance
Biased recessive
Biased to ground
Standby
(1) X = irrelevant
(2) For bus state and bias see Figure 10-2 and Figure 10-3
Table 10-5. Receiver Function Table Normal and Standby Mode
CAN Differential Inputs
VID = VCANH – VCANL
Device Mode
Bus State
RXD Pin
VID ≥ 0.9 V
0.5 V < VID < 0.9 V
VID ≤ 0.5 V
Dominant
Undefined
Recessive
Dominant
Undefined
Recessive
Open
Low
Undefined
High
Normal
VID ≥ 1.15 V
High
Low if a remote wake event
occurred
0.4 V < VID < 1.15 V
VID ≤ 0.4 V
Standby
Any
See Figure 10-5
Open (VID ≈ 0 V)
High
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11 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
11.1 Application Information
11.2 Typical Application
Figure 11-1 shows a typical configuration for 5 V system using the TCAN104xAV-Q1. The bus termination is
shown for illustrative purposes.
VIN
VOUT
VIN
5-V Voltage
Regulator
(e.g. TPSxxxx)
VCC
VIO
11
VCC
3
CANH1
13
STB1/nSTB1
Port x
14
RXD1
TXD1
RXD1
TXD1
4
1
CANL1
12
CAN FD Controller
Optional:
Filtering,
Transient and
ESD
TCAN1046AV-Q1
TCAN1048AV-Q1
Optional:
Terminating
Node
Dual CAN FD
Transceiver
STB2/nSTB2
8
Port x
CANH2
RXD2
TXD2
10
7
6
RXD2
TXD2
CANL2
9
2
5
GND1
GND2
Optional:
Filtering,
Transient and
ESD
Optional:
Terminating
Node
Figure 11-1. Transceiver Application Using 5 V I/O Connections
11.2.1 Design Requirements
11.2.1.1 CAN Termination
Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating
node. If filtering and stabilization of the common-mode voltage of the bus is desired, then split termination may
be used, see Figure 11-2. Split termination improves the electromagnetic emissions behavior of the network by
filtering higher-frequency common-mode noise that may be present on the differential signal lines.
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Standard Termination
Split Termination
CANH
CANH
RTERM/2
RTERM
TCAN Transceiver
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 11-2. CAN Bus Termination Concepts
11.2.2 Detailed Design Procedures
11.2.2.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN104xAV-Q1.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification, the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output
must be greater than 1.5 V. The TCAN104xAV-Q1 family is specified to meet the 1.5-V requirement down to
50 Ω and is specified to meet 1.4-V differential output at 45-Ω bus load. The differential input resistance of
the TCAN104xAV-Q1 is a minimum of 40 kΩ. If 100 TCAN104xAV-Q1 transceivers are in parallel on a bus,
this is equivalent to a 400-Ω differential load in parallel with the nominal 60-Ω bus termination which gives a
total bus load of approximately 52 Ω. Therefore, the TCAN104xAV-Q1family theoretically supports over 100
transceivers on a single bus segment. However, for a CAN network design margin must be given for signal
loss across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal
integrity thus a practical maximum number of nodes is often lower. Bus length may also be extended beyond
40 meters by careful system design and data rate tradeoffs. For example, CANopen network design guidelines
allow the network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes and
significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility,
the CAN network system, a good network design is required for robust network operation.
Please refer to the application report SLLA270: Controller Area Network Physical layer requirements. This
document discusses in detail all system design physical layer parameters.
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Node 1
Node 2
Node 3
Node n
(with termination)
System Contoller
System Controller
System Controller
System Controller
CAN FD
Controller
CAN FD
CAN FD
CAN FD
Controller
Controller
Controller
TCAN1048AV-Q1
TCAN1046AV-Q1
TCAN1044A-Q1
TCAN1043AV-Q1
R
TERM
R
TERM
Figure 11-3. Typical CAN Bus
11.2.3 Application Curves
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
A.
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 11-4. tPROP(LOOP1) TRX1 & TRX2
Figure 11-5. tPROP(LOOP2) TRX1 & TRX2
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11.3 System Examples
The CAN transceiver is typically used in applications with a host controller or FPGA that includes the link layer
portion of the CAN protocol. A 1.8 V, 2.5 V, or 3.3 V application is shown in Figure 11-6. The bus termination is
shown for illustrative purposes.
VIN
VOUT
1.8 V / 2.5 V / 3.3 V
Regulator
(e.g. TPSxxxx)
VOUT
5 V Voltage
VIN
VIN
Regulator
(e.g. TPSxxxx)
VIO
11
VCC
VCC
3
CANH1
13
STB1/nSTB1
Port x
14
RXD1
TXD1
RXD1
TXD1
4
1
CANL1
12
CAN FD Controller
Optional:
Terminating
Node
Optional:
Filtering,
TCAN1046AV-Q1
TCAN1048AV-Q1
Transient and
ESD
Dual CAN FD
Transceiver
STB2/nSTB2
8
Port x
CANH2
RXD2
TXD2
10
7
6
RXD2
TXD2
CANL2
9
5
2
Optional:
Terminating
Node
GND1
GND2
Optional:
Filtering,
Transient and
ESD
Figure 11-6. Transceiver Application Using 1.8 V, 2.5 V, 3.3 V I/O Connections
12 Power Supply Recommendations
The TCAN104xAV-Q1 device is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The device has an I/O level shifting supply input, VIO, designed for a range between 1.8 V and 5.5 V.
Both supply inputs must be well regulated. A decoupling capacitor, typically 100 nF, should be placed near the
CAN transceiver's main VCC and VIO supply pins in addition to bypass capacitors.
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13 Layout
Robust and reliable CAN node design may require special layout techniques depending on the application
and automotive design requirements. Since transient disturbances have high frequency content and a wide
bandwidth, high-frequency layout techniques should be applied during PCB design.
13.1 Layout Guidelines
•
Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows optional transient voltage suppression
(TVS) diodes, D1 and D2, which may be implemented if the system-level requirements exceed the specified
rating of the transceiver. This example also shows optional bus filter capacitors C6, C8, C9 and C11.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
•
•
•
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Note
High frequency current follows the path of least impedance and not the path of least resistance.
•
This layout example shows how split termination could be implemented on the CAN node. The termination is
split into two resistors, R8 and R9 for channel 1, R10 and R11 for channel 2 with the center or split tap of the
termination connected to ground via capacitor C7 or C10. Split termination provides common-mode filtering
for the bus. See CAN Termination, CAN Bus Short Circuit Current Limiting, and Equation 2 for information on
termination concepts and power ratings needed for the termination resistor(s).
13.2 Layout Example
STB1/nSTB1
GND
VCC
R1
TXD1
GND1
VCC
STB1 / nSTB1
CANH1
TXD1
R2
GND
GND
CMC
C7
CANL1
VCC
GND
GND
TCAN1046AV
VIO
CANH2
CANL2
R3
RXD1
GND2
RXD1
R4
TCAN1048AV
VCC
C10
CMC
TXD2
RXD2
R5
TXD2
RXD2
GND
R6
STB2 / nSTB2
STB2/nSTB2
GND
Figure 13-1. Layout Example
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14 Device and Documentation Support
14.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
14.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE MATERIALS INFORMATION
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24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1046AVDMTRQ1
TCAN1048AVDMTRQ1
VSON
VSON
DMT
DMT
14
14
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
4.8
4.8
1.2
1.2
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN1046AVDMTRQ1
TCAN1048AVDMTRQ1
VSON
VSON
DMT
DMT
14
14
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DMT 14
3 x 4.5, 0.65 mm pitch
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225088/A
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PACKAGE OUTLINE
DMT0014B
VSON - 1 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.13)
1.0
0.8
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
(0.19) TYP
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
PIN 1 ID
14X
0.1
C A B
(OPTIONAL)
0.05
C
4225087/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225087/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4225087/B 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
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EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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