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TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

具有集成音频处理器且支持 2.1 模式的 TAS5755M 2 × 50W (2 × 19W + 1

× 50W) 数字输入音频放大器

1 特性

2 应用

1

•

解决方案尺寸更小

•

DTV、UHD 和多功能监控器

条形音箱、电脑音频

通用音频设备

–

支持单芯片 2.1、2.0 和单声道模式

单声道 (PBTL) 模式采用单滤波器。

焊盘朝上封装和 80mΩ R_DSON增强热性能

3 说明

•

支持高输出功率：

TAS5755M 是具有集成式处理功能的单芯片灵活数字

音频解决方案，支持 2.1（2 个扬声器 + 1 个低音

炮）、2.0 或立体声（2 个扬声器）和单声道（高功率

扬声器）模式。

–

2.1 模式

可提供 2 × 19W +1 × 50W 的输出功率（2 ×

4Ω + 1 × 6Ω，24V）

–

2.0 模式可提供 2 × 50W 的输出功率（2 ×

6Ω，24V）

该器件具有高效率，R_DSON低至 80mΩ，并且采用焊

盘朝上封装，输出功率高达 2 × 50W 或 1 × 100W。

单声道模式可提供 1 × 100W 的输出功率（1 ×

2Ω，24V）

宽电源电压范围：8V 至 26.4V

TAS5755M 的立体声模式中的每个通道都使用 2 个全

H 桥。在 2.1 模式中，TAS5755M 使用 2 个半桥驱动

2 个独立的扬声器通道，同时使用 1 个全桥驱动低音

炮。此外，在单声道模式中，TAS5755M 使用单级滤

波器支持预滤波并联桥接式负载 (PBTL)，减少了系统

总尺寸并降低了成本。

•

音频性能：

–

频率为 1kHz 时，THD+N ≤ 0.05%（R_SPK=

8Ω，POUT = 1W，PVDD = 18V）

–

ICN ≤ 50µVRMS

串扰 ≤ - 67dB

SNR ≥ 104dB

TAS5755M 具有集成式音频处理功能。它包括：信号

混合、直流阻断滤波器、2 × 8 + 1 × 2 双二阶滤波

器，从而实现均衡。通过双频带对数式 DRC 和用于低

音炮通道的单独单频带 DRC 实现功率限制。

提供 BD 调制功能，提高音频性能和效率。

•

集成式音频处理：

–

2 × 8 + 1 × 2 双二阶滤波器

双频带 + 单频带可配置动态范围控制 (DRC)

免许可证的 3D 音效

器件信息⁽¹⁾

器件型号

TAS5755M

封装

封装尺寸（标称值）

信号混合和直流阻断滤波器

自动速率检测

DFD

14mm × 6.1mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

集成式自保护

–

热保护

过流限制保护

欠压保护

效率与总输出功率间的关系

输出功率与电源电压间的关系

100

90

80

70

60

50

40

30

20

10

0

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

THD+N=1%, R _L=4W

THD+N=10%, R _L=4W

THD+N=1%, R _L=6W

THD+N=10%, R _L=6W

BTL Mode

T_A=25èC

R_L=6W

PVDD = 12V

PVDD = 18 V

PVDD = 24 V

BTL Mode

T_A=25èC

0

10

20

30

40

50

60

70

80

8

10

12

14

16

18

20

22

24

26

Output Power (W)

Supply Voltage (V)

D014

D03072

D00234

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLOS982

TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

8

9

Parameter Measurement Information ................ 21

Detailed Description ............................................ 21

9.1 Overview ................................................................. 21

9.2 Functional Block Diagrams ..................................... 21

9.3 Feature Description................................................. 24

9.4 Device Functional Modes........................................ 34

9.5 Programming........................................................... 36

9.6 Register Maps......................................................... 41

10 Application and Implementation........................ 59

10.1 Application Information.......................................... 59

10.2 Typical Applications .............................................. 59

11 Power Supply Recommendations ..................... 68

11.1 DVDD and AVDD Supplies................................... 68

11.2 PVDD Power Supply............................................. 68

12 Layout................................................................... 68

12.1 Layout Guidelines ................................................. 68

12.2 Layout Examples................................................... 69

13 器件和文档支持 ..................................................... 71

13.1 器件支持 ............................................................... 71

13.2 文档支持 ............................................................... 71

13.3 社区资源................................................................ 71

13.4 商标....................................................................... 71

13.5 静电放电警告......................................................... 71

13.6 术语表 ................................................................... 71

7.5 PWM Operation at Recommended Operating

Conditions .................................................................. 8

7.6 DC Electrical Characteristics .................................... 8

7.7 AC Electrical Characteristics (BTL, PBTL)................ 9

7.8 Electrical Characteristics - PLL External Filter

Components............................................................... 9

7.9 Electrical Characteristic - I²C Serial Control Port

Operation ................................................................... 9

7.10 Timing Requirements - PLL Input Parameters ..... 10

7.11 Timing Requirements - Serial Audio Ports Slave

Mode ........................................................................ 10

7.12 Timing Requirements - I²C Serial Control Port

Operation ................................................................ 10

7.13 Timing Requirements - Reset (RESET)................ 10

7.14 Typical Characteristics.......................................... 13

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (January 2018) to Revision C

Page

•

Changed "DVSSO" in OSC_RES Pin Description to "DVSS_OSC ground." ........................................................................ 6

Added R_θJAin Thermal Information Table............................................................................................................................... 8

Changed R_θJC(top)in Thermal Information Table ..................................................................................................................... 8

Added R_θJBin Thermal Information Table............................................................................................................................... 8

Added Ψ_JTin Thermal Information Table................................................................................................................................ 8

Added R_θJC(bot)in Thermal Information Table ......................................................................................................................... 8

Changes from Revision A (November 2017) to Revision B

Page

•

Changed SE Mode, PVDD = 24 V, R_L= 4Ω, 7% THD from 17.1 W to 17.6 W in AC Electrical Characteristics (BTL,

PBTL) ..................................................................................................................................................................................... 9

Changed SE Mode, PVDD = 24 V, R_L= 4Ω, 10% THD from 18.1 W to 19 W in AC Electrical Characteristics (BTL,

PBTL) ..................................................................................................................................................................................... 9

•

Changed 图 6 and 图 7 ........................................................................................................................................................ 13

Changed 图 19, 图 20, and 图 21......................................................................................................................................... 16

Changed 图 33, 图 34, and 图 35 ........................................................................................................................................ 19

2

TAS5755M

www.ti.com.cn

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

Changes from Original (August 2017) to Revision A

Page

•

将器件发布为生产数据............................................................................................................................................................ 1

3

TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

www.ti.com.cn

5 Device Comparison Table

TAS5755M

TAS5731M

TAS5729MD

TAS5721

TAS5717

TAS5711

Max Power to Single-

Ended Load

19

50

100

2

18

10

16

Max Power to Bridge

Tied Load

37

70

2

20

40

15

30

4

10

20

40

4

Max Power to Parallel

Bridge Tied Load

Min Supported Single-

Ended Load

Min Supported Bridge

Tied Load

4

8

4

6

Min Supported Parallel

Bridge Tied Load

2

4

Closed/Open Loop

Max Speaker Outputs

Headphone Channels

Architecture

Open

3

Open

3

Open

2

Open

3

Open

2

Open

3

Yes

Class D

2-Band

Class D

2-Band

Class D

2-Band AGL

Class D

2-Band

Class D

2-Band AGL

Class D

Dynamic Range Control

(DRC)

Single-Band

Biquads (EQ)

21

28

21

28

21

4

TAS5755M

www.ti.com.cn

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

6 Pin Configuration and Functions

HTSSOP Package

56-Pin DFD

Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

ADR/FAULT

NO.

8

DIO

Dual function terminal which sets the LSB of the 7-bit I2C address to "0" if pulled to GND and to "1" if

pulled to DVDD. If configured to be a fault output by the methods described in I²C Address Selection

and Fault Output, this terminal is pulled low when an internal fault occurs. A pull-up or pull-down

resistor is required, as is shown in the Typical Application Circuit Diagrams. If pulled high (to DVDD), a

15-kΩ resistor must be used to minimize in-rush current at power up and to isolate the net if the pin is

used as a fault output, as described above.

AVDD

AVSS

9

13,14

17

P

3.3-V analog power supply

Analog 3.3-V supply ground

BST_A

BST_B

High-side bootstrap supply for half-bridge A

High-side bootstrap supply for half-bridge B

28

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

5

TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

29

BST_C

BST_D

DVDD

DVSS

P

DI

–

High-side bootstrap supply for half-bridge C

High-side bootstrap supply for half-bridge D

3.3-V digital power supply

40

47

44,46

3

Digital ground

DVSS_OSC

GVDD

LRCLK

MCLK

Oscillator ground

41

Gate drive internal regulator output

56

Input serial audio data left/right clock (sample-rate clock)

5

Master clock input

No connect

NC

6,7,22,35,

43,45,50,5

1

OSC_RES

OUT_A

OUT_B

OUT_C

OUT_D

PBTL

4

AO

O

Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSS_OSC ground.

20,21

26,27

30,31

36,37

15

Output, half-bridge A

Output, half-bridge B

Output, half-bridge C

Output, half-bridge D

O

DI

Low means BTL mode; high means PBTL mode. Information goes directly to power stage.

PDN

1

Power down, active-low. PDN prepares the device for loss of power supplies by shutting down the

noise shaper and initiating the PWM stop sequence.

PGND

23,24,25,

32,33,34

P

Power ground for half-bridges A and B

FLTM

12

11

AO

P

PLL negative loop-filter terminal

FLTP

PLL positive loop-filter terminal

PVDD_AB

PVDD_CD

RESET

18,19

38,39

49

Power-supply input for half-bridge output A and B

Power-supply input for half-bridge output C and D

P

DI

Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET is an

asynchronous control signal that restores the DAP to its default conditions and places the PWM in the

hard-mute (high-impedance) state.

I²C serial control clock input

SCL

52

55

53

54

16

DI

SCLK

SDA

Serial audio-data clock (shift clock). SCLK is the serial-audio-port input-data bit clock.

I²C serial control data interface input/output

DIO

DI

SDIN

Serial audio data input. SDIN supports three discrete (stereo) data formats.

SSTIMER

AI

Controls ramp time of OUT_x to minimize pop. Leave this pin floating for BD mode. Requires capacitor

of 2.2 nF to GND in AD mode. The capacitor determines the ramp time.

STEST

48

10

2

DI

P

Factory test pin. Connect directly to DVSS.

VR_ANA

VR_DIG

VREG

Internally regulated 1.8-V analog supply voltage. This pin must not be used to power external devices.

Internally regulated 1.8-V digital supply voltage. This pin must not be used to power external devices.

Digital regulator output. Not to be used for powering external circuitry.

42

PowerPAD™

Connect to GND for best system performance. If not connected to GND, leave floating.

6

TAS5755M

www.ti.com.cn

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.5

MAX

UNIT

V

DVDD, AVDD

4.2

Supply voltage

PVDD_x

30

V

3.3-V digital input

5-V tolerant⁽²⁾digital input (except MCLK)

DVDD + 0.5

DVDD + 2.5⁽³⁾

AVDD + 2.5⁽³⁾

Input voltage

V

5-V tolerant MCLK input

OUT_x to PGND_x

32⁽⁴⁾

39⁽⁴⁾

20

V

BST_x to PGND_x

Input clamp current, I_IK

Output clamp current, I_OK

Operating free-air temperature

Operating junction temperature

Storage temperature, T_stg

–20

0

mA

°C

20

85

0

150

125

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.

(3) Maximum pin voltage must not exceed 6 V.

(4) DC voltage + peak ac waveform measured at the pin must be below the allowed limit for all conditions.

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX

3.6

26.4⁽¹⁾

UNIT

V

Digital/analog supply voltage

Half-bridge supply voltage

High-level input voltage

Low-level input voltage

Operating ambient temperature range

Operating junction temperature range

Load impedance

DVDD, AVDD

PVDD_x

3

8

2

3.3

V

V_IH

V_IL

T_A

5-V tolerant

V

0.8

85

V

0

2

4

2

°C

Ω

(2)

T_J

125

R_L(PBTL)

R_L(BTL)

R_L(SE)

Output filter: L = 15 μH, C = 680 nF

Load impedance

Ω

Load impedance

Ω

Minimum output inductance under short-

circuit condition

L_O

Output-filter inductance

10

μH

(1) For operation at PVDD_x levels greater than 18 V, the modulation limit must be set to 93.8% through the control port register 0x10.

(2) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

7

TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

www.ti.com.cn

7.4 Thermal Information

TAS5755M

THERMAL METRIC⁽¹⁾

DFD HTSSOP

UNIT

56-PIN

50.9

1.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

26.9

3.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

26.7

—

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 PWM Operation at Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

11.025/22.05/44.1-kHz data rate ±2%

48/24/12/8/16/32-kHz data rate ±2%

VALUE

352.8

384

UNIT

Output PWM switch frequency

kHz

7.6 DC Electrical Characteristics

T_A= 25°, PVDD_x = 18 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL AD mode, f_S= 48 kHz (unless otherwise noted)

PARAMETER

High-level output voltage

TEST CONDITIONS

MIN TYP

MAX

UNIT

I_OH= –4 mA

DVDD = 3 V

V_OH

V_OL

I_IL

ADR/FAULT and SDA

2.4

V

I_OL= 4 mA

DVDD = 3 V

Low-level output voltage

Low-level input current

High-level input current

0.5

75

V_I< V_IL;

DVDD = AVDD = 3.6 V

μA

V_I> V_IH

;

I_IH

75⁽¹⁾

68

38

50

8

DVDD = AVDD = 3.6 V

Normal mode

49

23

32

4

3.3-V supply voltage (DVDD,

AVDD)

I_DD

3.3-V supply current

Supply current

mA

Reset (RESET = low,

PDN = high)

Normal mode

I_PVDD

No load (PVDD_x)

mA

Reset (RESET = low,

PDN = high)

Drain-to-source resistance, LS T_J= 25°C, includes metallization resistance

Drain-to-source resistance, HS T_J= 25°C, includes metallization resistance

80

(2)

r_DS(on)

mΩ

I/O

PROTECTION

V_uvp

Undervoltage protection limit

Overtemperature error

PVDD falling

PVDD rising

6.4

7.1

V

V_uvp,hyst

OTE⁽³⁾

150

°C

Extra temperature drop

required to recover from error

(3)

OTE_HYST

30

°C

I_OC

Overcurrent limit protection

Overcurrent response time

Output to output short in BTL mode

6

A

I_OCT

150

ns

(1) I_IHfor the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.

(2) This does not include bond-wire or pin resistance.

(3) Specified by design.

8

TAS5755M

www.ti.com.cn

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

7.7 AC Electrical Characteristics (BTL, PBTL)

PVDD_x = 18 V, BTL AD mode, f_S= 48 kHz, R_L= 8 Ω, C_BST= 10 nF, audio frequency = 1 kHz, AES17 filter,

f_PWM= 384 kHz, T_A= 25°C (unless otherwise noted). All performance is in accordance with recommended operating

conditions (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

3.9

UNIT

BTL mode, PVDD = 8 V, R_L= 8 Ω, 7% THD

BTL mode, PVDD = 8 V, R_L= 8 Ω,10% THD

BTL mode, PVDD = 12 V, R_L= 8 Ω, 7% THD

BTL mode, PVDD = 12 V, R_L= 8 Ω,10% THD

BTL mode, PVDD = 18 V, R_L= 8 Ω, 7% THD

BTL mode, PVDD = 18 V, R_L= 8 Ω, 10% THD

BTL mode, PVDD = 24 V, R_L= 8 Ω, 7% THD

BTL mode, PVDD = 24 V, R_L= 8 Ω, 10% THD

BTL mode, PVDD = 24 V, R_L= 6 Ω, 10% THD

PBTL mode, PVDD = 12 V, R_L= 4 Ω, 7% THD

PBTL mode, PVDD = 12 V, R_L= 4 Ω, 10% THD

PBTL mode, PVDD = 18 V, R_L= 4 Ω, 7% THD

PBTL mode, PVDD = 18 V, R_L= 4 Ω, 10% THD

PBTL mode, PVDD = 24 V, R_L= 4 Ω, 10% THD

SE Mode, PVDD = 12 V, RL = 4 Ω, 7% THD

SE Mode, PVDD = 12 V, RL = 4 Ω, 10% THD

SE Mode, PVDD = 18 V, RL = 4 Ω, 7% THD

SE Mode, PVDD = 18 V, RL = 4 Ω, 10% THD

SE Mode, PVDD = 24 V, RL = 4 Ω, 7% THD

SE Mode, PVDD = 24 V, RL = 4 Ω, 10% THD

PVDD = 8 V, P_O= 1 W

4.2

8

9.6

18.7

21.2

32.6

37.2

50

16.5

17.9

37

P_O

Power output per channel

W

39.6

66

69.6

4.2

4.6

9.6

10.2

17.6

19

0.15%

0.03%

0.04%

0.1%

46

PVDD = 12 V, P_O= 1 W

THD+N

Total harmonic distortion + noise

PVDD = 18 V, P_O= 1 W

PVDD = 24 V, P_O= 1 W

V_n

Output integrated noise (rms)

Cross-talk

A-weighted

μV

P_O= 0.25 W, f = 1 kHz (AD Mode)

–67

dB

A-weighted, f = 1 kHz, maximum power at THD

< 1%

SNR

Signal-to-noise ratio⁽¹⁾

104

dB

(1) SNR is calculated relative to 0-dBFS input level.

7.8 Electrical Characteristics - PLL External Filter Components

PARAMETER

TEST CONDITIONS

MIN

TYP

47

MAX

UNIT

nF

External PLL filter capacitor C1

External PLL filter capacitor C2

External PLL filter resistor R

SMD 0603 X7R

4.7

nF

SMD 0603, metal film

470

Ω

7.9 Electrical Characteristic - I²C Serial Control Port Operation

for I²C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_L

Load capacitance for each bus line

400

pF

9

TAS5755M

ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

www.ti.com.cn

7.10 Timing Requirements - PLL Input Parameters

MIN

2.8224

40%

NOM

MAX

24.576

60%

5

UNIT

f_MCLKI

MCLK frequency

MHz

MCLK duty cycle

50%

t_r/t_f(MCLK)

Rise/fall time for MCLK

LRCLK allowable drift before LRCLK reset

ns

4

MCLKs

7.11 Timing Requirements - Serial Audio Ports Slave Mode

over recommended operating conditions (unless otherwise noted)

MIN

NOM

MAX

UNIT

MHz

ns

f_SCLKIN

t_su1

Frequency, SCLK 32 × f_S, 48 × f_S, 64 × f_S

Setup time, LRCLK to SCLK rising edge

Hold time, LRCLK from SCLK rising edge

Setup time, SDIN to SCLK rising edge

Hold time, SDIN from SCLK rising edge

LRCLK frequency

C_L= 30 pF

1.024

10

12.288

t_h1

10

ns

t_su2

10

ns

t_h2

10

ns

8

48

50%

48

60%

kHz

SCLK duty cycle

40%

LRCLK duty cycle

SCLK

edges

SCLK rising edges between LRCLK rising edges

32

64

SCLK

period

t_(edge)

t_r/t_f

LRCLK clock edge with respect to the falling edge of SCLK

Rise/fall time for SCLK/LRCLK

–1/4

1/4

8

ns

7.12 Timing Requirements - I²C Serial Control Port Operation

for I²C Interface signals over recommended operating conditions (unless otherwise noted)

MIN

NOM

MAX

400

UNIT

kHz

μs

f_SCL

t_w(H)

t_w(L)

t_r

Frequency, SCL

No wait states

Pulse duration, SCL high

0.6

1.3

Pulse duration, SCL low

μs

Rise time, SCL and SDA

300

ns

t_f

Fall time, SCL and SDA

ns

t_su1

t_h1

Setup time, SDA to SCL

100

0

ns

Hold time, SCL to SDA

ns

t_(buf)

t_su2

t_h2

Bus free time between stop and start conditions

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

1.3

0.6

μs

t_su3

μs

7.13 Timing Requirements - Reset (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted).

MIN

NOM

MAX

UNIT

t_w(RESET)

Pulse duration, RESET active

Time to enable I²C

100

μs

t_{d(I2C_ready)}

12

ms

10

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ZHCSH30C –AUGUST 2017–REVISED APRIL 2018

t_r

t_f

SCLK

(Input)

t_(edge)

t_h1

t_su1

LRCLK

(Input)

t_h2

t_su2

SDIN

T0026-04

图 1. Slave-Mode Serial Data-Interface Timing

t_w(H)

t_w(L)

t_r

t_f

SCL

t_su1

t_h1

SDA

T0027-01

图 2. SCL and SDA Timing

SCL

t_(buf)

t_h2

t_su2

t_su3

SDA

Start

Condition

Stop

Condition

T0028-01

图 3. Start and Stop Conditions Timing

11

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RESET

t_w(RESET)

I²C Active

t_{d(I2C_ready)}

System Initialization.

Enable via I²C.

T0421-01

NOTES: On power up, it is recommended that the TAS5755M RESET be held LOW for at least 100 μs after DVDD has

reached 3 V.

If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after

PDN is deasserted (HIGH).

图 4. Reset Timing

12

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7.14 Typical Characteristics

7.14.1 Typical Characteristics, 2.1 SE Configuration

30

10

5

2.1 SE Mode

T_A=25èC

R_L=2ì4W + 6W

2.1 SE Mode

PV_DD=12V

f = 1kHz

25

2

1

T_A=25èC

0.5

20

15

10

0.2

0.1

0.05

0.02

0.01

RL = 2ì4W+4W

RL = 2ì4W+8W

RL = 2ì8W+8W

0.005

5

THD+N=1%

THD+N=10%

0.002

0.001

0

0.01

0.1

1

10

8

10

12

14

16

18

20

22 24 26

Output Power (W)

Supply Voltage (V)

D00278

D014

D03071

图 6. Total Harmonic Distortion + Noise vs Output Power

图 5. Output Power vs Supply Voltage

10

5

2.1 SE Mode

PV_DD=18V

f = 1kHz

2.1 SE Mode

PV_DD=24V

f = 1kHz

T_A=25èC

5

2

1

2

1

T_A=25èC

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

RL = 2ì4W+4W

RL = 2ì4W+8W

RL = 2ì8W+8W

0.005

RL = 2ì4W+4W

RL = 2ì4W+8W

RL = 2ì8W+8W

0.005

0.002

0.001

0.002

0.001

0.01

0.1

1

10

0.1

1

10

20

100

Output Power (W)

D02097

Output Power (W)

D00370

图 7. Total Harmonic Distortion + Noise vs Output Power

图 8. Total Harmonic Distortion + Noise vs Output Power

10

RL = 2þ8Ω+8Ω

2.1 SE Mode

P_O= 1W

PV_DD= 12V

P_O= 1W

PV_DD= 18V

RL = 2þ4Ω+8Ω

T_A= 25°C

RL = 2þ4Ω+4Ω

1

0.1

0.01

0.001

0.01

0.001

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C020

C021

图 9. Total Harmonic Distortion + Noise vs Frequency

图 10. Total Harmonic Distortion + Noise vs Frequency

13

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Typical Characteristics, 2.1 SE Configuration (接下页)

10

100

90

80

70

60

50

40

30

20

10

0

RL = 2þ8Ω+8Ω

2.1 SE Mode

P_O= 1W

PV_DD= 24V

T_A= 25°C

RL = 2þ4Ω+8Ω

RL = 2þ4Ω+4Ω

1

2.1 SE Mode

R_L= 2þ8+8Ω

T_A= 25°C

0.1

0.01

0.001

PVDD = 12V

PVDD = 18V

PVDD = 24V

20

200

2k

20k

0

20

40

60

80

Frequency (Hz)

Total Output Power (W)

C022

C023

图 11. Total Harmonic Distortion + Noise vs Frequency

图 12. Efficiency vs Total Output Power

0

100

90

Right-to-Left

2.1 SE Mode

P_O= 1W

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Left-to-Right

PV_DD= 12V

R_L= 2þ8+8Ω

T_A= 25°C

80

2.1 SE Mode

R_L= 2þ4+8Ω

T_A= 25°C

70

60

50

40

30

20

10

0

PVDD = 12V

PVDD = 18V

PVDD = 24V

20

200

2k

20k

0

20

40

60

80

Frequency (Hz)

Total Output Power (W)

C025

C024

图 14. Crosstalk vs Frequency

图 13. Efficiency vs Total Output Power

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Right-to-Left

2.1 SE Mode

Right-to-Left

Left-to-Right

2.1 SE Mode

P_O= 1W

PV_DD= 24V

R_L= 2þ8+8Ω

T_A= 25°C

P_O= 1W

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Left-to-Right

PV_DD= 12V

R_L= 2þ4+4Ω

T_A= 25°C

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C026

C027

图 15. Crosstalk vs Frequency

图 16. Crosstalk vs Frequency

14

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Typical Characteristics, 2.1 SE Configuration (接下页)

0

Right-to-Left

Left-to-Right

2.1 SE Mode

P_O= 1W

PV_DD= 24V

R_L= 2þ4+4Ω

T_A= 25°C

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

20

200

2k

20k

Frequency (Hz)

C028

图 17. Crosstalk vs Frequency

15

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www.ti.com.cn

7.14.2 Typical Characteristics, 2.0 BTL Configuration

75

10

5

2.0 BTL Mode

PV_DD=12V

f = 1kHz

70

65

60

55

50

45

40

35

30

25

20

15

10

5

THD+N=1%, R _L=4W

THD+N=10%, R _L=4W

THD+N=1%, R _L=6W

THD+N=10%, R _L=6W

2

1

T_A=25èC

0.5

0.2

0.1

0.05

0.02

0.01

RL = 4W

RL = 6W

RL = 8W

0.005

BTL Mode

T_A=25èC

0.002

0.001

0

0.1

1

10

20

100

8

10

12

14

16

18

20

22

24

26

Output Power (W)

Supply Voltage (V)

D00371

D014

D03072

图 19. Total Harmonic Distortion + Noise vs Output Power

图 18. Output Power vs Supply Voltage

10

5

10

2.0 BTL Mode

PV_DD=18V

f = 1kHz

2.0 BTL Mode

PV_DD=24V

f = 1kHz

T_A=25èC

5

2

1

2

1

T_A=25èC

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

RL = 4W

RL = 6W

RL = 8W

RL = 4W

RL = 6W

RL = 8W

0.005

0.002

0.001

0.002

0.001

0.1

1

10

20

100

0.1

1

10

20

100

Output Power (W)

D03027

D00373

图 20. Total Harmonic Distortion + Noise vs Output Power

图 21. Total Harmonic Distortion + Noise vs Output Power

10

RL = 4Ω

2.0 BTL Mode

PV_DD= 12V

P_O= 1W

PV_DD= 18V

P_O= 1W

RL = 6Ω

T

_A= 25°C

T_A= 25°C

RL = 8Ω

1

0.1

0.01

0.001

0.01

0.001

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C006

C007

图 22. Total Harmonic Distortion vs Frequency

图 23. Total Harmonic Distortion vs Frequency

16

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Typical Characteristics, 2.0 BTL Configuration (接下页)

10

100

90

80

70

60

50

40

30

20

10

0

RL = 4Ω

2.0 BTL Mode

PV_DD= 24V

P_O= 1W

T_A= 25°C

RL = 6Ω

RL = 8Ω

1

2.0 BTL Mode

R_L= 8Ω

T_A= 25°C

0.1

0.01

0.001

PVDD = 12V

PVDD = 18V

PVDD = 24V

20

200

2k

20k

0

20

40

60

80

Frequency (Hz)

Total Output Power (W)

C008

C005

图 24. Total Harmonic Distortion vs Frequency

图 25. Efficiency vs Output Power

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Right-to-Left

2.0 BTL Mode

P_O= 1W

PV_DD= 12V

R_L= 8Ω

P_O= 1W

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Left-to-Right

PV_DD= 24V

R_L= 8Ω

T

_A= 25°C

T_A= 25°C

20

200

2k

20k

200

2k

20k

Frequency (Hz)

C010

C011

图 26. Crosstalk vs Frequency

图 27. Crosstalk vs Frequency

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

Right-to-Left

2.0 BTL Mode

P_O= 1W

PV_DD= 12V

R_L= 4Ω

P_O= 1W

Left-to-Right

PV_DD= 24V

R_L= 4Ω

T_A= 25°C

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C015

C012

图 28. Crosstalk vs Frequency

图 29. Crosstalk vs Frequency

17

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www.ti.com.cn

Typical Characteristics, 2.0 BTL Configuration (接下页)

100

90

80

70

60

50

40

30

20

70

60

50

40

30

20

10

0

2.0 BTL Mode

T_A= 25°C

BTL Mode

_A=25èC

R_L=6W

PVDD = 12V

PVDD = 18 V

PVDD = 24 V

T

10

0

RL = 4Ω

0

10

20

30

40

50

60

70

80

RL = 6Ω

RL = 8Ω

Output Power (W)

D00234

图 30. Power vs Supply Voltage

8

10

12

14

16

18

20

22

24

Supply Voltage (V)

C009

图 31. Idle Channel Noise vs Supply Voltage

18

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7.14.3 Typical Characteristics, PBTL Configuration

120

10

5

PBTL Mode

PV_DD=12V

f = 1kHz

THD+N=1%, R _L=4W

THD+N=10%, R _L=4W

THD+N=1%, R _L=6W

THD+N=10%, R _L=6W

THD+N=1%, R _L=2W

THD+N=10%, R _L=2W

110

100

2

1

T_A=25èC

90

80

70

60

50

40

30

20

10

0

0.5

0.2

0.1

0.05

0.02

0.01

0.005

RL = 2W

RL = 4W

PBTL Mode

T_A=25èC

0.002

0.001

0.1

1

10

20

100

8

10

12

14

16

18

20

22

24 25

Output Power (W)

Supply Voltage (V)

D00374

D014

D03074

图 33. Total Harmonic Distortion + Noise vs Output Power

图 32. Output Power vs Supply Voltage

(PBTL Mode)

10

5

10

PBTL Mode

PV_DD=18V

f = 1kHz

PBTL Mode

PV_DD=24V

f = 1kHz

T_A=25èC

5

2

1

2

1

T_A=25èC

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

RL = 2W

RL = 4W

RL = 2W

RL = 4W

0.002

0.001

0.002

0.001

0.1

1

10

20

100

0.1

1

10

20

100

Output Power (W)

D03057

D00376

图 34. Total Harmonic Distortion + Noise vs Output Power

图 35. Total Harmonic Distortion + Noise vs Output Power

(PBTL Mode)

10

RL = 2Ω

PBTL Mode

P_O= 1W

PV_DD= 12V

T_A= 25°C

RL = 4Ω

RL = 6Ω

P_O= 1W

PV_DD= 18V

T_A= 25°C

RL = 4Ω

RL = 6Ω

1

0.1

0.01

0.001

0.01

0.001

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C037

C038

图 36. Total Harmonic Distortion vs Frequency (PBTL

图 37. Total Harmonic Distortion vs Frequency (PBTL

Mode)

19

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Typical Characteristics, PBTL Configuration (接下页)

10

100

90

80

70

60

50

40

30

20

10

0

RL = 2Ω

PBTL Mode

P_O= 1W

PV_DD= 24V

T_A= 25°C

RL = 4Ω

RL = 6Ω

1

PBTL Mode

R_L= 4Ω

T_A= 25°C

0.1

0.01

0.001

PVDD = 12V

PVDD = 18V

PVDD = 24V

20

200

2k

20k

0

20

40

60

80

Frequency (Hz)

Total Output Power (W)

C041

C035

图 38. Total Harmonic Distortion vs Frequency (PBTL

图 39. Efficiency vs Output Power (PBTL Mode)

Mode)

90

100

90

PBTL Mode

R_L= 4W

80

70

60

50

40

30

20

10

0

T

_A=25èC

80

PBTL Mode

R_L= 6Ω

T_A= 25°C

70

60

50

40

30

20

10

0

THD+N=1%

THD+N=10%

PVDD = 12V

PVDD = 18V

PVDD = 24V

8

10

12

14

16

18

20

22

24

Supply Voltage (V)

D014

D03075

图 41. Power vs Supply Voltage (PBTL Mode)

0

10

20

30

40

50

Total Output Power (W)

C034

图 40. Efficiency vs Output Power (PBTL Mode)

80

PBTL Mode

T_A= 25°C

60

40

20

0

RL = 4Ω

RL = 6Ω

RL = 8Ω

8

10

12

14

16

18

20

22

24

Supply Voltage (V)

C036

图 42. Idle Channel Noise vs Supply Voltage (PBTL Mode)

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8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section.

9 Detailed Description

9.1 Overview

The TAS5755M is an efficient 50-W stereo I²S input Class-D audio power amplifier. The digital auto processor of

the device uses noise shaping and customized correction algorithms to achieve a great power efficiency and high

audio performance. Also, the device has up to eight Equalizers per channel and two -band configurable Dynamic

Range Control (DRC).

The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal

voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of

the device enables its use in a multitude of applications.

The TAS5755M is a slave-only device that is controlled by a bidirectional I²C interface that supports both 100-

kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface

is used to program the registers of the device and read the device status.

The PWM of this device operates with a carrier frequency between 384 kHz and 354 kHz, depending the

sampling rate. This device allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using

a sampling frequency of 44.1 kHz or 48 kHz.

This device can be used in three different modes of operation, Stereo BTL mode, Single filter PBTL mono mode,

and 2.1 mode.

9.2 Functional Block Diagrams

OUT_A

2´ HB

FET Out

OUT_B

4^th-Order

Noise Shaper

and PWM

Serial

Audio

Port

S

R

C

Digital Audio Processor

(DAP)

SDIN

OUT_C

OUT_D

2´ HB

FET Out

Protection

Logic

MCLK

SCLK

Sample Rate

Autodetect

and PLL

Click and Pop

Control

LRCLK

Microcontroller

SDA

SCL

Based

System

Control

Serial

Control

Terminal Control

B0262-14

图 43. Functional Block Diagram

21

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www.ti.com.cn

Functional Block Diagrams (接下页)

4

Under-

voltage

Protection

FAULT

4

Power

On

Reset

AGND

GND

Protection

and

I/O Logic

Temp.

Sense

VALID

Overcurrent

Protection

I_sense

BST_D

PVDD_CD

OUT_D

PWM_D

PWM

Ctrl

Gate

Drive

Timing

Rcv

Pulldown Resistor

GVDD

Regulator

PGND_CD

GVDD_OUT

BST_C

PVDD_CD

OUT_C

PWM_C

PWM

Ctrl

Gate

Drive

Rcv

PGND_CD

BST_B

PVDD_AB

OUT_B

PWM_B

PWM

Ctrl

Gate

Drive

Rcv

GVDD

Regulator

PGND_AB

BST_A

PVDD_AB

OUT_A

PWM_A

PWM

Ctrl

Gate

Drive

Rcv

PGND_AB

B0034-08

图 44. Power-Stage Functional Block Diagram

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www.ti.com.cn

9.3 Feature Description

9.3.1 Power Supply

To facilitate system design, the TAS5755M needs only a 3.3-V supply in addition to the PVDD power-stage

supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all

circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in

bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical half-bridges with separate bootstrap pins (BST_x). The gate-drive voltage (GVDD_OUT) is

derived from the PVDD voltage. Special attention must be paid to placing all decoupling capacitors as close to

their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be

avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 10-nF, X7R ceramic

capacitors, size 0603 or 0805, for the bootstrap supply. These 10-nF capacitors ensure sufficient energy storage,

even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during

the remaining part of the PWM cycle.

Special attention must be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is

decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5755M is fully protected against erroneous power-stage turnon due to parasitic gate charging.

9.3.2 I²C Address Selection and Fault Output

ADR/FAULT is an input pin during power up. It can be pulled HIGH or LOW through a resistor as shown in the

Typical Applications sections in order to set the I²C address. Pulling this pin HIGH through the resistor results in

setting the I²C 7-bit address to 0011011 (0x36), and pulling it LOW through the resistor results in setting the

address to 0011010 (0x34).

During power up, the address of the device is latched in, freeing up the ADR/FAULT pin to be used as a fault

notification output. When configured as a fault output, the pin will go low when a fault occurs and will return to its

default state when register 0x02 is cleared. The behavior of the pin in response to a fault condition is to be pulled

low immediately upon an error. The device then waits for a period of time determined by BKND_ERR Register

(0x1C) before attempting to resume playback. If the error has been cleared when the device attempts to resume

playback, playback will resume, the ADR/FAULT pin will remain high, and normal operation will resume. If the

error has not been removed, then the device will immediately re-enter the protected state and wait again for the

predetermined period of time to pass. The device will pull the fault pin low for over-current, over-temperature, and

under-voltage lock-out.

9.3.3 Single-Filter PBTL Mode

The TAS5755M supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected

before the LC filter. In addition to connecting OUT_A/OUT_B and OUT_C/OUT_D, BST_A/BST_B and

BST_C/BST_D must also be connected before the LC filter, as shown in the 图 71. In order to put the part in

PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of half-bridges A and B (and similarly

C/D) if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that

configures the part in BTL mode if the pin is left floating.

PWM output multiplexers register (0x25) and PWM Shutdown Group Register (0x19) must be updated to set the

device in PBTL mode. Must follow one of below listed configurations for PBTL mode.

•

.

Register (0x25) be written with a value of 0x0110 3245, Register (0x19) be written with a value of 0x35

Register (0x25) be written with a value of 0x0101 2345, Register (0x19) be written with a value of 0x3A

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Feature Description (接下页)

9.3.4 Device Protection System

9.3.4.1 Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored by a protection system. If the high-current condition situation persists, that

is, the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power

stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault

condition (that is, a short circuit on the output) is removed. Current-limiting and overcurrent protection are not

independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent

fault, half-bridges A, B, C, and D are shut down.

9.3.4.2 Overtemperature Protection

The TAS5755M has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state. The TAS5755M recovers automatically once the temperature drops approximately 30°C.

9.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5755M fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD

and AVDD are independently monitored, a supply-voltage drop below the UVP threshold on AVDD or either

PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state.

9.3.5 SSTIMER Functionality

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when

exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current

source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the

desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is

shut down, the drivers are placed in the high-impedance state and transition slowly down through a 3-kΩ resistor,

similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin

capacitance. Larger capacitors increase the start-up time, while capacitors smaller than 2.2 nF decrease the

start-up time. The SSTIMER pin can be left floating for BD modulation.

9.3.6 Clock, Autodetection, and PLL

The TAS5755M is an I²S slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the Clock Control Register (0x00).

The TAS5755M checks to verify that SCLK is a specific value of 32 f_S, 48 f_S, or 64 f_S. The DAP only supports a 1

× f_SLRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock

rates as defined in the clock-control register.

The TAS5755M has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and reverts to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

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Feature Description (接下页)

9.3.7 PWM Section

The TAS5755M DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can

be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For a detailed description of using audio processing features like DRC and EQ, see the TAS5755EVM User's

Guide (SLOU481) and TAS570X GDE Software Setup development tool documentation (SLOC124).

9.3.8 2.1-Mode Support

The TAS5755M uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode

operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05

bit D2 must be set to 1. The SSTIMER pin must be left floating in this mode.

9.3.9 I²C Compatible Serial Control Interface

The TAS5755M DAP has an I²C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent. The serial control interface supports

both single-byte and multiple-byte read and write operations for status registers and the general control registers

associated with the PWM.

9.3.10 Audio Serial Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5755M DAP accepts serial data

in 16-, 20-, or 24-bit left-justified, right-justified, and I²S serial data formats.

9.3.10.1 I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × f_Sis used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data bit positions.

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Feature Description (接下页)

2-Channel I²S (Philips Format) Stereo Input

32 Clks

LRCLK (Note Reversed Phase)

Right Channel

Left Channel

SCLK

MSB

LSB

MSB

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

0

1

0

23 22

19 18

15 14

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

16-Bit Mode

15 14

T0034-01

NOTE: All data presented in 2s-complement form with MSB first.

图 46. I²S 64-F_SFormat

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Feature Description (接下页)

2-Channel I²S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

24-Bit Mode

23 22

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

0

23 22

19 18

15 14

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

1

20-Bit Mode

19 18

16-Bit Mode

15 14

9

8

9

8

T0092-01

NOTE: All data presented in 2s-complement form with MSB first.

图 47. I²S 48-F_SFormat

2-Channel I²S (Philips Format) Stereo Input

16 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

0

15 14 13 12 11 10

9

8

5

4

3

2

1

T0266-01

NOTE: All data presented in 2s-complement form with MSB first.

图 48. I²S 32-F_SFormat

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Feature Description (接下页)

9.3.10.2 Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

48, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK

toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data bit positions.

2-Channel Left-Justified Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

23 22

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

0

1

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

15 14

16-Bit Mode

15 14

T0034-02

NOTE: All data presented in 2s-complement form with MSB first.

图 49. Left-Justified 64-F_SFormat

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Feature Description (接下页)

2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18 17

16-Bit Mode

15 14 13

9

8

15 14 13

9

8

T0092-02

NOTE: All data presented in 2s-complement form with MSB first.

图 50. Left-Justified 48-F_SFormat

2-Channel Left-Justified Stereo Input

16 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

1

0

15 14 13 12 11 10

9

8

5

4

3

2

1

0

T0266-02

NOTE: All data presented in 2s-complement form with MSB first.

图 51. Left-Justified 32-F_SFormat

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Feature Description (接下页)

9.3.10.3 Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

32, 48, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-

bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK

transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused

leading data bit positions.

2-Channel Right-Justified (Sony Format) Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

0

24-Bit Mode

23 22

19 18

15 14

1

0

23 22

19 18

15 14

1

20-Bit Mode

16-Bit Mode

0

T0034-03

图 52. Right-Justified 64-F_SFormat

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Feature Description (接下页)

2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22

19 18

15 14

6

5

2

1

0

23 22

19 18

15 14

6

5

2

1

0

20-Bit Mode

16-Bit Mode

0

T0092-03

图 53. Right-Justified 48-F_SFormat

图 54. Right-Justified 32-F_SFormat

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Feature Description (接下页)

9.3.11 Dynamic Range Control (DRC)

The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left/right channels and one

DRC for the low-band left/right channels.

The DRC input/output diagram is shown in 图 55.

1:1 Transfer Function

Implemented Transfer Function

T

Input Level (dB)

M0091-04

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.

• Each DRC has adjustable threshold levels.

• Programmable attack and decay time constants

• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,

and decay times can be set slow enough to avoid pumping.

图 55. Dynamic Range Control

a, w

T

a_a, w_a/ a_d, w_d

0x40

DRC1

DRC2

0x3C

0x3F

0x3B

0x3E

0x43

Alpha Filter Structure

S

a

–1

Z

w

B0265-04

T = 9.23 format, all other DRC coefficients are 3.23 format

图 56. DRC Structure

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9.4 Device Functional Modes

9.4.1 Stereo BTL Mode

The classic stereo mode of operation uses the TAS5755M device to amplify two independent signals, which

represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented

on differential output pairs shown as OUT_A and OUT_B for a channel and OUT_C and OUT_D for the other

one. The routing of the audio data which is presented on the OUT_x outputs can be changed according to the

PWM Output Mux Register (0x25). By default, the TAS5755M device is configured to output channel 1 to the

OUT_A and OUT_B outputs, and channel 2 to the OUT_C and OUT_D outputs. Stereo Mode operation outputs

are shown in 图 57.

图 57. Stereo BTL Mode

9.4.2 Mono PBTL Mode

When this mode of operation is used, the two stereo outputs of the device are placed in parallel one with another

to increase the power sourcing capabilities of the device. The TAS5755M supports parallel BTL (PBTL) mode

with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter.

The merging of the two output channels in this device can be done before the inductor portion of the output filter.

This is called Single-Filter PBTL, and this mono operation is shown in 图 58. More information about this can be

found in Single-Filter PBTL Mode section.

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Device Functional Modes (接下页)

图 58. Pre-Filter PBTL

On the input side of the TAS5755M device, the input signal to the mono amplifier can be selected from a mix, left

or right frame from an I²S, LJ, or RJ signal. The routing of the audio data which is presented on the SPK_OUTx

outputs must be configured with the PWM Output Mux Register (0x25) and PWM Shutdown Group Register

(0x19).

Refer to the Mono Parallel Bridge Tied Load Application section for more details of the correct PBTL output

connection of the TAS5755M.

9.4.3 2.1 Mode

2.1 Mode is defined as the application of two Single ended channels and one BTL channel used in systems

where a third sub channel is required. Generally, both single-ended inputs drive the Left and Right channels,

while the BTL channel drives a low-frequency content channel called often Subwoofer. More information about

this can be found in the 2.1-Mode Support section.

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Device Functional Modes (接下页)

图 59. 2.1 Mode

Refer to 2.1 Application section for more details of the correct 2.1 output connection of the TAS5755M.

9.5 Programming

9.5.1 I²C Serial Control Interface

The TAS5755M DAP has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.

This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The

control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation

(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.

9.5.1.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in 图 60. The master

generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and

then waits for an acknowledge condition. The TAS5755M holds SDA low during the acknowledge clock period to

indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device

is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same

signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the

SDA and SCL signals to set the high level for the bus.

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Programming (接下页)

8-Bit Register Data For

Address (N)

8-Bit Register Data For

Address (N)

R/

W

8-Bit Register Address (N)

7-Bit Slave Address

A

SDA

SCL

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Start

Stop

T0035-01

图 60. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in 图 60.

The 7-bit address for TAS5755M is 0011 011 (0x36).

9.5.1.2 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received

when a stop command (or another start command) is received, the received data is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The

TAS5755M also supports sequential I²C addressing. For write transactions, if a subaddress is issued followed by

data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has taken place,

and the data for all 16 subaddresses is successfully received by the TAS5755M. For I²C sequential-write

transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,

before a stop or start is transmitted, determines how many subaddresses are written. As was true for random

addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data

is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is

accepted; only the incomplete data is discarded.

9.5.1.3 Single-Byte Write

As shown in 图 61, a single-byte data-write transfer begins with the master device transmitting a start condition

followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data

transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address and the

read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes

corresponding to the TAS5755M internal memory address being accessed. After receiving the address byte, the

TAS5755M again responds with an acknowledge bit. Next, the master device transmits the data byte to be

written to the memory address being accessed. After receiving the data byte, the TAS5755M again responds

with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-

write transfer.

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Programming (接下页)

Start

Condition

Acknowledge

R/W

A6 A5 A4 A3 A2 A1 A0

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

Data Byte

Stop

Condition

T0036-01

图 61. Single-Byte Write Transfer

9.5.1.4 Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes

are transmitted by the master device to the DAP as shown in 图 62. After receiving each data byte, the

TAS5755M responds with an acknowledge bit.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

图 62. Multiple-Byte Write Transfer

9.5.1.5 Single-Byte Read

As shown in 图 63, a single-byte data-read transfer begins with the master device transmitting a start condition,

followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a

read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5755M address and the

read/write bit, TAS5755M responds with an acknowledge bit. In addition, after sending the internal memory

address byte or bytes, the master device transmits another start condition followed by the TAS5755M address

and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving

the address and the read/write bit, the TAS5755M again responds with an acknowledge bit. Next, the TAS5755M

transmits the data byte from the memory address being read. After receiving the data byte, the master device

transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A0 ACK

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and

Read/Write Bit

Data Byte

Stop

Condition

T0036-03

图 63. Single-Byte Read Transfer

9.5.1.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes

are transmitted by the TAS5755M to the master device as shown in 图 64. Except for the last data byte, the

master device responds with an acknowledge bit after receiving each data byte.

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Programming (接下页)

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

D0 ACK D7

A6

A0 R/W ACK A7 A6 A5

A0 ACK

A6

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

图 64. Multiple-Byte Read Transfer

9.5.2 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23

numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This

is shown in 图 65.

2^–23Bit

2^–5Bit

2^–1Bit

2⁰Bit

2¹Bit

Sign Bit

S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

M0125-01

图 65. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in 图 65. If the most

significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If

the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted,

a 1 added to the result, and then the weighting shown in 图 66 applied to obtain the magnitude of the negative

number.

2¹Bit

2⁰Bit

2^–1Bit

2^–4Bit

2^–23Bit

(1 or 0) ´ 2¹+ (1 or 0) ´ 2⁰+ (1 or 0) ´ 2^–1+ ....... (1 or 0) ´ 2^–4+ ....... (1 or 0) ´ 2^–23

M0126-01

图 66. Conversion Weighting Factors — 3.23 Format To Floating Point

Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit

number (4-byte or 8-digit hexadecimal number) is shown in 图 67.

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Programming (接下页)

Fraction

Digit 6

Sign

Bit

Fraction

Digit 1

Fraction

Digit 2

Fraction

Digit 3

Fraction

Digit 4

Fraction

Digit 5

Integer

Digit 1

u

x

x.

x

x x x x

0

S

Coefficient

Digit 8

Coefficient

Digit 7

Coefficient

Digit 6

Coefficient

Digit 5

Coefficient

Digit 4

Coefficient

Digit 3

Coefficient

Digit 2

Coefficient

Digit 1

u = unused or don’t care bits

Digit = hexadecimal digit

M0127-01

图 67. Alignment of 3.23 Coefficient in 32-Bit I²C Word

表 1. Sample Calculation for 3.23 Format

db

0

LINEAR

1

DECIMAL

8,388,608

14,917,288

4,717,260

HEX (3.23 Format)

80 0000

5

1.77

00E3 9EA8

–5

X

0.56

L = 10^(X/20)

0047 FACC

D = 8,388,608 × L H = dec2hex (D, 8)

表 2. Sample Calculation for 9.17 Format

db

0

LINEAR

1

DECIMAL

131,072

HEX (9.17 Format)

2 0000

5

1.77

231,997

3 8A3D

–5

X

0.56

L = 10^(X/20)

73,400

1 1EB8

D = 131,072 × L

H = dec2hex (D, 8)

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9.6 Register Maps

9.6.1 Register Map Summary

表 3. Serial Control Interface Register Summary

NO. OF

BYTES

SUBADDRESS

REGISTER NAME

CONTENTS⁽¹⁾

INITIALIZATION VALUE

0x00

0x01

0x02

0x03

0x04

Clock control register

Device ID register

1

Description shown in subsequent section

0x6C

0x00

0xA0

0x05

Error status register

System control register 1

Serial data interface

register

0x05

0x06

System control register 2

Soft mute register

Master volume

1

Description shown in subsequent section

Reserved⁽²⁾

0x40

0x00

0x07

0xFF (mute)

0x30 (0 dB)

0x08

Channel 1 vol

0x09

Channel 2 vol

0x0A

Channel 3 vol

0x0B–0x0D

0x0E

Volume configuration

register

Description shown in subsequent section

0x91

0x0F

0x10

1

Reserved⁽²⁾

Modulation limit register

IC delay channel 1

IC delay channel 2

IC delay channel 3

IC delay channel 4

Description shown in subsequent section

Reserved⁽²⁾

0x02

0xAC

0x54

0xAC

0x54

0x11

0x12

0x13

0x14

0x15-0x18

0x19

PWM channel shutdown

group register

Description shown in subsequent section

0x30

0x1A

0x1B

Start/stop period register

Oscillator trim register

BKND_ERR register

1

0x0F

0x82

0x02

0x1C

1

0x1D–0x1F

0x20

1

Reserved⁽²⁾

Input MUX register

4

Description shown in subsequent section

Reserved⁽²⁾

0x0001 7772

0x0000 4303

0x21

Ch 4 source select register

4

0x22 -0x24

0x25

4

PWM MUX register

ch1_bq[0]

4

Description shown in subsequent section

Reserved⁽²⁾

0x0102 1345

0x26-0x28

0x29

4

20

u[31:26], b0[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x2A

ch1_bq[1]

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

(1) A u indicates unused bits.

(2) Reserved registers must not be accessed.

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Register Maps (接下页)

表 3. Serial Control Interface Register Summary (接下页)

NO. OF

BYTES

SUBADDRESS

REGISTER NAME

ch1_bq[2]

CONTENTS⁽¹⁾

INITIALIZATION VALUE

0x2B

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

ch1_bq[3]

ch1_bq[4]

ch1_bq[5]

ch1_bq[6]

ch2_bq[0]

ch2_bq[1]

ch2_bq[2]

ch2_bq[3]

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Register Maps (接下页)

表 3. Serial Control Interface Register Summary (接下页)

NO. OF

BYTES

SUBADDRESS

REGISTER NAME

CONTENTS⁽¹⁾

INITIALIZATION VALUE

0x34

ch2_bq[4]

ch2_bq[5]

ch2_bq[6]

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

Reserved⁽²⁾

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x35

0x36

0x37 - 0x39

0x3A

4

8

DRC1 ae⁽³⁾

DRC1 (1 – ae)

DRC1 aa

u[31:26], ae[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0xFDA2 1490

0x0384 2109

0x0008 4210

0xFDA2 1490

0x0384 2109

0x0008 4210

0x0000 0000

u[31:26], (1 – ae)[25:0]

u[31:26], aa[25:0]

0x3B

0x3C

0x3D

0x3E

0x3F

8

DRC1 (1 – aa)

DRC1 ad

u[31:26], (1 – aa)[25:0]

u[31:26], ad[25:0]

DRC1 (1 – ad)

DRC2 ae

u[31:26], (1 – ad)[25:0]

u[31:26], ae[25:0]

DRC 2 (1 – ae)

DRC2 aa

u[31:26], (1 – ae)[25:0]

u[31:26], aa[25:0]

DRC2 (1 – aa)

DRC2 ad

u[31:26], (1 – aa)[25:0]

u[31:26], ad[25:0]

DRC2 (1 – ad)

DRC1-T

u[31:26], (1 – ad)[25:0]

T1[31:0] (9.23 format)

u[31:26], K1[25:0]

0x40

0x41

4

DRC1-K

0x42

DRC1-O

4

u[31:26], O1[25:0]

0x43

DRC2-T

4

T2[31:0] (9.23 format)

u[31:26], K2[25:0]

0x44

DRC2-K

4

0x45

DRC2-O

4

u[31:26], O2[25:0]

0x46

DRC control

4

Description shown in subsequent section

Reserved⁽²⁾

0x47–0x4F

0x50

4

Bank switch control

Ch 1 output mixer

4

Description shown in subsequent section

Ch 1 output mix1[2]

Ch 1 output mix1[1]

Ch 1 output mix1[0]

Ch 2 output mix2[2]

Ch 2 output mix2[1]

Ch 2 output mix2[0]

0x0F70 8000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x51

12

0x52

Ch 2 output mixer

12

(3) "ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.

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Register Maps (接下页)

表 3. Serial Control Interface Register Summary (接下页)

NO. OF

BYTES

SUBADDRESS

REGISTER NAME

Ch 1 input mixer

CONTENTS⁽¹⁾

INITIALIZATION VALUE

0x53

16

12

Ch 1 input mixer[3]

Ch 1 input mixer[2]

Ch 1 input mixer[1]

Ch 1 input mixer[0]

Ch 2 input mixer[3]

Ch 2 input mixer[2]

Ch 2 input mixer[1]

Ch 2 input mixer[0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0002 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x54

0x55

Ch 2 input mixer

Channel 3 input mixer

Channel 3 input mixer [2]

Channel 3 input mixer [1]

Channel 3 input mixer [0]

u[31:26], post[25:0]

u[31:26], pre[25:0] (9.17 format)

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x56

0x57

0x58

Output post-scale

Output pre-scale

ch1 BQ[7]

4

20

0x59

0x5A

0x5B

0x5C

0x5D

ch1 BQ[8]

20

Subchannel BQ[0]

Subchannel BQ[1]

ch2 BQ[7]

ch2 BQ[8]

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Register Maps (接下页)

表 3. Serial Control Interface Register Summary (接下页)

NO. OF

BYTES

SUBADDRESS

REGISTER NAME

CONTENTS⁽¹⁾

INITIALIZATION VALUE

0x5E

pseudo_ch2 BQ[0]

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

Reserved⁽²⁾

0x0080 0000

0x0000 0000

0x5F

0x60

4

8

Channel 4 (subchannel)

output mixer

Ch 4 output mixer[1]

Ch 4 output mixer[0]

Ch 4 input mixer[1]

Ch 4 input mixer[0]

Post-IDF attenuation register

Reserved⁽²⁾

0x0000 0000

0x0080 0000

0x0040 0000

0x0000 0080

0x0000 0000

0x61

Channel 4 (subchannel)

input mixer

8

4

0x62

0x63–0xF7

0xF8

IDF post scale

Device address enable

register

4

Write F9 A5 A5 A5 in this register to enable write to

device address update (0xF9)

0xF9

Device address Update

Register

u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id

(7:1) defines the new device address

Reserved⁽²⁾

0X0000 0036

0x0000 0000

0xFA–0xFF

All DAP coefficients are 3.23 format unless specified otherwise.

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9.6.2 Register Maps

9.6.2.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5755M. The clock control register contains

the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The

device accepts a 64 f_Sor 32 f_SSCLK rate for all MCLK ratios, but accepts a 48 f_SSCLK rate for MCLK ratios of

192 f_Sand 384 f_Sonly.

表 4. Clock Control Register (0x00)

D7

0

1

–

D6

0

1

0

1

–

D5

0

1

0

1

0

1

0

1

–

D4

–

0

1

–

D3

–

0

1

0

1

–

D2

–

0

1

0

1

0

1

0

1

–

D1

–

0

–

D0

–

0

FUNCTION

f_S= 32-kHz sample rate

Reserved⁽¹⁾

f_S= 44.1/48-kHz sample rate⁽²⁾

f_S= 16-kHz sample rate

f_S= 22.05/24-kHz sample rate

f_S= 8-kHz sample rate

f_S= 11.025/12-kHz sample rate

(3)

MCLK frequency = 64 × f_S

(3)

MCLK frequency = 128 × f_S

(4)

MCLK frequency = 192 × f_S

(2)(5)

MCLK frequency = 256 × f_S

MCLK frequency = 384 × f_S

MCLK frequency = 512 × f_S

Reserved⁽¹⁾

Reserved^{(1) (2)}

(1) Reserved registers must not be accessed.

(2) Default values are in bold.

(3) Only available for 44.1-kHz and 48-kHz rates

(4) Rate only available for 32/44.1/48-kHz sample rates

(5) Not available at 8 kHz

9.6.2.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision.

表 5. General Status Register (0x01)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

Identification code

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9.6.2.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the

register (write zeroes) and then read them to determine if they are persistent errors.

Error Definitions:

•

MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.

SCLK Error: The number of SCLKs per LRCLK is changing.

LRCLK Error: LRCLK frequency is changing.

Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.

表 6. Error Status Register (0x02)

D7

1

D6

-

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

FUNCTION

MCLK error

–

1

–

0

–

PLL autolock error

SCLK error

–

1

–

1

–

LRCLK error

Frame slip

–

1

–

1

–

Clip indicator

–

1

–

Overcurrent, overtemperature, or undervoltage errors

–

0

Reserved

No errors⁽¹⁾

0

–

(1) Default values are in bold.

9.6.2.4 System Control Register 1 (0x03)

The system control register 1 has several functions:

Bit D7:

Bit D5:

If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).

If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the

same time as the volume ramp defined in register 0x0E.

If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step

volume ramp

Bits D1–D0: Select de-emphasis

表 7. System Control Register 1 (0x03)

D7

0

1

–

D6

–

0

–

D5

–

0

1

–

D4

–

0

–

D3

–

0

–

D2

–

0

–

D1

–

0

1

D0

–

0

1

0

1

FUNCTION

PWM high-pass (dc blocking) disabled

PWM high-pass (dc blocking) enabled⁽¹⁾

Reserved⁽¹⁾

Soft unmute on recovery from clock error

Hard unmute on recovery from clock error⁽¹⁾

Reserved⁽¹⁾

No de-emphasis⁽¹⁾

De-emphasis for f_S= 32 kHz

De-emphasis for f_S= 44.1 kHz

De-emphasis for f_S= 48 kHz

(1) Default values are in bold.

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9.6.2.5 Serial Data Interface Register (0x04)

As shown in 表 8, the TAS5755M supports 9 serial data modes. The default is 24-bit, I²S mode,

表 8. Serial Data Interface Control Register (0x04)

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD

LENGTH

D7–D4

D3

D2

D1

D0

Right-justified

16

20

24

16

20

24

16

20

24

0000

000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Right-justified

I²S

0000

(1)

I²S

Left-justified

Reserved

(1) Default values are in bold.

9.6.2.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs

are shut down (hard mute).

表 9. System Control Register 2 (0x05)

D7 D6 D5

D4

–

D3

–

0

1

–

-

D2

–

D1

–

D0

–

FUNCTION

0

1

–

0

1

–

Mid-Z ramp disabled⁽¹⁾

–

Mid-Z ramp enabled

–

Exit all-channel shutdown (normal operation)

Enter all-channel shutdown (hard mute)⁽¹⁾

Sub-channel in AD Mode

–

Sub-channel in BD Mode

2.0 mode [2.0 BTL]⁽¹⁾

–

0

–

0

1

–

0

1

–

0

2.1 mode [2 SE + 1 BTL]

ADR/FAULT pin is configured as to serve as an address input only⁽¹⁾

ADR/FAULT pin is configured as fault output

Reserved⁽¹⁾

(1) Default values are in bold.

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9.6.2.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

表 10. Soft Mute Register (0x06)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

0

–

0

–

0

–

0

–

0

–

Reserved⁽¹⁾

0

–

Soft unmute channel 3⁽¹⁾

Soft mute channel 3

Soft unmute channel 2⁽¹⁾

Soft mute channel 2

Soft unmute channel 1⁽¹⁾

Soft mute channel 1

1

–

0

–

1

–

0

–

1

(1) Default values are in bold.

9.6.2.8 Volume Registers (0x07, 0x08, 0x09, 0x0A)

Step size is 0.5 dB.

Master volume

– 0x07 (default is mute)

– 0x08 (default is 0 dB)

– 0x09 (default is 0 dB)

– 0x0A (default is 0 dB)

Channel-1 volume

Channel-2 volume

Channel-3 volume

表 11. Volume Registers (0x07, 0x08, 0x09, 0x0A)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

24 dB

0

1

0

0 dB (default for individual channel volume)⁽¹⁾

1

0

–103 dB

(1)

1

Soft mute (default for master volume)

(1) Default values are in bold.

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9.6.2.9 Volume Configuration Register (0x0E)

Bits

Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the

D2–D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of

the I²S data as follows

Sample Rate (KHz)

8/16/32

Approximate Ramp Rate

125 µs/step

11.025/22.05/44.1

12/24/48

90.7 µs/step

83.3 µs/step

表 12. Volume Control Register (0x0E)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

FUNCTION

1

–

0

1

–

0

1

–

1

–

0

–

0

1

0

1

X

Reserved⁽¹⁾

(2) (1)

–

Subchannel (ch4) volume = ch1 volume

Subchannel volume = register 0x0A⁽²⁾

Ch3 volume = ch2 volume⁽¹⁾

Ch3 volume = register 0x0A

–

0

Volume slew 512 steps (43-ms volume ramp time at 48 kHz)

Volume slew 1024 steps (85-ms volume ramp time at 48 kHz)⁽¹⁾

Volume slew 2048 steps (171- ms volume ramp time at 48 kHz)

Volume slew 256 steps (21-ms volume ramp time at 48 kHz)

Reserved

0

1

0

1

X

(1) Default values are in bold.

(2) Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)].

9.6.2.10 Modulation Limit Register (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform.

表 13. Modulation Limit Register (0x10)

D7

–

D6

–

D5

–

D4

–

D3

–

D2

0

D1

0

D0

0

MODULATION LIMIT

99.2%

–

0

1

98.4%

–

0

1

0

97.7%⁽¹⁾

–

0

1

96.9%

–

1

0

96.1%

–

1

0

1

95.3%

–

1

0

94.5%

–

1

93.8%

0

–

Reserved

(1) Default values are in bold.

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9.6.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

表 14. Channel Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

BITS DEFINITION

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

–

D0

–

FUNCTION

Minimum absolute delay, 0 DCLK cycles

Maximum positive delay, 31 × 4 DCLK cycles

Maximum negative delay, –32 × 4 DCLK cycles

Reserved

0

1

–

1

0

–

0

SUBADDRESS

0x11

D7

1

D6

0

D5

1

D4

0

D3

1

D2

1

D1

–

D0

–

DELAY = (VALUE) × 4 DCLKs

Default value for channel 1⁽¹⁾

Default value for channel 2⁽¹⁾

0x12

0

1

0

1

0

1

–

(1)

0x13

1

0

1

0

1

–

Default value for channel 1

(1)

0x14

0

1

0

1

0

1

–

Default value for channel 2

(1) Default values are in bold.

ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore,

appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD

mode, then update these registers before coming out of all-channel shutdown.

REGISTER

0x11

AD MODE

BD MODE

AC

54

B8

60

A0

48

0x12

0x13

AC

54

0x14

9.6.2.12 PWM Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The value must be 0x30 for BTL mode and

0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the

state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group

register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is

set to 0 in system control register 2, 0x05).

表 15. Shutdown Group Register (0x19)

D7

0

–

D6

–

0

–

D5

–

1

–

D4

–

1

–

D3

–

0

1

–

D2

–

0

1

–

D1

–

0

1

–

D0

–

0

1

FUNCTION

Reserved⁽¹⁾

PWM channel 4 does not belong to shutdown group.⁽¹⁾

PWM channel 4 belongs to shutdown group.

PWM channel 3 does not belong to shutdown group.⁽¹⁾

PWM channel 3 belongs to shutdown group.

PWM channel 2 does not belong to shutdown group.⁽¹⁾

PWM channel 2 belongs to shutdown group.

PWM channel 1 does not belong to shutdown group.⁽¹⁾

PWM channel 1 belongs to shutdown group.

(1) Default values are in bold.

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9.6.2.13 Start/Stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down

command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times

are only approximate and vary depending on device activity level and I²S clock stability.

表 16. Start/Stop Period Register (0x1A)

D7 D6 D5 D4 D3

D2

–

0

1

0

1

0

1

D1

–

0

1

0

1

0

1

0

1

0

1

0

1

D0

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FUNCTION

0

1

–

0

–

0

–

0

1

–

0

1

0

1

SSTIMER enabled⁽¹⁾

SSTIMER disabled

Reserved⁽¹⁾

No 50% duty cycle start/stop period

16.5-ms 50% duty cycle start/stop period

23.9-ms 50% duty cycle start/stop period

31.4-ms 50% duty cycle start/stop period

40.4-ms 50% duty cycle start/stop period

53.9-ms 50% duty cycle start/stop period

70.3-ms 50% duty cycle start/stop period

94.2-ms 50% duty cycle start/stop period

125.7-ms 50% duty cycle start/stop period⁽¹⁾

164.6-ms 50% duty cycle start/stop period

239.4-ms 50% duty cycle start/stop period

314.2-ms 50% duty cycle start/stop period

403.9-ms 50% duty cycle start/stop period

538.6-ms 50% duty cycle start/stop period

703.1-ms 50% duty cycle start/stop period

942.5-ms 50% duty cycle start/stop period

1256.6-ms 50% duty cycle start/stop period

1728.1-ms 50% duty cycle start/stop period

2513.6-ms 50% duty cycle start/stop period

3299.1-ms 50% duty cycle start/stop period

4241.7-ms 50% duty cycle start/stop period

5655.6-ms 50% duty cycle start/stop period

7383.7-ms 50% duty cycle start/stop period

9897.3-ms 50% duty cycle start/stop period

13,196.4-ms 50% duty cycle start/stop period

(1) Default values are in bold.

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9.6.2.14 Oscillator Trim Register (0x1B)

The TAS5755M PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This

reduces system cost because an external reference is not required. Currently, TI recommends a reference

resistor value of 18.2 kΩ (1%). This must be connected between OSC_RES and DVSSO.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

注

Trim must always be run following reset of the device.

表 17. Oscillator Trim Register (0x1B)

D7

0

D6

–

D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

–

0

–

0

–

0

–

Reserved⁽¹⁾

–

0

–

Oscillator trim not done (read-only)⁽¹⁾

Oscillator trim done (read only)

Reserved⁽¹⁾

–

1

–

0

–

0

–

Select factory trim (Write a 0 to select factory trim; default is 1.)

Factory trim disabled⁽¹⁾

–

1

–

0

Reserved⁽¹⁾

(1) Default values are in bold.

9.6.2.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset stopping all

PWM activity. Subsequently, the modulator waits approximately for the time listed in 表 18 before attempting to

re-start the power stage.

表 18. BKND_ERR Register (0x1C)⁽¹⁾

D7 D6 D5 D4 D3

D2

0

D1

0

D0

X

0

FUNCTION

0

–

0

–

0

–

0

–

0

1

Reserved

0

1

Set back-end reset period to 299 ms⁽²⁾

Set back-end reset period to 449 ms

Set back-end reset period to 598 ms

Set back-end reset period to 748 ms

Set back-end reset period to 898 ms

Set back-end reset period to 1047 ms

Set back-end reset period to 1197 ms

Set back-end reset period to 1346 ms

Set back-end reset period to 1496 ms

0

1

0

1

0

1

0

1

0

1

0

1

X

1

X

(1) This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.

(2) Default values are in bold.

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9.6.2.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal

channels.

表 19. Input Multiplexer Register (0x20)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Channel-1 AD mode⁽¹⁾

Channel-1 BD mode

SDIN-L to channel 1⁽¹⁾

SDIN-R to channel 1

Reserved

Reserved⁽¹⁾

D23

0

D22

–

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

1

–

0

–

0

1

–

0

1

0

–

0

1

–

Reserved

–

1

0

–

Reserved

–

1

0

1

–

Reserved

–

1

0

–

Ground (0) to channel 1

Reserved

–

1

–

0

–

Channel 2 AD mode⁽¹⁾

Channel 2 BD mode

SDIN-L to channel 2

SDIN-R to channel 2⁽¹⁾

Reserved

–

1

–

0

–

0

1

–

0

1

0

–

0

1

Reserved

–

1

0

Reserved

–

1

0

1

Reserved

–

1

0

Ground (0) to channel 2

Reserved

–

1

D15

0

D14

1

D13

1

D12

1

D11

0

D10

1

D9

1

D8

1

FUNCTION

Reserved⁽¹⁾

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

1

D0

0

FUNCTION

(1) Default values are in bold.

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9.6.2.17 Channel 4 Source Select Register (0x21)

This register selects the channel 4 source.

表 20. Subchannel Control Register (0x21)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

D14

D13

D12

D11

D10

D9

D8

Select SDIN path (third path), not available in

TAS5755M⁽¹⁾

0

1

0

1

–

0

1

(L + R)/2

Left-channel post-BQ⁽¹⁾

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

1

D0

1

FUNCTION

Reserved⁽¹⁾

(1) Default values are in bold.

9.6.2.18 PWM Output Mux Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be

output to any external output pin.

Bits D21–D20:

Bits D17–D16:

Bits D13–D12:

Bits D09–D08:

Selects which PWM channel is output to OUT_A

Selects which PWM channel is output to OUT_B

Selects which PWM channel is output to OUT_C

Selects which PWM channel is output to OUT_D

注

Channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.

表 21. PWM Output Mux Register (0x25)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

1

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

FUNCTION

Reserved⁽¹⁾

–

0

–

Multiplex PWM 1 to OUT_A⁽¹⁾

Multiplex PWM 2 to OUT_A

Multiplex PWM 3 to OUT_A

Multiplex PWM 4 to OUT_A

Reserved⁽¹⁾

–

0

1

–

1

0

–

1

–

0

–

0

Multiplex PWM 1 to OUT_B

Multiplex PWM 2 to OUT_B

Multiplex PWM 3 to OUT_B⁽¹⁾

Multiplex PWM 4 to OUT_B

–

0

1

–

1

0

–

1

(1) Default values are in bold.

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表 21. PWM Output Mux Register (0x25) (接下页)

D15

0

D14

0

D13

–

D12

–

D11

–

D10

–

D9

–

D8

–

FUNCTION

Reserved⁽¹⁾

–

0

–

Multiplex PWM 1 to OUT_C

Multiplex PWM 2 to OUT_C⁽¹⁾

Multiplex PWM 3 to OUT_C

Multiplex PWM 4 to OUT_C

Reserved⁽¹⁾

–

0

1

–

1

0

–

1

–

0

–

0

Multiplex PWM 1 to OUT_D

Multiplex PWM 2 to OUT_D

Multiplex PWM 3 to OUT_D

Multiplex PWM 4 to OUT_D⁽¹⁾

–

0

1

–

1

0

–

1

D7

0

D6

1

D5

0

D4

0

D3

0

D2

1

D1

0

D0

1

FUNCTION

Reserved⁽¹⁾

9.6.2.19 DRC Control Register (0x46)

Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.

表 22. DRC Control Register (0x46)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

(1)

Reserved

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

Reserved⁽¹⁾

D7

0

D6

0

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

0

–

Disable complementary (1 - H) low-pass filter generation

Enable complementary (1 - H) low-pass filter generation

–

1

–

0

–

1

–

0

Reserved⁽¹⁾

–

0

1

–

0

1

DRC2 turned OFF⁽¹⁾

DRC2 turned ON

DRC1 turned OFF⁽¹⁾

DRC1 turned ON

–

(1) Default values are in bold.

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9.6.2.20 Bank Switch and EQ Control Register (0x50)

表 23. Bank Switching Command Register (0x50)

D31

0

D30

–

D29

–

D28

–

D27

–

D26

–

D25

–

D24

–

FUNCTION

32 kHz, does not use bank 3⁽¹⁾

1

–

32 kHz, uses bank 3

–

0

–

Reserved⁽¹⁾

–

0

–

Reserved⁽¹⁾

–

0

–

44.1/48 kHz, does not use bank 3⁽¹⁾

44.1/48 kHz, uses bank 3

16 kHz, does not use bank 3

16 kHz, uses bank 3⁽¹⁾

–

1

–

0

–

1

–

0

–

22.025/24 kHz, does not use bank 3

22.025/24 kHz, uses bank 3⁽¹⁾

8 kHz, does not use bank 3

8 kHz, uses bank 3⁽¹⁾

–

1

–

0

–

1

–

0

11.025 kHz/12, does not use bank 3

11.025/12 kHz, uses bank 3⁽¹⁾

–

1

D23

0

D22

–

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

FUNCTION

32 kHz, does not use bank 2⁽¹⁾

1

–

32 kHz, uses bank 2

–

1

–

Reserved⁽¹⁾

–

1

–

Reserved⁽¹⁾

–

0

–

44.1/48 kHz, does not use bank 2

44.1/48 kHz, uses bank 2⁽¹⁾

16 kHz, does not use bank 2⁽¹⁾

16 kHz, uses bank 2

–

1

–

0

–

1

–

0

–

22.025/24 kHz, does not use bank 2⁽¹⁾

22.025/24 kHz, uses bank 2

8 kHz, does not use bank 2⁽¹⁾

8 kHz, uses bank 2

–

1

–

0

–

1

–

0

11.025/12 kHz, does not use bank 2⁽¹⁾

11.025/12 kHz, uses bank 2

FUNCTION

–

1

D15

0

D14

–

D13

–

D12

–

D11

–

D10

–

D9

–

D8

–

32 kHz, does not use bank 1

32 kHz, uses bank 1⁽¹⁾

1

–

0

–

Reserved⁽¹⁾

–

0

–

Reserved⁽¹⁾

–

0

–

44.1/48 kHz, does not use bank 1⁽¹⁾

44.1/48 kHz, uses bank 1

16 kHz, does not use bank 1⁽¹⁾

16 kHz, uses bank 1

–

1

–

0

–

1

–

0

–

22.025/24 kHz, does not use bank 1⁽¹⁾

22.025/24 kHz, uses bank 1

8 kHz, does not use bank 1⁽¹⁾

8 kHz, uses bank 1

–

1

–

0

–

1

–

0

11.025/12 kHz, does not use bank 1⁽¹⁾

–

1

11.025/12 kHz, uses bank 1

(1) Default values are in bold.

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表 23. Bank Switching Command Register (0x50) (接下页)

D7

0

D6

D5

D4

D3

D2

D1

D0

FUNCTION

EQ ON

1

–

0

–

0

1

–

EQ OFF (bypass BQ 0-7 of channels 1 and 2)

Reserved⁽¹⁾

Ignore bank-mapping in bits D31–D8.Use default mapping.⁽¹⁾

–

Use bank-mapping in bits D31–D8.

L and R can be written independently.⁽¹⁾

–

0

–

L and R are ganged for EQ biquads; a write to left-channel BQ is also

written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also

0x58–0x59 is ganged to 0x5C–0x5D)

–

1

–

0

–

0

1

–

0

1

0

1

–

0

1

0

1

0

1

X

Reserved⁽¹⁾

No bank switching. All updates to DAP⁽¹⁾

Configure bank 1 (32 kHz by default)

Configure bank 2 (44.1/48 kHz by default)

Configure bank 3 (other sample rates by default)

Automatic bank selection

Reserved

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

图 68, 图 71, and 图 72 highlight the required external components and system level connections for proper

operation of the device in several popular use cases.

Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible

modules allow full evaluation of the device in the most common modes of operation. Any design variation can be

supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the

audio amplifier discussion forum for additional information.

10.2 Typical Applications

10.2.1 Stereo Bridge Tied Load Application

A stereo system generally refers to a system in which there are two full range speakers without a separate

amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are

presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two

separate speakers.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the

audio for the left channel and the other channel containing the audio for the right channel.

The Stereo BTL Configuration with Headphone and Line Driver Amplifier application is shown in 图 68.

3.3V

8V-24V

PVDD

AVDD/DVDD

OUT_A

LRCLK

SCLK

MCLK

SDIN

Digital

Audio

Source

BST_A

LC_BTL

BST_B

OUT_B

I²C

Control

SDA

SCL

RESET

PDN

Control

Inputs

OUT_A

BST_A

LC_BTL

PLL_FLTP

PLL_FLTM

Loop

Filter

BST_B

OUT_B

图 68. Stereo Bridge Tied Load Application

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Typical Applications (接下页)

10.2.1.1 Design Requirements

表 24. Design Requirements

PARAMETER

Low Power Supply

High Power Supply

EXAMPLE

3.3 V

8 V to 24 V

I²S Compliant Master

I²C Compliant Master

GPIO Control

Host Processor

Output Filters

Speaker

Inductor-Capacitor Low Pass Filter

4 Ω minimum

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found in the TAS5755EVM User’s

Guide (SLOU481A). The device was tested with this list of components; deviation from this list of typical

application components, unless recommended by this document, may produce unwanted results, which could

range from degradation of audio performance to destructive failure of the device.

10.2.1.2.2 I²C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical

Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part

of the associated passive components for the System Processor. These resistor values must be chosen per the

guidance provided in the I²C Specification.

10.2.1.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5755M are described in previous sections. As discussed, whenever a static digital

pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it must be connected to

DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not,

however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor

can be used to tie all static I/O lines HIGH to reduce BOM count.

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3 V

AVDD/DVDD

0 ns

2 ms

PDN

0 ns

2

I C

2 ms

RESET

2 ms

0 ns

8 V

PVDD

6 V

T0420-05

图 70. Power-Loss Sequence

10.2.1.2.4.1 Initialization Sequence

Use the following sequence to power up and initialize the device:

1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.

2. Initialize digital inputs and PVDD supply as follows:

•

Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that

all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1,

and wait at least another 13.5 ms.

•

Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs

after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.

3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.

4. Configure the DAP via I²C, see TAS5755EVM Evaluation Module User's Guide (SLOU481A) for

typical values.

5. Configure remaining registers.

6. Exit shutdown (sequence defined in Shutdown Sequence).

10.2.1.2.4.2 Normal Operation

The following are the only events supported during normal operation:

1. Writes to master/channel volume registers

2. Writes to soft-mute register

3. Enter and exit shutdown (sequence defined in Shutdown Sequence)

注

Event 3 is not supported for 240 ms + 1.3 × t_startafter trim following AVDD/DVDD power-

up ramp (where t_startis specified by register 0x1A).

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10.2.1.2.4.3 Shutdown Sequence

Enter:

1. Write 0x40 to register 0x05.

2. Wait at least 1 ms + 1.3 × t_stop(where t_stopis specified by register 0x1A).

3. If desired, reconfigure by returning to step 4 of initialization sequence.

Exit:

1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms

after trim following AVDD/DVDD power-up ramp).

2. Wait at least 1 ms + 1.3 × t_start(where t_startis specified by register 0x1A).

3. Proceed with normal operation.

10.2.1.2.4.4 Power-Down Sequence

Use the following sequence to power down the device and its supplies:

1. If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of

sudden power loss, assert PDN = 0 and wait at least 2 ms.

2. Assert RESET = 0.

3. Drive digital inputs low and ramp down PVDD supply as follows:

•

Drive all digital inputs low after RESET has been low for at least 2 µs.

Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at

least 2 µs.

4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and

that it is never more than 2.5 V below the digital inputs.

10.2.1.3 Application Curves

space

表 25. Relevant Performance Curves

CURVE TITLE

FIGURE

Output Power vs Supply Voltage (2.0 BTL Mode)

图 18

With 4Ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V

Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode)

Total Harmonic Distortion vs Frequency (2.0 BTL Mode)

Efficiency vs Output Power (2.0 BTL Mode)

图 19

图 20

图 21

图 22

图 23

图 24

图 25

图 26

图 27

图 28

图 29

图 30

图 31

Crosstalk vs Frequency (2.0 BTL Mode)

Power vs Supply Voltage (2.0 BTL Mode)

Idle Channel Noise vs Supply Voltage (2.0 BTL Mode)

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10.2.2 Mono Parallel Bridge Tied Load Application

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge

Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the

loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5755M

device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the

amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while

the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an

audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed

together and sent through a low-pass filter in order to create a single audio signal which contains the low

frequency information of the two channels.

The Mono Parallel Bridge Tied Load application is shown in 图 71.

3.3 V

8 V–24 V

PVDD

AVDD/DVDD

OUT_A

LRCLK

SCLK

MCLK

SDIN

Digital

Audio

Source

BST_A

BST_B

OUT_B

I²C

Control

SDA

SCL

LC_PBTL

OUT_C

RESET

PDN

Control

Inputs

BST_C

BST_D

PLL_FLTP

PLL_FLTM

Loop

Filter

OUT_D

图 71. Mono Parallel Bridge Tied Load Application

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10.2.2.1 Design Requirements

表 26. Design Requirements

PARAMETER

EXAMPLE

Low Power Supply

High Power Supply

3.3 V

8 V to 24 V

I²S Compliant Master

I²C Compliant Master

GPIO Control

Host Processor

Output Filters

Speaker

Inductor-Capacitor Low Pass Filter

4 Ω minimum

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure for information.

10.2.2.3 Application Curves

SPACE

表 27. Relevant Performance Curves

CURVE TITLE

FIGURE

Output Power vs Supply Voltage (PBTL Mode)

图 32

With 2Ω Load on Typical 2 Layer PCB, Device May Be Thermally Limited Above 20 V

Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)

Total Harmonic Distortion vs Frequency (PBTL Mode)

Efficiency vs Output Power (PBTL Mode)

图 33

图 34

图 35

图 36

图 37

图 38

图 39

图 40

图 41

图 42

Efficiency vs Output Power (PBTL Mode)

Power vs Supply Voltage (PBTL Mode)

Idle Channel Noise vs Supply Voltage (PBTL Mode)

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10.2.3 2.1 Application

A 2.1 system generally refers to a system in which there are two full range speakers with a separate amplifier

path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to

the amplifier via the digital input signal, these are driven into two single-ended speakers and are mixed into a

third channel, conditioned to stream low-frequency content into a differentially connected speaker.

The 2.1 application is shown in 图 72.

3.3 V

8 V–24 V

PVDD

AVDD/DVDD

LC_SE

OUT_A

LRCLK

SCLK

MCLK

SDIN

PVDD

Digital

Audio

Source

BST_A

BST_B

OUT_B

LC_SE

I²C

Control

SDA

SCL

PVDD

RESET

PDN

Control

Inputs

OUT_C

PLL_FLTP

PLL_FLTM

Loop

Filter

BST_C

BST_D

LC_BTL

OUT_D

图 72. Simplified 2.1 Application Diagram

10.2.3.1 Design Requirements

表 28. Design Requirements

PARAMETER

Low Power Supply

EXAMPLE

3.3 V

High Power Supply

8 V to 24 V

I²S Compliant Master

I²C Compliant Master

GPIO Control

Host Processor

Output Filters

Speaker

Inductor-Capacitor Low Pass Filter

4 Ω (BTL), 2 Ω (SE) minimum

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10.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure for information.

10.2.3.3 Application Curves

表 29. Relevant Performance Curves

CURVE TITLE

FIGURE

Output Power vs Supply Voltage (2.1 SE Mode)

图 5

With 2 × 4Ω + 4Ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V

Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode)

Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode)

Efficiency vs Total Output Power (2.1 SE Mode)

图 6

图 7

图 8

图 9

图 10

图 11

图 12

图 13

图 14

图 15

图 16

图 17

Efficiency vs Total Output Power (2.1 SE Mode)

Crosstalk vs Frequency (2.1 SE Mode)

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11 Power Supply Recommendations

The TAS5755M requires two power supplies; a low voltage 3.3 V nominal for the pins DVDD and AVDD and a

high power supply, 8 V to 24 V for the pin PVDD. There is no requirement for power up sequencing of low and

high power supplies, however is recommended to put the PDN pin to low before removing the low voltage power

supplies in order to protect the outputs.

11.1 DVDD and AVDD Supplies

The AVDD Supply is used to power the analog internal circuit of the device, and needs a well regulated and

filtered 3.3-V supply voltage. The DVDD Supply is used to power the digital circuitry. DVDD needs a well

regulated and filtered 3.3-V supply voltage.

11.2 PVDD Power Supply

The TAS5755M class-D audio amplifier requires adequate power supply decoupling to ensure the output total

harmonic distortion (THD) and noise is as low as possible. A good low equivalent-series-resistance (ESR)

ceramic capacitor, typically 1 µF, placed as close as possible to the device PVDD leads works best. For filtering

lower frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier is

recommended.

12 Layout

12.1 Layout Guidelines

Class-D switching edges are fast and switched currents are high so it is necessary to take care when planning

the layout of the printed circuit board. The following suggestions will help to meet audio, thermal and EMC

requirements.

•

Decoupling capacitors: the high-frequency decoupling capacitors must be placed as close to the supply pins

as possible; on the TAS5755M a 1-µF high-quality ceramic capacitor is used. Large (10 μF or greater) bulk

power supply decoupling capacitors must be placed near the TAS5755M on the PVDD supplies.

•

Keep the current loop from each of the outputs through the output inductor and the small filter cap and back

to GND as small and tight as possible. The size of this current loop determines its effectiveness as an

antenna.

•

Grounding: A big common GND plane is recommended. The PVDD decoupling capacitors must connect to

GND. The TAS5755M PowerPAD must be connected to GND.

Output filter: remember to select inductors that can handle the high short circuit current of the device. The LC

filter must be placed close to the outputs.

The EVM product folder (TAS5755EVM) and User’s Guide (SLOU481A) available on www.ti.com show

schematic, bill of material, gerber files, and more detailed layout plots.

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12.2 Layout Examples

图 73. Top Layer Layout with Stereo BTL Mode

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Layout Examples (接下页)

图 74. Bottom Layer Layout with Stereo BTL Mode

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13 器件和文档支持

13.1 器件支持

13.1.1 开发支持

TAS570X GDE 软件设置开发工具文档 (SLOC124)

13.2 文档支持

EVM 产品文件夹 (TAS5755MEVM)

13.2.1 相关文档

《TAS5755MEVM 用户指南》(SLOU481A)

13.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

13.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

13.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

71

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5755MDFDR

HTSSOP

DFD

56

2000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DFD 56

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TAS5755MDFDR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DFD HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TAS5755MDFD

56

35

530

11.89

3600

4.9

Pack Materials-Page 3

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS5755M
厂家：	TEXAS INSTRUMENTS
描述：	具有 2.1 声道模式的 50W 立体声、100W 单声道、8V 至 26.4V、数字输入开环 D 类音频放大器放大器音频放大器
文件：	总79页 (文件大小：2532K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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