TAS5756MDCA [TI]
30W 立体声、40W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器 | DCA | 48 | -25 to 85;型号: | TAS5756MDCA |
厂家: | TEXAS INSTRUMENTS |
描述: | 30W 立体声、40W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器 | DCA | 48 | -25 to 85 放大器 音频放大器 |
文件: | 总106页 (文件大小:4268K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TAS5756M
SLAS988B –JUNE 2014–REVISED AUGUST 2015
Burr-Brown Audio
TAS5756M Digital Input, Closed-Loop Class-D Amplifier With Processing
1 Features
3 Description
The TAS5756M device is a high-performance, stereo
closed-loop amplifier with integrated audio processor
with architecture. To convert from digital to analog,
the device uses a high performance DAC with Burr-
Brown® mixed signal heritage. It requires only two
power supplies; one DVDD for low-voltage circuitry
and one PVDD for high-voltage circuitry. It is
controlled by a software control port using standard
I2C communication. In the family, the TAS5756M
uses traditional BD modulation, ensuring low
distortion characteristics. The TAS5754M uses 1SPW
modulation to reduce output ripple current, the
expense of slightly higher distortion.
1
•
Flexible Audio I/O Configuration
–
–
–
Supports I2S, TDM, LJ, RJ Digital Input
8 kHz to 192 kHz Sample Rate Support
Stereo Bridge Tied Load (BTL) or Mono
Parallel Bridge Tied Load (PBTL) Operation
–
–
BD Amplifier Modulation
Supports 3-Wire Digital Audio Interface (No
MCLK required)
•
•
High-Performance Closed-Loop Architecture
(PVDD = 12V, RSPK = 8 Ω, SPK_GAIN = 20 dBV)
–
–
–
Idle Channel Noise = 56 µVrms (A-Wtd)
THD+N = 0.006 % (at 1 W, 1 kHz)
The unique HybridFlow architecture allows the
system designer to choose from several configurable
DSP programs that are specifically designed for use
in popular audio end equipment such as bluetooth
(BT) speakers, sound bars, docking stations, and
subwoofers. This architecture combines the flexibility
of a fully programmable device with the fast download
time and ease of use of a fixed-function ROM device.
SNR = 104 A-Wtd (Ref. to THD+N = 1%)
PurePath™ HybridFlow Processing Architecture
–
Several Configurable MiniDSP Programs
(called HybridFlows)
–
–
Download Time <100 ms (typ)
Advanced Audio Processing Algorithms (2)
An optimal mix of thermal performance and device
cost is provided in the 90 mΩ rDS(on) of the output
MOSFETs. Additionally, a thermally enhanced 48-Pin
HTSSOP provides excellent operation in the elevated
ambient temperatures found in modern consumer
electronic devices.
•
•
Communication Features
–
–
Software Mode Control via I2C Port
Two Address Select Pins – Up to 4 Devices
Robustness and Reliability Features
–
–
Clock Error, DC, and Short-Circuit Protection
Over Temperature and Overcurrent Protection
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TAS5756M
HTSSOP (48)
12.50 mm × 6.10 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
•
•
•
LCD, LED TV, and Multi-Purpose Monitors
Sound Bars, Docking Stations, PC Audio
(2) Please refer to SLAU577 for information regarding Audio
Processing options available via the HybridFlow library.
Wireless Subwoofers, Bluetooth and Active
Speakers
(3) Tested on TAS5756MDCAEVM.
Power at 10% THD+N vs PVDD(3)
Simplified Block Diagram
DVDD
PVDD
50
Inst Power, Rspk = 8Ω
Cont Power, Rspk = 8Ω
Inst Power, Rspk = 6Ω
Cont Power, Rspk = 6Ω
Inst Power, Rspk = 4Ω
Cont Power, Rspk = 4Ω
45
40
35
30
25
20
15
10
5
High Voltage
Supply Domain
Low-Voltage Supply Domain
HybridFlow
Processing
High Performance
Stereo DAC
001100
1101
Closed Loop Stereo
Class D Amplifier
Serial
Audio In
Analog
Audio Out
PWM
Modulator
Power
Stage
Serial
Audio Out
miniDSP Core
Hardware
Control Port
Software Control Port
I²C Communication
0
GPIO/Status
4
6
8
10
12
14
16
18
20
22
24
PVDD (V)
C036
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5756M
SLAS988B –JUNE 2014–REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
6.1 Internal Pin Configurations........................................ 5
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information.................................................. 9
7.5 Electrical Characteristics........................................... 9
7.6 MCLK Timing ......................................................... 14
7.7 Serial Audio Port Timing – Slave Mode.................. 14
7.8 Serial Audio Port Timing – Master Mode................ 15
7.9 I2C Bus Timing – Standard ..................................... 15
7.10 I2C Bus Timing – Fast........................................... 15
7.11 SPK_MUTE Timing .............................................. 16
7.12 Power Dissipation ................................................. 18
7.13 Typical Characteristics.......................................... 24
8
Detailed Description ............................................ 32
8.1 Overview ................................................................. 32
8.2 Functional Block Diagram ....................................... 33
8.3 Feature Description................................................. 33
8.4 Device Functional Modes........................................ 57
Application and Implementation ........................ 60
9.1 Application Information............................................ 60
9.2 Typical Applications ............................................... 62
9
7
10 Power Supply Recommendations ..................... 82
10.1 Power Supplies ..................................................... 82
11 Layout................................................................... 84
11.1 Layout Guidelines ................................................. 84
11.2 Layout Example .................................................... 86
12 Device and Documentation Support ................. 96
12.1 Device Support...................................................... 96
12.2 Community Resources.......................................... 96
12.3 Trademarks........................................................... 97
12.4 Electrostatic Discharge Caution............................ 97
12.5 Glossary................................................................ 97
13 Mechanical, Packaging, and Orderable
Information ........................................................... 97
4 Revision History
Changes from Revision A (January 2015) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
Added TAS880021DCA device to Device Comparison Table................................................................................................ 3
Clarified OCECLRTIME specification in Electrical Characteristics table ................................................................................... 11
Clarified OTECLRTIME specification in Electrical Characteristics table ................................................................................... 11
Corrected several typographical errors in Electrical Characteristics table ........................................................................... 12
Removed reference to Frequency Response graphs in Table 25........................................................................................ 24
Clarified clock generation explanation in Device Clocking section....................................................................................... 33
Clarified description of the modulation scheme used in the Class D amplifier in Modulation Scheme section ................... 49
Added clarity to Adjustable Amplifier Gain and Switching Frequency Selection section ..................................................... 51
Added example resistor values for SPK_GAIN/FREQ pin configuration to Table 15 ......................................................... 52
Clarified the description of overtemperature error from latching to self-clearing in Device Overtemperature Protection
section .................................................................................................................................................................................. 52
•
Corrected description of the overcurrent protection error from latching to self-clearing in SPK_OUTxx Overcurrent
Protection section ................................................................................................................................................................. 53
•
•
•
•
•
Added clarity to I2C Communication Port section................................................................................................................. 55
Added Programming the TAS5756M section ....................................................................................................................... 61
Updated Table 22 ................................................................................................................................................................ 64
Updated Table 25 ................................................................................................................................................................ 69
Updated Table 27 ................................................................................................................................................................ 73
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Changes from Original (June 2014) to Revision A
Page
•
•
•
•
Corrected typographical error in Device Information table .................................................................................................... 1
Updated Functional Block Diagram...................................................................................................................................... 33
Updated Table 15 ................................................................................................................................................................ 52
Added component specification note in Application and Implementation section................................................................ 60
5 Device Comparison Table
DEVICE NAME
MODULATION STYLE
PROCESSING TYPE
50MIPs, HybridFlow (Uses mixture of RAM and ROM components to
create several process flows)
TAS5754MDCA
1SPW (Ternary)
50MIPs, HybridFlow (Uses mixture of RAM and ROM components to
create several process flows)
TAS5756MDCA
TAS880021DCA
BD Modulation
1SPW (Ternary)
100MIPs, Fixed-Function (Uses single ROM image of process flow)
6 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
BSTRPAœ
SPK_OUTAœ
PGND
SPK_OUTA+
BSTRPA+
PVDD
1
2
3
4
5
6
7
8
48
BSTRPBœ
SPK_OUTBœ
PGND
SPK_OUTB+
BSTRPB+
PVDD
PVDD
PVDD
SPK_FAULT
PGND
SPK_INBœ
SPK_INB+
DAC_OUTB
CPVSS
CN
GND
CP
CPVDD
DVDD
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
PVDD
GVDD_REG
SPK_GAIN/FREQ
AGND
9
10
11
12
13
14
15
16
17
18
19
SPK_INAœ
SPK_INA+
DAC_OUTA
AVDD
AGND
SDA
SCL
GPIO0
Thermal Pad
GPIO1
ADR1
GPIO2
MCLK
SCLK
DGND
20
21
22
23
24
29
28
27
26
25
DVDD_REG
SPK_MUTE
ADR0
SDIN
LRCK/FS
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Pin Functions
PIN
INTERNAL
TERMINATION
TYPE(1)
DESCRIPTION
NAME
ADR0
ADR1
NO.
26
20
10
15
14
Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
DI
DI
Figure 11
Sets the second LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD
AGND
G
—
Ground reference for analog circuitry(2)
AVDD
P
P
Figure 2
Power supply for internal analog circuitry
Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for
the high-side gate drive for SPK_OUTA–
BSTRPA–
1
5
Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for
the high-side gate drive for SPK_OUTA
BSTRPA+
BSTRPB–
BSTRPB+
P
P
P
Figure 3
Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for
the high-side gate drive for SPK_OUTB–
48
44
Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for
the high-side gate drive for SPK_OUTB+
CN
34
32
31
35
13
36
29
30
P
P
Figure 15
Figure 14
Figure 2
Negative pin for capacitor connection used in the line--driver charge pump
Positive pin for capacitor connection used in the line-driver charge pump
Power supply for charge pump circuitry
CP
CPVDD
CPVSS
DAC_OUTA
DAC_OUTB
DGND
P
P
Figure 15
–3.3-V supply generated by charge pump for the DAC
Single-ended output for Channel A of the DAC
AO
AO
G
Figure 8
Single-ended output for Channel B of the DAC
—
Ground reference for digital circuitry. Connect this pin to the system ground.
Power supply for the internal digital circuitry
DVDD
P
Figure 2
Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided
as a connection point for filtering capacitors for this supply and must not be used to power any
external circuitry.
DVDD_REG
28
P
Figure 16
—
GND
33
18
19
21
G
Ground pin for device. This pin should be connected to the system ground.
GPIO0
GPIO1
GPIO2
General purpose input/output pins (GPIOx) which can be incorporated in a HybridFlow for a given
purpose. Refer to documentation of target HybridFlow to determine if any of these pins are required
by the HybridFlow and, if so, how they are to be used. In most HybridFlows, presentation of a serial
audio signal, called SDOUT, is done through GPIO2.
DI/O
P
Figure 11
Figure 5
Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of
output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and
must not be used to power any external circuitry.
GVDD_REG
8
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ, and
RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds
to the frame sync boundary.
LRCK/FS
MCLK
25
DI/O
DI
Figure 12
22
3
Master clock used for internal clock tree and sub-circuit and state machine clocking
PGND
39
46
6
G
—
Ground reference for power device circuitry. Connect this pin to the system ground.
7
PVDD
41
42
43
17
23
16
24
11
12
38
37
P
Figure 1
Power supply for internal power circuitry
I2C serial control port clock
SCL
DI
DI/O
DI/O
D1
AI
Figure 10
Figure 12
Figure 9
SCLK
Bit clock for the digital signal that is active on the input data line of the serial data port
I2C serial control port data
SDA
SDIN
Figure 12
Data line to the serial data port
SPK_INA–
SPK_INA+
SPK_INB–
SPK_INB+
Negative pin for differential speaker amplifier input A
Positive pin for differential speaker amplifier input A
Negative pin for differential speaker amplifier input B
Positive pin for differential speaker amplifier input B
AI
Figure 7
AI
AI
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
(2) This pin should be connected to the system ground.
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Pin Functions (continued)
PIN
INTERNAL
TERMINATION
TYPE(1)
DESCRIPTION
NAME
NO.
Fault pin which is pulled low when an overcurrent, overtemperature, overvoltage, undervoltage, or DC
detect event occurs
SPK_FAULT
40
DO
AI
Figure 17
Figure 6
SPK_GAIN/F
REQ
9
Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device.
SPK_OUTA–
SPK_OUTA+
SPK_OUTB–
SPK_OUTB+
2
4
AO
AO
AO
AO
Negative pin for differential speaker amplifier output A
Positive pin for differential speaker amplifier output A
Negative pin for differential speaker amplifier output B
Positive pin for differential speaker amplifier output B
Figure 4
47
45
Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and
pulled high (connected to DVDD) to unmute the device.
SPK_MUTE
Themal pad
27
I
Figure 13
—
Provides both electrical and thermal connection from the device to the board. A matching ground pad
must be provided on the PCB and the device connected to it through solder. For proper electrical
operation, this ground pad must be connected to the system ground.
G
6.1 Internal Pin Configurations
PVDD
DVDD
30 V ESD
3.3 V ESD
Figure 1. PVDD Pins
Figure 2. AVDD, DVDD and CPVDD Pins
GVDD
PVDD
BSTRPxx
PVDD
7 V ESD
SPK_OUTxx
SPK_OUTxx
Figure 3. BSTRPxx Pins
Figure 4. SPK_OUTxx Pins
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Internal Pin Configurations (continued)
GVDD
PVDD
10 Ω
GVDD
10 kΩ
SPK_GAIN/FREQ
7 V ESD
7 V ESD
Figure 5. GVDD_REG Pin
Figure 6. SPK_GAIN/FREQ Pin
AVDD
SPK_INxx
7 V ESD
Gain Switch
CPVSS
DAC_OUTA
Figure 7. SPK_INxx Pins
Figure 8. DAC_OUTx Pins
DVDD
SDA
DVDD
SCL
3.3 V
ESD
3.3 V
ESD
Figure 9. SDA Pin
Figure 10. SCL Pin
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Internal Pin Configurations (continued)
DVDD
DVDD
GPIO1
GPIO2
GPIO3
ADR0
ADR1
MCLK
SCLK
3.3 V
ESD
SDIN
3.3 V
ESD
LRCK/FS
Figure 11. GPIO and ADR Pins
Figure 12. SCLK, BCLK, SDIN, and LRCK/FS Pins
CVPDD
DVDD
CP
3.3 V
ESD
SPK_MUTE
3.3 V
ESD
Figure 13. SPK_MUTE Pin
Figure 14. CP Pin
DVDD
GND
CN
3.3 V
ESD
DVDD_REG
1.8 V
ESD
CPVSS
3.3 V
ESD
Figure 15. CN and CPVSS Pins
Figure 16. DVDD_REG Pin
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Internal Pin Configurations (continued)
100 Ω
SPK_FAULT
28 V
ESD
Figure 17. SPK_FAULT Pin
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
3.9
UNIT
Low-voltage digital, analog, charge pump
DVDD, AVDD, CPVDD
supply
V
V
V
PVDD supply
PVDD
30
Input voltage for SPK_GAIN/FREQ and
SPK_FAULT pins
VI(AmpCtrl)
VGVDD + 0.3
DVDD referenced digital inputs(2)
Analog input into speaker amplifier
Voltage at speaker output pins
Ambient operating temperature, TA
Storage temperature, Tstg
VI(DigIn)
–0.5
–0.3
–0.3
–25
–40
VDVDD + 0.5
V
V
VI(SPK_INxx)
VI(SPK_OUTxx)
6.3
32
V
85
°C
°C
125
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and
SPK_MUTE.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3.63
26.4
UNIT
DVDD, AVDD, CPVDD
2.9
V(POWER)
Power supply inputs
V
PVDD
4.5
BTL Mode
PBTL Mode
3
2
Ω
Ω
V
V
RSPK
Minimum speaker load
VIH(DigIn)
VIL(DigIn)
Input logic high for DVDD referenced digital inputs(1)(2)
Input logic low for DVDD referenced digital inputs(1)(3)
0.9 × VDVDD
VDVDD
VDVDD
0
0.1 × VDVDD
Minimum inductor value in LC filter under short-circuit
condition
LOUT
1
4.7
µH
(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and
SPK_MUTE.
(2) The best practice for driving the input pins of the TAS5756M device is to power the drive circuit or pullup resistor from the same supply
which provides the DVDD power supply.
(3) The best practice for driving the input pins of the TAS5756M device low is to pull them down, either actively or through pulldown
resistors to the system ground.
7.4 Thermal Information
TAS5756M
DCA (HTSSOP)
48 PINS
THERMAL METRIC(1)(2)
UNIT
JEDEC
STANDARD
2-LAYER PCB
JEDEC
STANDARD
4-LAYER PCB
TAS5756MDCAEVM
4-LAYER PCB
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
41.8
14.4
9.4
0.6
8.1
1
27.6
14.4
9.4
0.6
9.3
1
19.4
14.4
9.4
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
4.8
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) For the PCB layout, see the Using the TAS5754/6M HybridFlow Processor user's guide, SLAU577.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
DIGITAL I/O
Input logic high current
level for DVDD
|IIH|1
VIN(DigIn) = VDVDD
µA
referenced digital input
pins(1)
Input logic low current
level for DVDD
|IIL|1
VIH1
VIN(DigIn) = 0 V
–10
µA
referenced digital input
pins(1)
Input logic high threshold
for DVDD referenced
digital inputs(1)
70%
80%
VDVDD
Input logic low threshold
for DVDD referenced
digital inputs(1)
VIL1
30%
VDVDD
Output logic high voltage
level(1)
VOH(DigOut)
IOH = 4 mA
VDVDD
(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and
SPK_MUTE.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output logic low voltage
level(1)
VOL(DigOut)
IOH = –4 mA
22%
VDVDD
Output logic low voltage
level for SPK_FAULT
VOL(SPK_FAULT)
With 100-kΩ pullup resistor
0.8
V
I2C CONTROL PORT
Allowable load
CL(I2C)
capacitance for each I2C
Line
400
pF
fSCL(fast)
fSCL(slow)
Support SCL frequency
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
Noise margin at High
level for each connected
device (including
hysteresis)
VNH
0.2 × VDD
V
MCLK AND PLL SPECIFICATIONS
Allowable MCLK duty
cycle
DMCLK
40%
128
6.7
1
60%
512
20
Supported MCLK
frequencies
(2)
fMCLK
Up to 50 MHz
fS
Clock divider uses fractional divide
D > 0, P = 1
fPLL
PLL input frequency
MHz
Clock divider uses integer divide
D = 0, P = 1
20
(2) A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the
TAS5756M device.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SERIAL AUDIO PORT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Required LRCK/FS to
SCLK rising edge delay
tDLY
DSCLK
fS
5
40%
8
ns
Allowable SCLK duty
cycle
60%
192
Supported input sample
rates
kHz
Supported SCLK
frequencies
(2)
fSCLK
fSCLK
32
64
fS
SCLK frequency
Either master mode or slave mode
24.576
MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
SPK_GAIN/FREQ voltage < 3 V,
see Adjustable Amplifier Gain and Switching
20
dBV
Frequency Selection
AV(SPK_AMP)
Speaker amplifier gain
SPK_GAIN/FREQ voltage > 3.3 V,
see Adjustable Amplifier Gain and Switching
Frequency Selection
26
±1
dBV
dBV
Typical variation of
speaker amplifier gain
ΔAV(SPK_AMP)
Switching frequency depends on voltage
presented at SPK_GAIN/FREQ pin and the
clocking arrangement, including the incoming
sample rate, see Adjustable Amplifier Gain
and Switching Frequency Selection
Switching frequency of
the speaker amplifier
fSPK_AMP
176.4
768
kHz
Injected Noise = 50 Hz to 60 Hz, 200 mVP-P
Gain = 26 dBV, input audio signal = digital
zero
,
Power supply rejection
ratio
KSVR
60
90
dB
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C,
includes PVDD/PGND pins, leadframe,
bondwires and metallization layers.
Drain-to-source on
resistance of the
individual output
MOSFETs
mΩ
rDS(on)
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C
90
mΩ
SPK_OUTxx Overcurrent
Error Threshold
OCETHRES
OTETHRES
7.5
A
Overtemperature Error
Threshold
150
1.3
°C
s
Time required to clear
Overcurrent Error after
error condition is
removed.
OCECLRTIME
Time required to clear
Overtemperature Error
after error condition is
removed.
OTECLRTIME
1.3
s
PVDD Overvoltage Error
Threshold
OVETHRES(PVDD)
27
V
V
PVDD Undervoltage Error
Threshold
UVETHRES(PVDD)
4.5
SPEAKER AMPLIFIER (STEREO BTL)
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 20 dBV
gain, VPVDD = 12 V
2
6
10
15
|VOS
|
Amplifier offset voltage
mV
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 26 dBV
gain, VPVDD = 24 V
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
56
VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
58
86
ICN(SPK)
PO(SPK)
SNR
Idle channel noise
µVRMS
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
88
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
15
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
20
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
28
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, THD+N = 0.1%
20
Output Power (Per
Channel)
W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
18
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
18
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
12
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
Signal-to-noise ratio
(referenced to 0 dBFS
input signal)
dB
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
106
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
105
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, PO = 1 W
0.011%
0.007%
0.02%
0.015%
0.01%
0.017%
0.015%
0.017%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
Total harmonic distortion
and noise
THD+NSPK
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
–88
1-kHz Sine, across f(S)
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
–97
–88
–88
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
X-talkSPK
dB
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, Input Signal 250 mVrms,
1-kHz Sine, across f(S)
SPEAKER AMPLIFIER (MONO PBTL)
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 20 dBV
gain, VPVDD = 12 V
0.5
1
8
|VOS
|
Amplifier offset voltage
mV
Measured differentially with zero input data,
SPK_GAIN/FREQ pin configured for 26 dBV
gain, VPVDD = 24 V
14
VPVDD = 15 V, SPK_GAIN = 20 dBV, RSPK =
8 Ω, A-Weighted
58
57
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted
ICN
Idle channel noise
µVRMS
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK =
8 Ω, A-Weighted
85
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted
85
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
40
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
56
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
34
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
40
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, THD+N = 0.1%
8
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
36
Output Power (Per
Channel)
PO
W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
21.3
36
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
24
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, THD+N = 0.1%
13.5
30
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2
Ω, THD+N = 0.1%, Unless otherwise noted
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, THD+N = 0.1%, Unless otherwise noted
15
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
104
107
Signal-to-noise ratio
(referenced to 0 dBFS
input signal)
SNR
dB
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, A-Weighted, –120 dBFS Input
105
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 4
Ω, PO = 1 W
0.013%
0.007%
0.02%
0.028%
0.018%
0.017%
0.027%
0.016%
0.03%
0.01%
0.03%
0.012%
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
VPVDD = 24 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
Total harmonic distortion
and noise
THD+N
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 4
Ω, PO = 1 W
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 2
Ω, PO = 1 W
VPVDD = 15 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
VPVDD = 12 V, SPK_GAIN = 20 dBV, RSPK = 2
Ω, PO = 1 W
VPVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8
Ω, PO = 1 W
7.6 MCLK Timing
See Figure 18.
MIN
NOM
MAX
UNIT
ns
tMCLK
MCLK period
20
9
1000
tMCLKH
tMCLKL
MCLK pulse width, high
MCLK pulse width, low
ns
9
ns
7.7 Serial Audio Port Timing – Slave Mode
See Figure 19.
MIN
NOM
MAX
UNIT
MHz
ns
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
SCLK period
SCLK pulse width, low
ns
SCLK pulse width, high
ns
SCLK rising to LRCK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
ns
tLS
8
ns
tSU
8
ns
tDH
8
ns
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Serial Audio Port Timing – Slave Mode (continued)
See Figure 19.
MIN
NOM
MAX
UNIT
tDFS
Data delay time from SCLK falling edge
15
ns
7.8 Serial Audio Port Timing – Master Mode
See Figure 20.
MIN NOM
MAX
UNIT
ns
tSCLK
tSCLKL
tSCLKH
tLRD
SCLK period
40
16
16
–10
8
SCLK pulse width, low
ns
SCLK pulse width, high
ns
LRCK/FS delay time from to SCLK falling edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
20
15
ns
tSU
ns
tDH
8
ns
tDFS
ns
7.9 I2C Bus Timing – Standard
MIN
MAX
UNIT
kHz
µs
fSCL
SCL clock frequency
100
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
4.7
µs
tHI
High period of the SCL clock
4
4.7
µs
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
tSCL-R1
tSCL-F
tSDA-R
tSDA-F
tP-SU
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
µs
4
µs
250
ns
Data hold time
0
900
1000
1000
1000
1000
1000
ns
Rise time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
ns
Rise time of SCL signal after a repeated START condition and after an acknowledge bit
Fall time of SCL signal
ns
ns
Rise time of SDA signal
ns
Fall time of SDA signal
ns
Setup time for STOP condition
µs
7.10 I2C Bus Timing – Fast
See Figure 21.
MIN
MAX
UNIT
kHz
µs
fSCL
SCL clock frequency
400
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
1.3
1.3
tLOW
µs
tHI
High period of the SCL clock
600
ns
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
tSCL-R1
tSCL-F
tSDA-R
tSDA-F
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
600
ns
600
ns
100
ns
Data hold time
0
900
300
300
300
300
300
ns
Rise time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
ns
Rise time of SCL signal after a repeated START condition and after an acknowledge bit
Fall time of SCL signal
ns
ns
Rise time of SDA signal
ns
Fall time of SDA signal
ns
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I2C Bus Timing – Fast (continued)
See Figure 21.
MIN
MAX
UNIT
ns
tP-SU
tSP
Setup time for STOP condition
Pulse width of spike suppressed
600
50
ns
7.11 SPK_MUTE Timing
See Figure 22.
MIN
MAX
20
UNIT
ns
tr
tf
Rise time
Fall time
20
ns
t
MCLKH
"H"
0.7 × V
DVDD
0.3 × V
DVDD
"L"
t
t
MCLKL
MCLK
Figure 18. Timing Requirements for MCLK Input
LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
DH
SU
t
DFS
DATA
(Output)
Figure 19. MCLK Timing Diagram in Slave Mode
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SLAS988B –JUNE 2014–REVISED AUGUST 2015
t
BCL
t
SCLK.
SCLK
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
LRD
SCLK
LRCK/FS
(Input)
t
DFS
DATA
(Input)
0.5 × DVDD
t
t
DH
SU
DATA
(Output)
0.5 × DVDD
Figure 20. MCLK Timing Diagram in Master Mode
Repeated
START
START
STOP
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
Figure 21. I2C Communication Port Timing Diagram
0.9 × DV
0.1 × DV
DD
DD
SPK_MUTE
t
r
t
f
< 20 ns
< 20 ns
Figure 22. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin
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7.12 Power Dissipation
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
21.3
0.273
0.273
0.273
0.273
0.273
0.274
0.071
0.072
0.072
0.018
0.018
0.019
0.319
0.319
0.297
0.319
0.319
0.319
0.071
0.071
0.072
0.019
0.019
0.019
Idle
Mute
21.33
21.3
21.33
21.34
21.36
2.08
384
Standby
Powerdown
Idle
2.11
2.17
2.03
2.04
1
2.06
1
7.4
20
27.48
27.49
24.46
27.5
35
35
35
35
35
35
17
17
17
1
Mute
27.51
27.52
2.04
768
Standby
Powerdown
2.08
2.11
2.06
2.07
1
2.08
1
(1) Mute: P0-R3-B0,B5 = 1
(2) Standby: P0-R2-B5 = 1
(3) P0-R2-B0 = 1
(4) IPVDD refers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current
draw were removed.
(5) IDVDD refers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the
DUT current draw were removed.
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Power Dissipation (continued)
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
24.33
24.32
24.36
24.36
24.32
24.37
3.58
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
0.386
0.385
0.386
0.386
0.385
0.386
0.096
0.096
0.096
0.042
0.042
0.043
0.456
0.456
0.456
0.150
0.456
0.456
0.095
0.095
0.096
0.042
0.042
0.043
Idle
Mute
384
Standby
Powerdown
Idle
3.57
3.58
3.52
3.52
1
3.54
1
11.1
20
30.7
35
35
35
35
35
35
17
17
17
1
30.65
30.67
3.072
30.69
30.69
3.54
Mute
768
Standby
Powerdown
3.54
3.58
3.53
3.53
1
3.55
1
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Power Dissipation (continued)
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
25.07
25.08
25.1
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
0.416
0.416
0.417
0.417
0.416
0.417
0.103
0.103
0.103
0.050
0.050
0.050
0.491
0.491
0.491
0.491
0.491
0.491
0.103
0.103
0.103
0.050
0.050
0.050
Idle
Mute
25.12
25.08
25.11
3.92
384
Standby
Powerdown
Idle
3.93
3.94
3.87
3.85
1
3.87
1
12
20
31.31
31.29
31.31
31.31
31.33
31.32
3.88
35
35
35
35
35
35
17
17
17
1
Mute
768
Standby
Powerdown
3.9
3.91
3.89
3.91
1
3.88
1
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SLAS988B –JUNE 2014–REVISED AUGUST 2015
Power Dissipation (continued)
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
27.94
27.91
27.75
27.98
27.94
27.88
5.09
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
0.535
0.534
0.532
0.535
0.535
0.534
0.132
0.133
0.134
0.079
0.079
0.080
0.611
0.611
0.612
0.611
0.611
0.611
0.132
0.132
0.133
0.079
0.079
0.080
Idle
Mute
384
Standby
Powerdown
Idle
5.12
5.19
5.02
5.06
1
5.14
1
15
26
33.05
33.03
33.08
33.03
33.04
33.05
5.07
35
35
35
35
35
35
17
17
17
1
Mute
768
Standby
Powerdown
5.09
5.14
5.02
5.04
1
5.09
1
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Power Dissipation (continued)
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
32.27
32.19
32.08
32.27
32.24
32.22
6.95
6.93
7
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
0.748
0.746
0.744
0.748
0.747
0.747
0.192
0.192
0.193
0.138
0.139
0.140
0.801
0.801
0.801
0.801
0.801
0.801
0.192
0.192
0.193
0.137
0.138
0.139
Idle
Mute
384
Standby
Powerdown
Idle
6.89
6.9
1
6.96
34.99
34.95
34.97
34.96
34.98
34.96
6.93
6.93
6.98
6.84
6.89
6.9
1
19.6
26
35
35
35
35
35
35
17
17
17
1
Mute
768
Standby
Powerdown
1
1
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Power Dissipation (continued)
(4)
(5)
VPVDD
(V)
SPK_GAIN(1)(2)(3)
(dBV)
fSPK_AMP
(kHz)
STATE OF
OPERATION
RSPK
(Ω)
IPVDD
IDVDD
PDISS
(W)
(mA)
36.93
36.87
36.77
36.94
36.89
36.85
8.73
(mA)
35
35
35
35
35
35
17
17
17
1
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
1.002
1.000
0.998
1.002
1.001
1.000
0.266
0.265
0.265
0.211
0.211
0.212
1.000
1.000
0.999
1.000
1.000
0.999
0.264
0.264
0.265
0.210
0.211
0.211
Idle
Mute
384
Standby
Powerdown
Idle
8.72
8.71
8.64
8.66
1
8.69
1
24
26
36.84
36.86
36.83
36.85
36.84
36.82
8.66
35
35
35
35
35
35
17
17
17
1
Mute
768
Standby
Powerdown
8.68
8.71
8.63
8.64
1
8.65
1
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7.13 Typical Characteristics
All performance plots were taken using the TAS5754M-56MEVM at room temperature, unless otherwise noted.
The term Traditional LC filter refers to the output filter that is present by default on the EVM. For Filterless
measurements, the on-board LC filter was removed and an Audio Precision AUX-025 measurement filter was
used to take the measurements.
Table 1. Quick Reference Table
OUTPUT
CONFIGURATIONS
PLOT TITLE
FIGURE NUMBER
Output Power vs PVDD
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 57
Figure 58
Figure 53
Figure 54
Figure 55
Figure 56
Figure 59
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
Bridge Tied Load (BTL)
Configuration Curves
Efficiency vs Output Power
Idle Current Draw (Filterless) vs PVDD
Idle Current Draw (Traditional LC Filter) vs PVDD
Crosstalk vs. Frequency
PVDD PSRR vs Frequency
DVDD PSRR vs Frequency
AVDD PSRR vs Frequency
CPVDD PSRR vs Frequency
Powerdown Current Draw vs PVDD
Output Power vs PVDD
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
Parallel Bridge Tied
Load (PBTL)
Configuration
Efficiency vs Output Power
Idle Current Draw (filterless) vs PVDD
Idle Current Draw (traditional LC filter) vs PVDD
PVDD PSRR vs Frequency
DVDD PSRR vs Frequency
AVDD PSRR vs Frequency
CPVDD PSRR vs Frequency
Powerdown Current Draw vs PVDD
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7.13.1 Bridge Tied Load (BTL) Configuration Curves
Return to Quick Reference Table.
50
1
0.1
Inst Power, Rspk = 8Ω
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
Cont Power, Rspk = 8Ω
Inst Power, Rspk = 6Ω
Cont Power, Rspk = 6Ω
Inst Power, Rspk = 4Ω
Cont Power, Rspk = 4Ω
45
40
35
30
25
20
15
10
5
0.01
0.001
0
4
6
8
10
12
14
16
18
20
22
24
20
200
2k
20k
PVDD (V)
Frequency (Hz)
C036
C034
AV(SPK_AMP) = 26 dBV
Figure 23. Output Power vs PVDD – BTL
AV(SPK_AMP) = 20 dBV
PO = 1 W
VPVDD = 12 V
Figure 24. THD+N vs Frequency – BTL
1
0.1
1
0.1
Rspk = 4Ω
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
Rspk = 6Ω
Rspk = 8Ω
0.01
0.001
0.01
0.001
20
200
2k
20k
20
200
2k
20k
C002
Frequency (Hz)
Frequency (Hz)
C038
AV(SPK_AMP) = 20 dBV
PO = 1 W
VPVDD = 15 V
AV(SPK_AMP) = 20 dBV
PO = 1 W
VPVDD = 18 V
Figure 25. THD+N vs Frequency – BTL
Figure 26. THD+N vs Frequency – BTL
10
1
1
0.1
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
0.1
0.01
0.001
0.01
0.001
0.01
0.1
1
10
20
200
2k
20k
Power (W)
Frequency (Hz)
C035
C003
AV(SPK_AMP)
= 20 dBV
Input Signal = 1 kHz Sine
VPVDD = 12 V
AV(SPK_AMP)
= 26 dBV
PO = 1 W
VPVDD = 24 V
Figure 28. THD + N vs Power – BTL
Figure 27. THD+N vs Frequency – BTL
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10
10
1
Rspk = 4Ω
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
Rspk = 6Ω
Rspk = 8Ω
1
0.1
0.01
0.1
0.01
0.001
0.001
0.01
0.1
1
10
0.01
0.1
1
10
Power (W)
Power (W)
C004
C039
AV(SPK_AMP)
= 20 dBV
Input Signal = 1 kHz Sine
VPVDD = 15 V
AV(SPK_AMP)
= 26 dBV
Input Signal = 1 kHz Sine
VPVDD =
18 V
Figure 29. THD + N vs Power – BTL
Figure 30. THD + N vs Power – BTL
10
1
150
125
100
75
Rspk = 4Ω
Rspk = 6Ω
Rspk = 8Ω
Gain = 20dBV, fspk_amp = 384kHz
Gain = 26dBV, fspk_amp = 384kHz
Gain = 20dBV, fspk_amp = 768kHz
Gain = 26dBV, fspk_amp = 768kHz
0.1
0.01
50
0.001
0.01
25
4
0.1
1
10
6
8
10
12
14
16
18
20
22
24
Power (W)
PO = 1 W
PVDD (V)
C005
C006
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
AV(SPK_AMP) = 20 dBV
fSPK_AMP = 384 kHz
RSPK = 8 Ω
Figure 31. THD + N vs Power – BTL
Figure 32. Idle Channel Noise vs PVDD – BTL
100
90
80
70
60
50
60
50
40
30
20
10
0
Filterless
PVDD = 12V
PVDD = 15V
PVDD = 18V
PVDD = 24V
0
10
20
30
40
50
60
70
80
90
4
6
8
10
12
14
16
18
20
22
24
Total Output Power (W)
PVDD (V)
C007
C013
RSPK = 8 Ω
fSPK_AMP = 768 kHz
RSPK = 8 Ω
Figure 33. Efficiency vs Output Power – BTL
Figure 34. Idle Current Draw (Filterless) vs VPVDD – BTL
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0
œ10
Ch. B vs Ch. A
Ch. A vs Ch. B
Traditional LC
70
60
50
40
30
20
10
0
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
œ100
œ110
œ120
4
6
8
10
12
14
16
18
20
22
24
20
200
2k
20k
PVDD (V)
Frequency (Hz)
C015
C008
fSPK_AMP = 768 kHz
RSPK = 8 Ω
AV(SPK_AMP) = 26 dBV
Sine Input
VPVDD = 24 V
Figure 35. Idle Current Draw
(Traditional LC Filter) vs PVDD – BTL
Figure 36. Crosstalk vs Frequency – BTL
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
Ch. B kSVR
Ch. A kSVR
Ch. B kSVR
Ch. A kSVR
20
200
2k
20k
20
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C009
C010
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
Supply Noise = 250 mV
Sine Input
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
Supply Noise = 250 mV
RSPK = 8 Ω
Figure 37. PVDD PSRR vs Frequency – BTL
Figure 38. DVDD PSRR vs Frequency – BTL
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
Ch. B kSVR
Ch. A kSVR
Ch. B kSVR
Ch. A kSVR
20
200
2k
20k
20
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C011
C012
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
Supply Noise = 250 mV
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
Supply Noise = 250 mV
Sine Input
RSPK = 8 Ω
Figure 39. AVDD PSRR vs Frequency – BTL
Figure 40. CPVDD PSRR vs Frequency – BTL
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10
9
8
7
6
5
4
3
2
1
0
Idle Current
4
6
8
10
12
14
16
18
20
22
24
PVDD (V)
C014
AV(SPK_AMP) = 26 dBV
fSPK_AMP = 786 kHz
Figure 41. Powerdown Current Draw vs PVDD – BTL
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7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
Return to Quick Reference Table.
1
0.1
120
Inst Power, Rspk = 4Ω
Cont Power, Rspk = 4Ω
Inst Power, Rspk = 3Ω
Cont Power, Rspk = 3Ω
Inst Power, Rspk = 2Ω
Cont Power, Rspk = 2Ω
Rspk = 2Ω
Rspk = 3Ω
Rspk = 4Ω
100
80
60
40
20
0
0.01
0.001
20
200
2k
20k
4
6
8
10
12
14
16
18
20
22
24
PVDD (V)
Frequency (Hz)
C037
C017
AV(SPK_AMP) = 26 dBV
Measured on TAS5754/6 EVM
AV(SPK_AMP) = 20 dBV
PO = 1 W
VPVDD = 12 V
Figure 42. Output Power vs PVDD – PBTL
Figure 43. THD+N vs Frequency – PBTL
1
0.1
1
0.1
Rspk = 2Ω
Rspk = 2Ω
Rspk = 3Ω
Rspk = 4Ω
Rspk = 3Ω
Rspk = 4Ω
0.01
0.001
0.01
0.001
20
200
2k
20k
20
200
2k
20k
Frequency (Hz)
C019
Frequency (Hz)
C018
AV(SPK_AMP) = 26 dBV
PO = 1 W
VPVDD = 18 V
AV(SPK_AMP) = 20 dBV
PO = 1 W
VPVDD = 15 V
Figure 45. THD+N vs Frequency – PBTL
Figure 44. THD+N vs Frequency – PBTL
1
0.1
10
1
Rspk = 2Ω
Rspk = 2Ω
Rspk = 3Ω
Rspk = 4Ω
Rspk = 3Ω
Rspk = 4Ω
0.1
0.01
0.001
0.01
0.001
20
200
2k
20k
0.01
0.1
1
Power (W)
PO = 1 W
10
Frequency (Hz)
C020
C021
AV(SPK_AMP) = 26 dBV
PO = 1 W
VPVDD = 24 V
AV(SPK_AMP) = 20 dBV
VPVDD = 12 V
Figure 46. THD+N vs Frequency – PBTL
Figure 47. THD+N vs Power – PBTL
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10
10
1
Rspk = 2Ω
Rspk = 2Ω
Rspk = 3Ω
Rspk = 4Ω
Rspk = 3Ω
Rspk = 4Ω
1
0.1
0.01
0.1
0.01
0.001
0.001
0.01
0.1
1
Power (W)
PO = 1 W
10
0.01
0.1
1
10
100
Power (W)
C022
C023
AV(SPK_AMP) = 20 dBV
VPVDD = 15 V
AV(SPK_AMP) = 20 dBV
VPVDD = 18 V
PO = 1 W
Input Signal = 1 kHz Sine
Figure 48. THD+N vs Power – PBTL
Figure 49. THD+N vs Power – PBTL
10
1
150
125
100
75
Gain = 20dBV, fspk_amp = 384kHz
Gain = 26dBV, fspk_amp = 384kHz
Gain = 20dBV, fspk_amp = 768kHz
Gain = 26dBV, fspk_amp = 768kHz
Rspk = 2Ω
Rspk = 3Ω
Rspk = 4Ω
0.1
50
0.01
0.001
25
0
0.01
0.1
1
10
100
4
6
8
10
12
14
16
18
20
22
24
Power (W)
PVDD (V)
C024
C025
AV(SPK_AMP) = 20 dBV
VPVDD = 24 V
PO = 1 W
AV(SPK_AMP)
= 26 dBV
ILOAD = xA
VPVDD = 18 V
Input Signal = 1 kHz Sine
Figure 51. Idle Channel Noise vs PVDD – PBTL
Figure 50. THD+N vs Power – PBTL
100
90
80
70
60
50
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
Rspk = 4Ω
PVDD = 12V
PVDD = 15V
PVDD = 18V
PVDD = 24V
0
10
20
30
40
50
60
70
80
90 100
20
200
2k
20k
Total Output Power (W)
Frequency (Hz)
C026
C027
AV(SPK_AMP) = 26
dBV
ILOAD = xA
VPVDD = 24 V
AV(SPK_AMP) = 26dBV
Sine Input
VPVDD = 24V
Figure 53. PVDD PSRR vs Frequency – PBTL
Figure 52. Efficiency vs Output Power – PBTL
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0
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
Rspk = 4Ω
Rspk = 4Ω
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
20
200
2k
20k
20
200
2k
20k
Frequency (Hz)
Frequency (Hz)
C028
C029
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
RSPK = 8 Ω
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
RSPK = 8 Ω
Supply Noise = 250 mV
Supply Noise = 250 mV
Figure 54. DVDD PSRR vs Frequency – PBTL
Figure 55. AVDD PSRR vs Frequency – PBTL
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
60
50
40
30
20
10
0
Rspk = 4Ω
Filterless
20
200
2k
20k
4
6
8
10
12
14
16
18
20
22
24
Frequency (Hz)
PVDD (V)
C030
C031
AV(SPK_AMP) = 26 dBV
VPVDD = 24 V
Sine Input
Supply Noise = 250 mV
Figure 57. Idle Current Draw (Filterless) vs PVDD – PBTL
Figure 56. CPVDD PSRR vs Frequency – PBTL
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
Traditional LC
Shutdown
0
4
6
8
10
12
14
16
18
20
22
24
4
6
8
10
12
14
16
18
20
22
24
PVDD (V)
PVDD (V)
C033
C032
AV(SPK_AMP) = 26 dBV
fSPK_AMP = 786 kHz
Figure 58. Idle Current Draw
(Traditional LC filter) vs PVDD – PBTL
Figure 59. Powerdown Current Draw vs PVDD – PBTL
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8 Detailed Description
8.1 Overview
The TAS5756M device integrates 4 main building blocks together into a single cohesive device that maximizes
sound quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
•
•
A stereo audio DAC, boasting a strong Burr-Brown heritage with a highly flexible serial audio port.
A miniDSP audio processing core with HybridFlow architecture, which provides an increase in flexibility over a
fixed-function ROM device with faster download time than a fully programmable device
•
A flexible closed-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
An I2C control port for communication with the device
•
The device requires only two power supplies for proper operation. A DVDD supply is needed to power the low-
voltage digital and analog circuitry. Another supply, called PVDD, is needed to provide power to the output stage
of the audio amplifier. The operating range for these supplies is shown in the Recommended Operating
Conditions table.
Communication with the device is accomplished through the I2C control port. A speaker amplifier fault line is also
provided to notify a system controller of the occurrence of an overtemperature, overcurrent, overvoltage,
undervoltage, or DC error in the speaker amplifier. There are three digital GPIO pins that are available for use by
the HybridFlows. One popular use of the GPIO lines is to provide a Serial Audio Output from the device
(SDOUT). HybridFlows which provide an SDOUT customarily present that signal on GPIO2, although this
configuration can be changed via the I2C control port. The register space in the control port spans several pages
to accommodate some static controls which maintain their functionality across HybridFlows, as well as controls
that are determined by the HybridFlow used.
The MiniDSP audio processing core, featuring a HybridFlow architecture, allows the selection of a configurable
DSP program called a HybridFlow from a list of available HybridFlows. A hybrid flow combines audio processing
blocks, many of which that are built in the ROM portion of the device, together in a single payload. The
PurePath™ Console GUI provides a means by which to select the HybridFlow and manipulate the controls
associated with that HybridFlow.
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8.2 Functional Block Diagram
Internal
Voltage
Supplies
Charge
Pump
Internal Gate
Drive Regulator
1.8-V
Internal Voltage
Regulator
Supplies
Closed Loop Class D Amplifier
Gate
SPK_OUTA+
SPK_OUTA-
SPK_OUTB+
SPK_OUTB-
Full Bridge
Power
Stage A
Mini-DSP
Output
Current
Monitoring
and
Analog
to
Drives
Hybrid RAM/
ROM
Architecture
with
Several
Selectable
HybridFlows
MCLK
SCLK
PWM
Modulator
Full Bridge
Power
Stage B
Gate
Drives
Protection
DAC
Serial
Audio
Port
LRCK/FS
SDIN
Clock Monitoring
and Error Protection
Die Temperature
Monitoring and Protection
Error Reporting
SDOUT
Internal Control Registers and State Machines
GPIO0
GPIO1 GPIO2
SPK_GAIN/FREQ
SCL
SDA
ADR0
ADR1
SPK_MUTE
SPK_SD SPK_FAULT
8.3 Feature Description
8.3.1 Power-on-Reset (POR) Function
The TAS5756M device has a power-on reset function. This feature resets all of the registers to their default
configuration as the device is powering up. When the low-voltage power supply used to power DVDD, AVDD,
and CPVDD exceeds the POR threshold, the device holds sets all of the internal registers to their default values
and holds them there until it receives valid MCLK, SCLK, and LRCK/FS toggling for a period of approximately 4
ms. After the toggling period has passed, the internal reset of the registers is removed and the registers can be
programmed via the I2C Control Port.
8.3.2 Device Clocking
The TAS5756M devices have flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface in one form or another.
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Feature Description (continued)
fS
(24-bit)
16 fS
(24-bit)
128 fS
(~8-bit)
Serial Audio
Interface
(Input)
miniDSP
(including
interpolator)
Delta
Sigma
Modulator
I to V
Line
Driver
Current
Segments
+
Audio
In
Audio
Out
Charge Pump
CPCK
DSPCK
OSRCK
DACCK
LRCK/FS
Figure 60. Audio Flow with Respective Clocks
Figure 60 shows the basic data flow at basic sample rate (fS). When the data is brought into the serial audio
interface, it is processed, interpolated and modulated to 128 × fS before arriving at the current segments for the
final digital to analog conversion.
Figure 61 shows the clock tree.
PLLEN
(P0-R4)
MCLK
SREF
(P0-R13)
Divider
DDSP (P0-R27)
SCLK
GPIO
MCLK
SDAC
(P0-R14)
PLL
K × R/P
PLLCKIN
PLLCK
K = J.D
J = 1,2,3,…..,62,63
D= 0000,0001,….,9998,9999
R= 1,2,3,4,….,15,16
DACCK (DAC Clock )
MCLK
GPIO
Divider
CPCK (Charge Pump Clock )
P= 1,2,….,127,128
DDAC
(P0-R28)
Divider
DNCP (P0-R29)
OSRCK
(Oversampling
Ratio Clock )
Divider
MUX
DOSR
(P0-R30)
Divide
by 2
I16E (P0-R34)
Figure 61. TAS5756M Clock Distribution Tree
The Serial Audio Interface typically has 4 connection pins which are listed as follows:
•
•
•
MLCK (System Master Clock)
SLCK (Bit Clock)
LRCK/FS (Left Right Word Clock and Frame Sync)
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Feature Description (continued)
•
SDIN (Input Data. The output date, SDOUT, is presented on one of the GPIO pins. See the Serial Data
Output section)
The device has an internal PLL that is used to take either MLCK or SLCK and create the higher rate clocks
required by the and the DAC clock.
In situations where the highest audio performance is required, bringing MLCK to the device along with SLCK and
LRCK/FS is recommended. The device should be configured so that the PLL is only providing a clock source to
the DSP. All other clocks are then a division of the incoming MLCK. To enable the MCLK as the main source
clock, with all others being created as divisions of the incoming MCLK, set the DAC CLK source Mux (SDAC in
Figure 61) to use MLCK as a source, rather than the output of the MLCK/PLL Mux.
8.3.3 Serial Audio Port
8.3.3.1 Clock Master Mode from Audio Rate Master Clock
In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the
appropriate pins. To configure the device in this mode, first put the device into reset, then use registers SLCKO
and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSLCK and RLRK (P0-R12).
Finally, exit reset.
Figure 62 shows a simplified serial port clock tree for the device in master mode.
Audio Related System Clock (MCLK)
MCLK
SCLKO (Bit Clock Output In Master Mode)
Divider
Q1 = 1...128
SCLK
LRCK/FS (LR Clock or Frame Sync Output In
Master Mode
Divider
LRCK/FS
Q1 = 1...128
Figure 62. Simplified Clock Tree for MLCK Sourced Master Mode
In master mode, MLCK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer
divisions of MLCK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the
PLL in standalone mode. The PLL needs to be configured to ensure that the on-chip processor can be driven at
its maximum clock rate. This mode of operation is described in the Clock Master from a Non-Audio Rate Master
Clock section.
When used with audio rate master clocks, the register changes that need to be done include switching the device
into master mode, and setting the divider ratio. An example of this mode of operations is using 24.576 MCLK as
a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz. In this mode,
the DAC section of the device is also running from the PLL output. The TAS5756M device is able to meet the
specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator source will
have less jitter than the PLL.
To switch the DAC clocks (SDAC in the Figure 61) the following registers should be modified
•
•
Clock Tree Flex Mode (P253-R63 and P253-R64)
DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MLCK input, and OSR is set to whatever the
DAC source is)
•
The DAC clock divider should be 16fS.
–
–
–
16 × 48 kHz = 768 kHz
24.576 MHz (MLCK in) / 768 kHz = 32
Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives
0x00 = 1, so 32 must be converter to 0x1F (31dec).
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Feature Description (continued)
8.3.3.2 Clock Master from a Non-Audio Rate Master Clock
The classic example here is running 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for
the device (shown in Figure 61), a non-audio clock rate cannot be brought into the MLCK to the PLL in master
mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another
GPIO pin.
Non-Audio MCLK
GPOIx
PLL
GPOIy
New
Audio
MCLK
MCLK
Master Mode
SLCK Integer
Divider
SCLK
Out
SCLK
Master Mode
LRCK/FS
Integer Divider
LRCK/FS
Out
LRCK/FS
Figure 63. Generating Audio Clocks Using Non-Audio Clock Sources
The clock flow through the system is shown in Figure 63. The newly generated MLCK must be brought out of the
device on a GPIO pin, then brought into the MLCK pin for integer division to create SCLK and LRCK/FS outputs.
NOTE
Pullup resistors should be used on SCLK and LRCK/FS in this mode to ensure the device
remains out of sleep mode.
8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
The TAS5756M device requires a system clock to operate the digital interpolation filters and advanced segment
DAC modulators. The system clock is applied at the MLCK input and supports up to 50 MHz. The TAS5756M
device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling
frequencies in the bands of 8 kHz, 16 kHz, (32 kHz – 44.1 kHz – 48kHz), (88.2 kHz – 96 kHz), and (176.4 kHz –
192 kHz) are supported.
NOTE
Values in the parentheses are grouped when detected, for example, 88.2 kHz and 96 kHz
are detected as double rate, 32 kHz, 44.1 kHz and 48 kHz are detected as single rate and
so on.
In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and
PLL to drive the miniDSP as required.
The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the
Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common
audio sampling rates.
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Feature Description (continued)
MLCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by
configuring various PLL and clock-divider registers directly. In this mode, auto clock mode should be disabled
using P0-R37. Additionally, it may be necessary to ignore clock error detection if external clocks are not-available
for some time during configuration or if the clocks presented on the pins of the device or are invalid. This
extended programmability allows the device to operate in an advanced mode in which it becomes a clock master
and drive the host serial port with LRCK/FS and SLCK, from a non-audio related clock (for example, using a
setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SLCK]).
Table 2 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master
Mode section.
Table 2. System Master Clock Inputs for Audio Related Clocks
SYSTEM CLOCK FREQUENCY (fMLCK) (MHz)
SAMPLING
FREQUENCY
64 fS
128 fS
1.024(2)
2.048(2)
4.096(2)
5.6488(2)
6.144(2)
11.2896(2)
12.288(2)
22.5792
24.576
192 fS
1.536(2)
3.072(2)
6.144(2)
8.4672(2)
9.216(2)
16.9344
18.432
256 fS
2.048
384 fS
3.072
512 fS
4.096
8 kHz
16 kHz
4.096
6.144
8.192
32 kHz
8.192
12.288
16.9344
18.432
33.8688
36.864
16.384
22.5792
24.576
45.1584
49.152
44.1 kHz
48 kHz
11.2896
12.288
22.5792
24.576
45.1584
49.152
See(1)
88.2 kHz
96 kHz
176.4 kHz
192 kHz
33.8688
36.864
See(1)
See(1)
(1) This system clock rate is not supported for the given sampling frequency.
(2) This system clock rate is supported by PLL mode.
8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)
8.3.3.4.1 Clock Generation using the PLL
The TAS5756M device supports a wide range of options to generate the required clocks as shown in Figure 61.
The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SLCK or MLCK, a
GPIO can also be used.
The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-
R13, B[6:4]. The TAS5756M device provides several programmable clock dividers to achieve a variety of
sampling rates. See Figure 61.
If PLL functionality is not required, set the PLLEN value on P0-R4, B[0] to 0. In this situation, an external master
clock is required.
Table 3. PLL Configuration Registers
CLOCK MULTIPLEXER
REGISTER
SREF
FUNCTION
PLL Reference
BITS
P0-R13, B[6:4]
P0-R27, B[6:0]
P0-R32, B[6:0]
P0-R33, B[7:0]
DDSP
clock divider
DSLCK
DLRK
External SLCK Div
External LRCK/FS Div
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8.3.3.4.2 PLL Calculation
The TAS5756M device has an on-chip PLL with fractional multiplication to generate the clock frequency needed
by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of
clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to
50 MHz and is register programmable to enable generation of required sampling rates with fine precision.
The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, B[0]. When the PLL is enabled, the
PLL output clock PLLCK is given by Equation 1:
PLLCKIN x R x J.D
P
PLLCKIN x R x K
P
PLLCK =
or PLLCK =
where
•
•
•
•
R = 1, 2, 3,4, ... , 15, 16
J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999
K = [J value].[D value]
P = 1, 2, 3, ... 15
(1)
R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while
D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).
8.3.3.4.2.1 Examples:
•
•
•
•
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied:
•
•
•
1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
1 ≤ J ≤ 63
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:
•
•
•
•
6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz
64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz
4 ≤ J ≤ 11
R = 1
When the PLL is enabled,
•
•
fS = (PLLCLKIN × K × R) / (2048 × P)
The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.
Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Values are written to the registers in Table 4.
Table 4. PLL Registers
DIVIDER
PLLE
FUNCTION
PLL enable
PLL P
BITS
P0-R4, B[0]
PPDV
PJDV
P0-R20, B[3:0]
P0-R21, B[5:0]
P0-R22, B[5:0]
P0-R23, B[7:0]
P0-R24, B[3:0]
PLL J
PDDV
PRDV
PLL D
PLL R
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Table 5. PLL Configuration Recommendations
EQUATIONS
fS (kHz)
DESCRIPTION
Sampling frequency
RMLCK
Ratio between sampling frequency and MLCK frequency (MLCK frequency = RMLCK x sampling frequency)
System master clock frequency at MLCK input (pin 20)
MLCK (MHz)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 61
One of the PLL coefficients in Equation 1
PLL REF (MHz) Internal reference clock frequency which is produced by MLCK / P
P
M = K × R
K = J.D
R
The final PLL multiplication factor computed from K and R as described in Equation 1
One of the PLL coefficients in Equation 1
One of the PLL coefficients in Equation 1
PLL fS
DSP fS
NMAC
Ratio between fS and PLL VCO frequency (PLL VCO / fS)
Ratio between operating clock rate and fS (PLL fS / NMAC)
The clock divider value in Table 3
DSP CLK (MHz) The operating frequency as DSPCK in Figure 61
MOD fS
Ratio between DAC operating clock frequency and fS (PLL fS / NDAC)
MOD f (kHz)
NDAC
DAC operating frequency as DACCK in
DAC clock divider value in Table 3
OSR clock divider value in Table 3 for generating OSRCK in Figure 61. DOSR must be chosen so that MOD fS / DOSR =
16 for correct operation.
DOSR
NCP
CP f
NCP (negative charge pump) clock divider value in Table 3
Negative charge pump clock frequency (fS × MOD fS / NCP)
Percentage of error between PLL VCO / PLL fS and fS (mismatch error).
% Error
•
•
This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).
This value may be non-zero only when the TAS5756M device acts as a master.
The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL.
Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.
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Table 6. Recommended Clock Divider Settings for PLL as Master Clock
fS
(kHz)
MCLK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
CP f
(kHz)
RMLCK
P
M = K×R
K = J×D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% ERROR
NCP
128
192
1.024
1.536
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
3
3
3
3
9
9
9
9
1
3
1
3
3
3
3
9
9
9
9
1
1
1
1
3
3
3
3
3
9
9
9
1.024
1.536
2.048
1.024
1.365
2.048
2.731
1.024
1.365
1.82
96
64
48
96
72
48
36
96
72
54
36
64
128
32
64
48
32
24
64
48
36
24
96
48
32
24
48
36
24
18
16
36
27
18
48
32
48
48
36
48
36
48
36
54
36
32
32
32
32
48
32
24
32
48
36
24
48
48
32
24
48
36
24
18
16
36
27
18
2
2
1
2
2
1
1
2
2
1
1
2
4
1
2
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
12288
12288
12288
12288
12288
12288
12288
12288
12288
12288
12288
8192
8192
8192
8192
8192
8192
8192
8192
8192
8192
8192
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
12
12
12
12
12
12
12
12
12
12
12
8
8.192
8.192
768
768
768
768
768
768
768
768
768
768
768
512
512
512
512
512
512
512
512
512
512
512
384
384
384
384
384
384
384
384
384
384
384
384
6144
6144
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
48
48
48
48
48
48
48
48
48
48
48
32
32
32
32
32
32
32
32
32
32
32
24
24
24
24
24
24
24
24
24
24
24
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
256
2.048
8.192
6144
1536
384
3.072
8.192
6144
1536
512
4.096
8.192
6144
1536
8
768
6.144
8.192
6144
1536
1024
1152
1536
2048
3072
128
8.192
8.192
6144
1536
9.216
8.192
6144
1536
12.288
16.384
24.576
1.4112
2.1168
2.8224
4.2336
5.6448
8.4672
11.2896
12.7008
16.9344
22.5792
33.8688
1.024
8.192
6144
1536
8.192
6144
1536
2.731
1.411
0.706
2.822
1.411
1.882
2.822
3.763
1.411
1.882
2.509
3.763
1.024
2.048
3.072
4.096
2.048
2.731
4.096
5.461
6.144
2.731
3.641
5.461
8.192
6144
1536
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
16.384
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
6144
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1536
192
8
256
8
384
8
512
8
11.025
768
8
1024
1152
1536
2048
3072
64
8
8
8
8
8
6
128
2.048
6
6144
1536
192
3.072
6
6144
1536
256
4.096
6
6144
1536
384
6.144
6
6144
1536
512
8.192
6
6144
1536
16
768
12.288
16.384
18.432
24.576
32.768
49.152
6
6144
1536
1024
1152
1536
2048
3072
6
6144
1536
6
6144
1536
6
6144
1536
6
6144
1536
6
6144
1536
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Table 6. Recommended Clock Divider Settings for PLL as Master Clock (continued)
fS
(kHz)
MCLK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
CP f
(kHz)
RMLCK
P
M = K×R
K = J×D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% ERROR
NCP
64
128
192
256
384
512
768
1024
1152
1536
2048
32
1.4112
2.8224
4.2336
5.6448
8.4672
11.2896
16.9344
22.5792
25.4016
33.8688
45.1584
1.024
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
1
1
3
1
3
3
3
3
9
9
9
1
1
1
1
3
2
3
3
3
3
9
6
1
1
1
3
2
3
3
3
3
1.411
2.822
1.411
5.645
2.822
3.763
5.645
7.526
2.822
3.763
5.018
1.024
1.536
2.048
4.096
2.048
4.096
4.096
5.461
8.192
10.923
4.096
8.192
1.411
2.822
5.645
2.822
5.645
5.645
7.526
11.29
15.053
64
32
64
16
32
24
16
12
32
24
18
96
64
48
24
48
24
24
18
12
9
32
32
32
16
32
24
16
12
32
24
18
48
16
24
24
48
24
24
18
12
9
2
1
2
1
1
1
1
1
1
1
1
2
4
2
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
3072
2048
2048
2048
2048
2048
2048
2048
2048
2048
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
22.5792
32.768
256
256
256
256
256
256
256
256
256
256
256
192
192
192
192
192
192
192
192
192
192
192
192
128
128
128
128
128
128
128
128
128
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
6144
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
12
12
12
12
12
12
12
12
12
12
12
12
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1536
22.05
48
1.536
98.304
32.768
6144
1536
64
2.048
98.304
32.768
6144
1536
128
192
256
384
512
768
1024
1152
1536
32
4.096
98.304
32.768
6144
1536
6.144
98.304
32.768
6144
1536
8.192
98.304
32.768
6144
1536
32
12.288
16.384
24.576
32.768
36.864
49.152
1.4112
2.8224
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
45.1584
98.304
32.768
6144
1536
98.304
32.768
6144
1536
98.304
32.768
6144
1536
98.304
32.768
6144
1536
98.304
24
12
64
32
16
32
16
16
12
8
24
12
32
16
16
32
16
16
12
8
32.768
6144
1536
98.304
32.768
6144
1536
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
45.1584
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
5644.8
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
1411.2
64
8
128
192
256
384
512
768
1024
8
8
44.1
8
8
8
8
6
6
8
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Table 6. Recommended Clock Divider Settings for PLL as Master Clock (continued)
fS
(kHz)
MCLK
(MHz)
PLL VCO
(MHz)
PLL REF
(MHz)
DSP CLK
(MHz)
MOD f
(kHz)
CP f
(kHz)
RMLCK
P
M = K×R
K = J×D
R
PLL fS
DSP fS
NMAC
MOD fS
NDAC
DOSR
% ERROR
NCP
32
64
1.536
3.072
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
1
1
1
3
2
3
3
3
3
1
3
1
2
3
4
6
8
1
3
1
2
3
4
1.536
3.072
6.144
3.072
6.144
6.144
8.192
12.288
16.384
3.072
1.536
6.144
6.144
6.144
6.144
6.144
6.144
6.144
3.072
12.288
12.288
12.288
12.288
64
32
16
32
16
16
12
8
32
16
16
32
16
16
12
8
2
2
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
1
1
1
2048
2048
2048
2048
2048
2048
2048
2048
2048
1024
1024
1024
1024
1024
1024
1024
1024
512
1024
1024
1024
1024
1024
1024
1024
1024
1024
512
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
49.152
128
128
128
128
128
128
128
128
128
64
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
6144
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
1536
128
192
256
384
512
768
1024
32
6.144
9.216
48
12.288
18.432
24.576
36.864
49.152
3.072
6
6
32
64
16
16
16
16
16
16
16
32
8
16
32
8
48
4.608
512
64
64
6.144
512
64
128
192
256
384
512
32
12.288
18.432
24.576
36.864
49.152
6.144
16
16
16
16
16
8
512
64
96
512
64
512
64
512
64
512
64
256
32
48
9.216
16
4
512
256
32
64
12.288
24.576
36.864
49.152
512
256
32
192
128
192
256
8
8
512
256
32
8
8
512
256
32
8
8
512
256
32
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8.3.3.5 Serial Audio Port – Data Formats and Bit Depths
The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN
(pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift
register of the audio interface. Serial data is clocked into the TAS5756M device on the rising edge of SCLK.The
LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
Table 7. TAS5756M device Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCK/FS
FREQUENCY (kHz)
FORMAT
DATA BITS
MCLK RATE (fS)
SCLK RATE (fS)
I2S/LJ/RJ
32, 24, 20, 16
Up to 192
Up to 48
96
128 to 3072 (≤ 50 MHz)
128 to 3072
64, 48, 32
125, 256
125, 256
128
TDM/DSP
32, 24, 20, 16
128 to 512
192
128, 192, 256
The TAS5756M device requires the synchronization of LRCK/FS and system clock, but does not need a specific
phase relation between LRCK/FS and system clock.
If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is
initialized within one sample period and analog outputs are forced to the bipolar zero level until re-
synchronization between LRCK/FS and system clock is completed.
If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is
initialized within one sample period and analog outputs are forced to the bipolar zero level until re-
synchronization between LRCK/FS and SCLK is completed.
8.3.3.5.1 Data Formats and Master/Slave Modes of Operation
The TAS5756M device supports industry-standard audio data formats, including standard I2S and left-justified.
Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio
data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 64 through Figure 69.
The TAS5756M device also supports right-justified and TDM/DSP data. I2S, LJ, RJ, and TDM/DSP are selected
using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are
accepted. Default setting is I2S and 24 bit word length. The I2S slave timing is shown in .
shows a detailed timing diagram for the serial audio interface.
In addition to acting as a I2S slave, the TAS5756M device can act as an I2S master, by generating SCLK and
LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or
Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing
requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave
Mode section.
Table 8. I2S Master Mode Registers
REGISTER
FUNCTION
P0-R9-B0, B4, and B5
P0-R32-B[6:0]
I2S Master mode select
SCLK divider and LRCK/FS divider
P0-R33-B[7:0]
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1 tS .
Right-channel
Left-channel
LRCK/FS
SLCK
…
…
…
…
…
…
…
Audio data word = 16-bit, SLCK = 32, 48, 64fS
…
1
2
15 16
1
1
2
15 16
DATA
LSB
LSB
MSB
MSB
Audio data word = 24-bit, SLCK = 48, 64fS
…
…
2
1
2
24
2
23 24
DATA
LSB
LSB
MSB
MSB
Audio data word = 32-bit, SLCK = 64fS
…
…
1
2
31 32
1
2
31 32
DATA
MSB
LSB
MSB
LSB
Figure 64. Left Justified Audio Data Format
1 tS .
LRCK/FS
SLCK
Left-channel
Right-channel
…
…
…
…
…
…
Audio data word = 16-bit, SLCK = 32, 48, 64fS
…
…
1
2
15 16
1
1
2
15 16
DATA
LSB
LSB
MSB
MSB
Audio data word = 24-bit, SLCK = 48, 64fS
…
…
2
2
23 24
1
23 24
DATA
LSB
MSB
LSB
MSB
Audio data word = 32-bit, SLCK = 64fS
…
…
1
2
31 32
1
2
31 32
DATA
MSB
LSB
MSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 65. I2S Audio Data Format
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1 /fS .
Right-channel
Left-channel
LRCK/FS
…
…
…
…
…
…
SLCK
Audio data word = 16-bit, SLCK = 32, 48, 64fS
DATA
…
…
1
2
15 16
1
2
15 16
LSB
LSB
MSB
MSB
Audio data word = 24-bit, SLCK = 48, 64fS
…
…
2
1
2
24
1
2
23 24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, SLCK = 64fS
…
…
1
2
31 32
1
2
31 32
DATA
MSB
LSB
MSB
LSB
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 66. Right Justified Audio Data Format
1 /fS .
LRCK/FS
SLCK
…
…
…
…
…
…
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
-
,
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM/DSP Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 67. TDM/DSP 1 Audio Data Format
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1 /fS .
OFFSET = 1
LRCK/FS
…
…
…
…
…
SLCK
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM/DSP Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 68. TDM/DSP 2 Audio Data Format
1 /fS .
OFFSET = n
LRCK/FS
SLCK
…
…
…
…
…
Audio data word = 16-bit, Offset = n
…
…
1
2
15 16
1
2
15 16
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = n
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = n
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
Data Slot 1
Data Slot 2
MSB
TDM/DSP Data Format with OFFSET = N
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 69. TDM/DSP 3 Audio Data Format
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8.3.3.6 Input Signal Sensing (Power-Save Mode)
The TAS5756M device has a zero-detect function. This function can be applied to both channels of data as an
AND function or an OR function, via controls provided in the control port in P0-R65-B[2:1].Continuous Zero data
cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59, B[6:4] for
the data which is clocked in on the left frame of an I2S signal or Slot 1 of a TDM signal and P0-R59, B[2:0] for
the data which is clocked in on the right frame of an I2S signal or Slot 2 of a TDM signal as shown in Table 10.
Default values are 0 for both channels.
Table 9. Zero Detection Mode
ATMUTECTL
VALUE
FUNCTION
Zero data triggers for the two channels for zero detection are
ORed together.
0
Bit : 2
Zero data triggers for the two channels for zero detection are
ANDed together.
1 (Default)
0
Zero detection and analog mute are disabled for the data
clocked in on the right frame of an I2S signal or Slot 2 of a
TDM signal.
Bit : 1
Bit : 0
Zero detection analog mute are enabled for the data clocked in
on the right frame of an I2S signal or Slot 2 of a TDM signal.
1 (Default)
0
Zero detection analog mute are disabled for the data clocked
in on the left frame of an I2S signal or Slot 1 of a TDM signal.
Zero detection analog mute are enabled for the data clocked in
on the left frame of an I2S signal or Slot 1 of a TDM signal.
1 (Default)
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Table 10. Zero Data Detection Time
ATMUTETIML OR
ATMA
NUMBER OF
LRCK/FS CYCLES
TIME at 48 kHz
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1024
5120
21 ms
106 ms
10240
25600
51200
102400
256000
512000
213 ms
533 ms
1.066 secs
2.133 secs
5.333 secs
10.66 secs
8.3.3.7 Serial Data Output
If it is supported by the HybridFlow in use, the TAS5756M device can present serial data on one of the three
available hardware pins, GPIO0, GPIO1, or GPIO2. In a HybridFlow which supports serial data out, the serial
data out origin can always be configured to come before the mini-DSP, by clearing the SDSL bit in P0-R7. This
feature is used as a loop-back to check the integrity of the data transmission from the source to the TAS5756M
device . In addition to the default loop-back mode, HybridFlows allows the SDOUT signal to originate from either
a point after the processing or from some intermediary point within the HybridFlow. This option is accomplished
by setting the SDSL bit in P0-R7. Figure 70 shows how to configure the origin of the serial data output signal.
MiniDSP
!udio
trocessing
Serial Audio Input
To Speaker Amplifier
Mux
To GPIO Configuration to
be presented on GPIO pins
Mux
{5{[
(t0-ꢁ7)
Çhis mux, if presenꢀ, is
unique ꢀo each IybridClow
and has unique conꢀrols
Figure 70. Serial Data Output Signal
Choosing the origin to be after all processing has been applied to the signal (i.e. before it is sent to the amplifier)
is popular for sending a monitor signal back to a voice processing or echo-cancelling device elsewhere in the
system. Other origins may configure the signal to originate after a subwoofer generation block, which sums in the
inputs and applies a low-pass filter to create a mono, low-frequency signal. Please refer to the target
HybridFlows for details regarding the options for the serial data output.
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8.3.4 Modulation Scheme
8.3.4.1 BD-Modulation
The TAS5756M uses BD modulation. This modulation scheme allows operation without the classic LC output
filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to
the supply voltage PVDD. The SPK_OUTx+ and SPK_OUTx- are in phase with each other with no input signal
so that there is little or no current in the speaker. The duty cycle of SPK_OUTx+ is greater than 50% and
SPK_OUTx- is less than 50% for positive output voltages. The duty cycle of SPK_OUTx+ is less than 50% and
SPK_OUTx- is greater than 50% for negative output voltages. The voltage across the load remains at 0 V
throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the
load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 71. BD-Modulation
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8.3.5 miniDSP Audio Processing Engine
The TAS5756M device integrates a highly efficient processing engine called a miniDSP. The miniDSP in the
TAS5756M device uses a Hybrid architecture in which some processing blocks are built in ROM and other
processing blocks are created in RAM via the PurePath™ Control Console GUI. This approach allows the
flexibility of a fully-programmable device to be combined with the ease of use and rapid download time of a hard-
coded ROM device.
8.3.5.1 HybridFlow Architecture
The Hybrid RAM and ROM Architecture allows the device to be highly flexible, but also easy to use. Unlike a
device where all digital processing blocks are hard-coded in ROM, the hybrid RAM and ROM architecture allows
a variety of processing blocks to be used in various combinations with various connectivity. These combinations
of processing blocks are called HybridFlows.
HybridFlows are generated by combining a collection of processing blocks together in a targeted manner so that
the device is well suited for a particular application or use case. Some HybridFlows are targeted for stereo
applications, while others are targeted for mono, 1.1 (Bi-Amped), or 2.1 configurations.
It is important to note that the amount of processing which can be combined together into a given process flow is
highly dependent on the sample rate of the audio signal which is being processed. For instance, an audio signal
at 48 kHz can have much more processing applied than the same signal presented to the TAS5756M device at
192 kHz sample rate. For this reason, a HybridFlow which supports only up to 48 kHz sample rate cannot be
used with a 192 kHz input signal.
8.3.5.2 Volume Control
8.3.5.2.1 Digital Volume Control
A basic digital volume control with range between 24 dB and 103 dB and mute is available on each channels by
P0-R61-B[7:0] for SPK_OUTB± and P0-R62-B[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB step
programmability over most gain and attenuation ranges. Table 11 lists the detailed gain versus programmed
setting for this basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the
same time or independently by P0-R61-B[1:0] . When B[1:0] set 00 (default), independent control is selected.
When B[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When B[1:0] set 10, SPK_OUTA± volume
controls the volume for both channels. To set B[1:0] to 11 is prohibited.
Table 11. Digital Volume Control Settings
GAIN
SETTING
GAIN
(dB)
BINARY DATA
COMMENTS
0
1
0000-0000
0000-0001
24.0
23.5
Positive maximum
.
.
.
.
.
.
.
.
.
46
47
48
49
50
51
0010-1110
0010-1111
0011-0000
0011-0001
0011-0010
0011-0011
1.0
0.5
0.0
No attenuation (default)
–0.5
–1.0
–1.5
.
.
.
.
.
.
.
.
.
253
254
255
1111-1101
1111-1110
1111-1111
–102.5
–103
Negative maximum
–
Negative infinite (Mute)
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Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, B[7:6] and B[3:2] as shown in
Table 12. Also ramp-up step and ramp-down step can be controlled by P0-R63, B[5:4] and B[1:0] as shown in
Table 13.
Table 12. Ramp Up or Down Frequency
RAMP UP
SPEED
RAMP DOWN
FREQUENCY
EVERY N fS
COMMENTS
EVERY N fS
COMMENTS
00
01
10
11
1
Default
00
01
10
11
1
Default
2
2
4
4
Direct change
Direct change
Table 13. Ramp Up or Down Step
RAMP UP
STEP
RAMP DOWN
COMMENTS
STEP dB
STEP dB
COMMENTS
STEP
00
01
10
11
4.0
2.0
1.0
0.5
00
01
–4.0
–2.0
–1.0
–0.5
Default
10
11
Default
8.3.5.2.1.1 Emergency Volume Ramp Down
Emergency ramp down of the volume by is provided for situations such as I2S clock error and power supply
failure. Ramp-down speed is controlled by P0-R64-B[7:6]. Ramp-down step can be controlled by P0-R64-B[5:4].
Default is ramp-down by every fS cycle with –4dB step.
8.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
The voltage divider between the GVDD_REG pin a the SPK_GAIN/FREQ pin is used to set the gain and
switching frequency of the amplifier. Upon start-up of the device, the voltage presented on the SPK_GAIN/FREQ
pin is digitized and then decoded into a 3-bit word which is interpreted inside the TAS5756M device to
correspond to a given gain and switching frequency. In order to change the SPK_GAIN or switching frequency of
the amplifier, the device must first be powered down, and then powered back back, with the new voltage level
presented to the device on the SPK_GAIN/FREQ pin.
Because the amplifier adds gain to both the signal and the noise present in the audio signal, the lowest gain
setting that can meet voltage-limited output power targets should be used. This ensures that the power target
can be reached while minimizing the idle channel noise of the system. The switching frequency selection affects
three important operating characteristics of the device. These are the power dissipation in the device, the power
dissipation in the inductor, and the target output filter for the application.
Higher switching frequencies typically result in slightly higher power dissipation in the TAS5756M device and
lower dissipation in the inductor in the system, due to decreased ripple current through the inductor and
increased charging and discharging current in device and parasitic capacitances. Switching at the higher of the
two available switching frequencies will result in lower overall dissipation in the system and lower operating
temperature of the inductors. However, the thermally limited power output of the device may be decreased in this
situation, because some of the TAS5756M device thermal headroom will be absorbed by the higher switching
frequency. Conversely inductor heating can be reduced by using the higher switching frequency to reduce the
ripple current.
Another advantage of increasing the switching frequency is that the higher frequency carrier signal can be filtered
by an L-C filter with a higher corner frequency, leading to physically smaller components. Use the highest
switching frequency that continues to meet the thermally limited power targets for the application. If thermal
constraints require heat reduction in the TAS5756M device, use a lower switching rate.
The switching frequency of the speaker amplifier is dependent on an internal synchronizing signal, (fSYNC), which
is synchronous with the sample rate. The rate of the synchronizing signal is also dependent on the sample rate.
Refer to Table 14 below for details regarding how the sample rates correlate to the synchronizing signal.
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Table 14. Sample Rates vs Synchronization Signal
SAMPLE RATE
fSYNC
[kHz]
[kHz]
8
16
32
96
48
96
192
11.025
22.05
44.1
88.2
88.2
Table 15 summarizes the de-code of the voltage presented to the SPK_GAIN/FREQ pin. The voltage presented
to the SPK_GAIN/FREQ pin is latched in upon startup of the device. Subsequent changes require power cycling
the device. A gain setting of 20 dBV is recommended for nominal supply voltages of 13 V and lower, while a gain
of 26 dBV is recommended for supply voltages up to 26.4 V. Table 15 shows the voltage required at the
SPK_GAIN/FREQ pin for various gain and switching scenarios as well some example resistor values for meeting
the voltage range requirements.
Table 15. Amplifier Switching Mode vs. SPK_GAIN/FREQ Voltage
VSPK_GAIN/FREQ (V)
RESISTOR EXAMPLES
AMPLIFIER
SWITCHING
FREQUENCY MODE
R100 (kΩ): RESISTOR TO
GROUND
R101 (kΩ): RESISTOR TO
GVDD_REG
GAIN MODE
MIN
MAX
6.61
5.44
7
Reserved
Reserved
Reserved
8 × fSYNC
R100 = 750
R101 = 150
6.6
R100 = 390
R101 = 150
4.67
3.89
3.11
2.33
1.56
0.78
0
5.43
4.66
3.88
3.1
6 × fSYNC
5 × fSYNC
4 × fSYNC
8 × fSYNC
6 × fSYNC
5 × fSYNC
4 × fSYNC
26dBV
R100 = 220
R101 = 150
R100 = 150
R101 = 150
R100 = 100
R101 = 150
R100 = 56
R101 = 150
2.32
1.55
0.77
20dBV
R100 = 33
R101 = 150
R100 = 8.2
R101 = 150
8.3.7 Error Handling and Protection Suite
8.3.7.1 Device Overtemperature Protection
The TAS5756M device continuously monitors die temperature to ensure it does to exceed the OTETHRES level
specified in the Recommended Operating Conditions table. If an OTE event occurs, the SPK_FAULT line is
pulled low and out the SPK_OUTxx outputs transition to high impedance, signifying a fault. This is a non-latched
error and will attempt to self clear after OTECLRTIME has passed.
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8.3.7.2 SPK_OUTxx Overcurrent Protection
The TAS5756M device continuously monitors the output current of each amplifier output to ensure it does to
exceed the OCETHRES level specified in the Recommended Operating Conditions table. If an OCE event occurs,
the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault.
This is a non-latched error and will attempt to self clear after OCECLRTIME has passed.
8.3.7.3 DC Offset Protection
If the TAS5756M device measures a DC offset in the output voltage, the SPK_FAULT line is pulled low and the
SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error require the SPK_MUTE
line to toggle to reset the error. Alternatively, pulling the MCLK, SCLK, or LRCK low causes a clock error, which
also resets the device. Normal operation resumes by re-starting the stopped clock.
8.3.7.4 Internal VAVDD Undervoltage-Error Protection
The TAS5756M device internally monitors the AVDD net to protect against the AVDD supply dropping
unexpectedly. To enable this feature, P1-R5-B0 is used.
8.3.7.5 Internal VPVDD Undervoltage-Error Protection
If the voltage presented on the PVDD supply drops below the UVETHRES(PVDD) value listed in the Recommended
Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error,
which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions
table, the device resumes normal operation.
8.3.7.6 Internal VPVDD Overvoltage-Error Protection
If the voltage presented on the PVDD supply exceeds the OVETHRES(PVDD) value listed in the Recommended
Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing
error, which means that once the PVDD level drops below the level listed in the Recommended Operating
Conditions table, the device will resume normal operation. It is important to note that this voltage only protects up
to the level described in the Recommended Operating Conditions table for the PVDD voltage. Exceeding this
absolute maximum rating causes damage and possible device failure, because the levels exceed that which can
be protected against by the OVE protection circuit.
8.3.7.7 External Undervoltage-Error Protection
The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack
in portable device, by using a voltage divider created with two resistors (see Figure 72).
•
If the SPK_MUTE pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external
undervoltage protection mode. This mode uses two trigger levels.
•
•
When the SPK_MUTE pin level reaches 2 V, soft mute process begins.
When the SPK_MUTE pin level reaches 1.2 V, analog output mute engages, regardless of digital audio level,
and analog output shutdown begins.
Figure 73 shows a timing diagram for external undervoltage error protection.
NOTE
The SPK_MUTE input pin voltage range is provided in the Recommended Operating
Conditions table. The ratio of external resistors must produce a voltage within this input
range. Any increase in power supply (such as power supply positive noise or ripple) can
pull the SPK_MUTE pin higher than that the level specified in the Recommended
Operating Conditions table, potentially causing damage to or failure of the device.
Therefore, it is imperative that any monitored voltage (including all ripple, power supply
variation, resistor divider variation, transient spikes, and others) is scaled by the resistor
divider network to never drive the voltage on the SPK_MUTE pin higher than the
maximum level specified in the Recommended Operating Conditions table.
When the divider is set correctly, any DC voltage can be monitored. Figure 72 shows a 12-V example of how the
SPK_MUTE is used for external undervoltage error protection.
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VDD
12 V
7.25 kΩ
2.75 kΩ
SPK_MUTE
Figure 72. SPK_MUTE Used in External Undervoltage Error Protection
Digital attenuation followed by analog mute
Analog mute
SPK_MUTE
0.9 × DV
DD
2.0 V
1.2 V
0.1 × DV
DD
t
f
Figure 73. SPK_MUTE Timing for External Undervoltage Error Protection
8.3.7.8 Internal Clock Error Notification (CLKE)
8.3.8 GPIO Port and Hardware Control Pins
The TAS5756M device includes a versatile GPIO port, allowing signals to be passed from the system to the
device or sent out of the device to the system. There are three GPIO pins available for use. These pins can be
used for advanced clocking features, to pass internal signals to the system or accept signals from the system for
use inside the device by a HybridFlow, or simply to monitor the status of an external signal via I2C. The GPIO
port requires some configuration in the control port. This configuration is detailed in Figure 74.
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Internal Data
(P0-R82)
GPIOx Output Enable
P0-R8
GPIOx Output Inversion
P0-R87
GPIOx Output Selection
P0-R82
Off (low)
DSP GPIOx output
Register GPIOx output (P0-R86)
Auto mute flag (Both A and B)
Auto mute flag (Channel B)
Auto mute flag (Channel A)
Clock invalid flag
Mux
GPIOx
Mux
Serial Audio Data Output
Analog mute flag for B
Analog mute flag for A
PLL lock flag
Charge Pump Clock
Under voltage flag 1
Under voltage flag 2
PLL output/4
GPIOx Input State
Monitoring
(P0-R119)
To MiniDSP
To Clock Tree
Figure 74. GPIO Port
In addition to the dynamic controls which can be implemented with the GPIO port, each HybridFlow uses the
GPIO port as required. In some HybridFlows, a GPIO is used to present an internal serial audio data signal to a
system controller. In others, the status of a GPIO pin is monitored and the status of that pin is used to adjust the
audio processing applied to the signal. Refer to each HybridFlow for specifics regarding how the GPIO port is
used. GPIOs which have been allocated to a function in a HybridFlow can be reassigned using the same controls
as those listed in Figure 74. However, they no longer serve the purpose intended by the design of the
HybridFlow.
8.3.9 I2C Communication Port
The TAS5756M device supports the I2C serial bus and the data transmission protocol for standard and fast mode
as a slave device. Because the TAS5756M register map spans several pages, it is be necessary to change from
page to page before writing individual register bits or bytes. This is accomplished via register 0 on each page.
This register value selects the register page, from 0 to 255.
8.3.9.1 Slave Address
Table 16. I2C Slave Address
MSB
1
LSB
0
0
1
1
ADR2
ADR1
R/ W
The TAS5756M device has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are
factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be
user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus
at one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E, as detailed below. Each TAS5756M device
responds when it receives its own slave address.
Table 17. I2C Address Configuration via ADR0 and ADR1 Pins
ADR1
ADR0
I2C SLAVE ADDRESS [R/W]
0
0
1
1
0
1
0
1
0x99/0x98
0x9B/0x9A
0x9D/0x9C
0x9F/0x9E
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8.3.9.2 Register Address Auto-Increment Mode
MSB
LSB
A0
INC
A6
A5
A4
A3
A2
A1
Figure 75. Auto Increment Mode
Auto-increment mode allows multiple sequential register locations to be written to or read back in a single
operation, and is especially useful for block write and read operations.
8.3.9.3 Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit,
data if write or acknowledge if read, and stop condition. The TAS5756M device supports only slave receivers and
slave transmitters.
SDA
SCL
9
1–7
8
9
1–8
9
1–8
9
Sp
St
Slave address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
Start
condition
Stop
condition
R/W: Read operation if 1; otherwise, write operation
ACK: Acknowledgement of a byte if 0
DATA: 8 bits (byte)
Figure 76. Packet Protocol
Table 18. Write Operation - Basic I2C Framework
Transmitter
Data Type
M
M
M
S
M
S
M
S
S
M
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
ACK
Sp
Table 19. Read Operation - Basic I2C Framework
Transmitter
Data Type
M
M
M
S
S
M
S
M
M
M
St
slave address
R/
ACK
DATA
ACK
DATA
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition
8.3.9.4 Write Register
A master can write to any TAS5756M device registers using single or multiple accesses. The master sends a
TAS5756M device slave address with a write bit, a register address with auto-increment bit, and the data. If auto-
increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the
data is received properly, the index register is incremented by 1 automatically. When the index register reaches
0x7F, the next value is 0x0. Table 20 shows the write operation.
Table 20. Write Operation
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
S
S
M
reg
addr
write
data 1
write
data 2
St
slave addr
W
ACK
inc
ACK
ACK
ACK
ACK
Sp
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M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge
8.3.9.5 Read Register
A master can read the TAS5756M device register. The value of the register address is stored in an indirect index
register in advance. The master sends a TAS5756M device slave address with a read bit after storing the
register address. Then the TAS5756M device transfers the data which the index register points to. When auto-
increment is enabled, the index register is incremented by 1 automatically. When the index register reaches
0x7F, the next value is 0x0. Table 21 lists the read operation.
Table 21. Read Operation
Transmitter
Data Type
M
M
M
S
M
S
M
M
M
S
S
M
M
M
slave
addr
reg
addr
slave
addr
St
W
ACK
inc
ACK
Sr
R
ACK
data
ACK
NACK
Sp
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition;
W = Write; R = Read; NACK = Not acknowledge
8.4 Device Functional Modes
Because the TAS5756M device is a highly configurable device, numerous modes of operation can exist for the
device. For the sake of succinct documentation, these modes are divided into two modes:
•
•
Fundamental operating modes
Secondary usage modes
Fundamental operating modes are the primary modes of operation that affect the major operational
characteristics of the device. These are the most basic configurations that are chosen to ensure compatibility
with the intended application or the other components that interact with the device in the final system. Some
examples of these are the communication protocol used by the control port, the output configuration of the
amplifier, or the Master/Slave clocking configuration.
The fundamental operating modes are described starting in the Serial Audio Port Operating Modes section.
Secondary usage modes are best described as modes of operation that are used after the fundamental operating
modes are chosen to fine tune how the device operates within a given system. These secondary usage modes
may include selecting between left justified and right justified Serial Audio Port data formats, or enabling some
slight gain/attenuation within the DAC path. Secondary usage modes are accomplished through manipulation of
the registers and controls in the I2C control port. Those modes of operation are described in their respective
register/bit descriptions and, to avoid redundancy, are not included in this section.
8.4.1 Serial Audio Port Operating Modes
The serial audio port in the TAS5756M device supports industry-standard audio data formats, including I2S, Time
Division Multiplexing (TDM), Left-Justified (LJ), and Right-Justified (RJ) formats. To select the data format that
will be used with the device, controls are provided on P0-R40. The timing diagrams for the serial audio port are
shown in the Serial Audio Port Timing – Slave Mode section, and the data formats are shown in the Serial Audio
Port – Data Formats and Bit Depths section.
8.4.2 Communication Port Operating Modes
The TAS5756M device is configured via an I2C communication port. The device does not support a hardware
only mode of operation, nor Serial Peripheral Interface (SPI) communication. The I2C Communication Protocol is
detailed in the I2C Communication Port section. The I2C timing requirements are described in the I2C Bus
Timing – Standard and I2C Bus Timing – Fast sections.
8.4.3 Audio Processing Modes via HybridFlow Audio Processing
The TAS5756M device can be configured to include several different audio processing features through the use
of pre-defined DSP loads called HybridFlows. These HybridFlows have been created and tested to be application
focused. This approach results in a device which offers the flexibility of a programmable device with the ease-of-
use and fast download time of a fixed function device. The HybridFlows are selected and downloaded using the
PurePath™ ControlConsole software. .
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Device Functional Modes (continued)
8.4.4 Speaker Amplifier Operating Modes
The TAS5756M device can be used in three different amplifier configurations:
•
•
•
Stereo Mode
Mono Mode
Bi-Amp Mode
8.4.4.1 Stereo Mode
The familiar stereo mode of operation uses the TAS5756M device to amplify two independent signals, which
represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented
on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is
presented on the SPK_OUTxx outputs can be changed according to the HybridFlow which is used and the
configuration of registers P0-R42-B[5:4] and P0-R42-B[1:0]. This mode of operation is shown in Figure 79.
By default, the TAS5756M device is configured to output the Right frame of a I2S input on the Channel A output
and the left frame on the Channel B output.
8.4.4.2 Mono Mode
This mode of operation is used to describe operation in which the two outputs of the device are placed in parallel
with one another to increase the power sourcing capabilities of the device.
On the output side of the TAS5756M device, the summation of the devices can be done before the filter in a
configuration called Pre-Filter Parallel Bridge Tied Load (PBTL). However, it is sometimes preferable to merge
the two outputs together after the inductor portion of the output filter. Doing so does require two additional
inductors, but allows smaller, less expensive inductors to be used because the current is divided between the
two inductors. This is called Post-Filter PBTL. Both variants of mono operation are shown in Figure 77 and
Figure 78.
[
CL[Ç
[
{tY_hÜÇ!+
CL[Ç
{tY_hÜÇ!+
/
CL[Ç
/
CL[Ç
{tY_hÜÇ!-
[
CL[Ç
{tY_hÜÇ!-
/
CL[Ç
{tY_hÜÇ.+
/
CL[Ç
[
CL[Ç
{tY_hÜÇ.-
/
CL[Ç
{tY_hÜÇ.+
[
CL[Ç
[
CL[Ç
{tY_hÜÇ.-
/
CL[Ç
Figure 77. Pre-Filter PBTL
Figure 78. Post-Filter PBTL
On the input side of the TAS5756M device, the input signal to the mono amplifier can be selected from the any
slot in a TDM stream or the left or right frame from an I2S, LJ, or RJ signal. It can also be configured to amplify
some mixture of two signals, as in the case of a subwoofer channel which mixes the left and right channel
together and sends it through a low-pass filter to create a mono, low-frequency signal.
This mode of operation is shown in the Mono (PBTL) Systems section.
8.4.4.3 Bi-Amp Mode
Bi-Amp mode, sometimes also referred to as 1.1 Mode uses a two channel device (such as the TAS5756M
device ) to amplify two different frequency regions of the same signal for a two-way speaker. This is most often
used in a single active speaker, where one channel of the amplifier is use to drive the high frequency transducer
and one channel is used to drive the low-frequency transducer. To operate in Bi-Amped Mode or 1.1 Mode, an
appropriate HybridFlow must be selected, because the frequency separation and audio processing must occur in
the DSP. This mode of operation is shown in the 1.1 (Dual BTL, Bi-Amped) Systems section.
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Device Functional Modes (continued)
8.4.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port
The digital audio serial port in the TAS5756M device can be configured to receive its clocks from another device
as a serial audio slave device. This mode of operation is described in the Clock Slave Mode with SLCK PLL to
Generate Internal Clocks (3-Wire PCM) section. If there no system processor available to provide the audio
clocks, the TAS5756M device can be placed into Master Mode. In this mode, the TAS5756M device provides the
clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation
within the TAS5756M device, see the Serial Audio Port Operating Modes section.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
One of the most significant benefits of the TAS5756M device is the ability to be used in a variety of applications
and with an assortment of signal processing options. This section details the information required to configure the
device for several popular configurations and provides guidance on integrating the TAS5756M device into the
larger system.
9.1.1 External Component Selection Criteria
The Supporting Component Requirements table in each application description section lists the details of the
supporting required components in each of the System Application Schematics.
Where possible, the supporting component requirements have been consolidated to minimize the number of
unique components which are used in the design. Component list consolidation is a method to reduce the
number of unique part numbers in a design, to ease inventory management, and reduce the manufacturing steps
during board assembly. For this reason, some capacitors are specified at a higher voltage than what would
normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply
net.
In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of
that value into a single component type. Similarly, a several unique resistors, having all the same size and value
but with different power ratings can be consolidated by using the highest rated power resistor for each instance
of that resistor value.
While this consolidation may seem excessive, the benefits of having fewer components in the design may far
outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere
in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the
capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of
the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.
9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
Because the layout is important to the overall performance of the circuit, the package size of the components
shown in the component list were intentionally chosen to allow for proper board layout, component placement,
and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane
extends from the TAS5756M device between two pads of a surface mount component and into to the
surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or
larger package sizes, it is highly recommended that the package size remain identical to that used in the
application circuit as shown. This consistency ensures that the layout and routing can be matched very closely,
optimizing thermal, electromagnetic, and audio performance of the TAS5756M device in circuit in the final
system.
9.1.3 Amplifier Output Filtering
The TAS5756M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
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Application Information (continued)
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are
commonly used. In other high-power applications, large toroid inductors are required for maximum power and
film capacitors may be preferred due to audio characteristics. Refer to the application report SLOA119 for a
detailed description on proper component selection and design of an L-C filter based upon the desired load and
response.
9.1.4 Programming the TAS5756M
The device includes an I2C compatible control port to configure the internal registers of the TAS5756M. The
Control Console software provided by TI is required to configure the device for operation with the various
HybridFlows. More details regarding programming steps, and a few important notes are available below and also
in the design examples that follow.
9.1.4.1 Resetting the TAS5756M registers and modules
The TAS5756M device has several methods by which it can reset the register, interpolation filters, and DAC
modules. The registers offer the flexibility to do these in or out of shutdown as well as in or out of standby.
However, there can be issues if the reset bits are toggled in certain illegal operation modes.
Any of the following routines can be used with no issue:
•
•
•
•
•
•
•
Reset Routine 1
–
–
Place device in Standby
Reset modules
Reset Routine 2
–
–
Place device in Standby + Power Down
Reset registers
Reset Routine 3
–
–
Place device in Power Down
Reset registers
Reset Routine 4
–
–
Place device in Standby
Reset registers
Reset Routine 5
–
–
Place device in Standby + Power Down
Reset modules + Reset registers
Reset Routine 6
–
–
Place device in Power Down
Reset modules + Reset registers
Reset Routine 7
–
–
Place device in Standby
Reset modules + Reset registers
There are two reset routines which are not support and should be avoided. If used, they can cause the device to
become unresponsive. These unsupported routines are shown below.
•
Unsupported Reset Routine 1 (do not use)
–
–
Place device in Standby + Power Down
Reset modules
•
Unsupported Reset Routine 2 (do not use)
–
–
Place device in Power Down
Reset modules
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Application Information (continued)
9.1.4.2 Adaptive Mode and using CRAM buffers
The TAS5756M device has the ability to operate in a mode called "adaptive mode". In this mode, coefficients
used the configuration of DSP blocks can be switched "on-the-fly", which means changed while the DSP is
running and not muted or placed into shutdown. When adaptive buffering is enabled the configuration file
generated by the Control Console software will initialize the coefficients in buffer A and the coefficients in buffer
B with identical values. For example, if there is a mixing component in the HybridFlow which has been enabled to
change while the DSP is running, the coefficient corresponding to the mixer coefficient is presented in both
coefficient buffer A and B when the user clicks on the "run" button in the GUI. If the coefficient is to be changed
"on-the-fly", there is a bit called "Switch Active CRAM" at location P44-R1-B0 that instructs the miniDSP to swap
buffers A and B when this bit is set. When the user needs to change the value of the coefficient stored in the
CRAM buffer, the host processor should do the following:
1. Write the new value of the coefficient to buffer A
2. Set the buffer-swap bit (P44-R1-B0).
3. Check the state of the Active CRAM Selection bit (P44-R1-B2) to ensure that the proper CRAM buffer is
being used.
4. Write the new value of the unused buffer to make sure that both buffers remain in sync.
5. Repeat, if necessary, for each subsequent changing of this coefficient, switching between buffer A and buffer
B.
At the end of each frame, the miniDSP sees if this bit is set. If it is, it swaps the buffer from A to B or vice versa.
At the same time, it clears the bit that was set by host.
9.2 Typical Applications
9.2.1 2.0 (Stereo BTL) System
For the stereo (BTL) PCB layout, see Figure 86.
A 2.0 system generally refers to a system in which there are two full range speakers without a separate amplifier
path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to
the amplifier via the digital input signal. These two channels are amplified and then sent to two separate
speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover
network after the L-C filter. Even so, the application is considered 2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
It is important to note that the HybridFlows which have been developed for specifically for stereo applications will
frequently apply the same equalizer curves to the left channel and the right channel. This maximizes the
processing capabilities of each HybridFlow by minimizing the cycles required by the BiQuad filters.
When two signals that are not two separate signals, but instead are derived from a single signal which is
separated into low frequency and high frequency by the signal processor, the application is commonly referred to
as 1.1 or Bi-Amped systems. Figure 79 shows the 2.0 (Stereo BTL) system application.
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PVDD
R100
750k
R101
150k
C103
1µF
C100
0.1µF
C101
22µF
C102
22µF
GND
GND
GND
GND
GND
C104
To System Processor
0.22µF
3.3V
L100
L101
2.0-SDA
2.0-SCL
2.0-SPK_OUTA+
2.0-GPIO0
2.0-GPIO1
2.0-SDOUT
2.0-MCLK
2.0-SCLK
2.0-SDIN
2.0-OUTA+
2.0-OUTA-
C105
1µF
C106
2.2µF
C107
2.2µF
2.0-SPK_OUTA-
C108
3.3V
C109
0.68µF
C110
0.68µF
0.22µF
GND
U100
TAS5754MDCA
TAS5756MDCA
GND
GND
PAD
GND
C111
2.0-LRCK/FS
0.22µF
L102
L103
GND
GND
GND
GND
GND
2.0-SPK_OUTB-
2.0-OUTB-
2.0-OUTB+
C112
1µF
C113
2.2µF
C114
2.2µF
3.3V
2.0-SPK_OUTB+
C115
C116
0.68µF
C117
0.68µF
C118
1µF
C119
1µF
C120
1µF
GND
0.22µF
PVDD
GND
GND
2.0-SPK_MUTE
2.0-SPK_FAULT
GND
GND
GND
C121
0.1µF
C122
22µF
C123
22µF
GND
GND
GND
Figure 79. 2.0 (Stereo BTL) System Application Schematic
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9.2.1.1 Design Requirements
•
Power supplies:
–
–
3.3-V supply
5-V to 24-V supply
Communication: host processor serving as I2C compliant master
•
•
External memory (such as EEPROM and flash) used for coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5756M device in a Stereo 2.0 (BTL) system is
provided in Table 22.
Table 22. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
U100
TAS5756M
48 Pin TSSOP
0402
R100
R101
See Adjustable
Amplifier Gain and
Switching Frequency
Selection section
1%, 0.063 W
0402
1%, 0.063 W
L100, L101, L102,
L103
See Amplifier Output Filtering section
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C100, C121
0.1 µF
0.22 µF
0.68 µF
0402
0603
C104, C108, C111,
C115
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C109, C110, C116,
C117
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
0805
0603
(this body size
chosen to aid in trace Voltage rating must be > 16 V
routing)
Ceramic, 1 µF, ±10%, X7R
C103
1 µF
1 µF
C105, C118, C119,
C120
0402
Ceramic, 1 µF, 6.3V, ±10%, X5R
Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher
voltage caps have been shown to have better stability under DC
bias please follow the guidance provided in the
TAS5756MDCAEVM for suggested values.
C106, C107, C113,
C114
2.2 µF
22 µF
0402
0805
C101, C102, C122,
C123
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
–
The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are
given precedent as design trade-offs are made is recommended.
–
For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
•
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.
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9.2.1.2.3 Step Three: Software Integration
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
•
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.1.3 Application Curves
Table 23 shows the application specific performance plots for Stereo 2.0 (BTL) systems.
Table 23. Relevant Performance Plots
PLOT TITLE
FIGURE NUMBER
Output Power vs PVDD
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 38
Figure 39
Figure 40
Figure 41
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
Efficiency vs Output Power
Idle Current Draw (Filterless) vs PVDD
Idle Current Draw (Traditional LC Filter) vs PVDD
DVDD PSRR vs. Frequency
AVDD PSRR vs. Frequency
CPVDD PSRR vs. Frequency
Powerdown Current Draw vs. PVDD
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9.2.2 Mono (PBTL) Systems
For the mono (PBTL) PCB layout, see Figure 88.
A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge
Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the
loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5756M
device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the
amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while
the on-resistance is approximately halved.
The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an
audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed
together and sent through a low-pass filter to create a single audio signal which contains the low frequency
information of the two channels. Conversely, advanced digital signal processing can create a low-frequency
signal for a multichannel system, with audio processing which is specifically targeted on low-frequency effects.
Although any of the HybridFlows can be made to work with a mono speaker, it is strongly recommended that
HybridFlows which have been created specifically for mono applications be used. These HybridFlows contain the
mixing and filtering required to generate the mono signal. They also include processing which is targeted at
improving the low-frequency performance of an audio system- a feature that, while targeted at subwoofers, can
also be used to enhance the low-frequency performance of a full-range speaker.
Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency
signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate
channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL
configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo
BTL + External Mono Amplifier) Systems section.
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PVDD
R200
750k
R201
150k
C204
390µF
C200
1µF
C201
0.1µF
C202
1µF
C203
22µF
GND
GND
GND
GND
GND
GND
To System Processor
3.3V
MONO-SDA
MONO-SCL
C208
MONO-GPIO0
MONO-GPIO1
MONO-SDOUT
MONO-MCLK
MONO-SCLK
MONO-SDIN
0.22µF
L200
C205
1µF
C206
2.2µF
C207
2.2µF
MONO-SPK_OUTA
C209
MONO_OUT+
C220
0.68µF
0.22µF
GND
U200
TAS5754MDCA
TAS5756MDCA
GND
PAD
GND
C214
MONO-LRCK/FS
0.22µF
L201
GND
GND
GND
GND
GND
MONO-SPK_OUTB
C215
MONO_OUT-
C210
1µF
R202
49.9k
C221
0.68µF
3.3V
0.22µF PVDD
C211
1µF
C212
1µF
C213
1µF
GND
C219
390µF
C216
0.1µF
C217
1µF
C218
22µF
MONO-SPK_MUTE
MONO-SPK_FAULT
GND
GND
GND
GND
GND
GND
GND
Figure 80. Mono (PBTL) System Application Schematic
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9.2.2.1 Design Requirements
•
Power supplies:
–
–
3.3-V supply
5-V to 24-V supply
Communication: Host processor serving as I2C compliant master
•
•
External memory (EEPROM, flash, and others) used for coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5756M device in a Mono (PBTL) system is provided
in Table 24.
Table 24. Supporting Component Requirements for Mono (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
U200
TAS5756M
48 Pin TSSOP
R200
See Adjustable
Amplifier Gain and
Switching Frequency
Selection section
0402
0402
0402
1%, 0.063 W
1%, 0.063 W
1%, 0.063 W
R201
R202
L200, L201
See Amplifier Output Filtering section
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C216, C201
0.1 µF
0.22 µF
0.68 µF
0402
0603
C208, C209, C214,
C215
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C220, C221
0805
0603
(this body size
chosen to aid in trace Voltage rating must be > 16 V
routing)
Ceramic, 1 µF, ±10%, X7R
C200
1 µF
1 µF
1 µF
C205, C211, C213,
C212
0402
Ceramic, 1 µF, 6.3 V, ±10%, X5R
0805
(this body size
C202, C217, C352,
C367
Ceramic, 1 µF, ±10%, X5R
chosen to aid in trace Voltage rating must be > 1.45 × VPVDD
routing)
Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher
C206, C207
C203, C218
2.2 µF
0402
voltage caps have been shown to have better stability under DC
bias please follow the guidance provided in the
TAS5756MDCAEVM for suggested values.
22 µF
0805
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
390 µF
10 × 10
Aluminum, 390 µF, ±20%, 0.08-Ω
Voltage rating must be > 1.45 × VPVDD Anticipating that this
application circuit would be followed for higher power subwoofer
applications, these capacitors are added to provide local current
sources for low-frequency content. These capacitors can be
reduced or even removed based upon final system testing, including
critical listening tests when evaluating low-frequency designs.
C204, C219
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
–
The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are
given precedent as design trade-offs are made is recommended.
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–
For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
•
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.
9.2.2.2.3 Step Three: Software Integration
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
•
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
Table 25. Relevant Performance Plots
PLOT TITLE
Output Power vs PVDD
FIGURE NUMBER
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 57
Figure 58
Figure 53
Figure 54
Figure 55
Figure 56
Figure 59
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
Efficiency vs Output Power
Idle Current Draw (filterless) vs PVDD
Idle Current Draw (traditional LC filter) vs PVDD
PVDD PSRR vs Frequency
DVDD PSRR vs. Frequency
AVDD PSRR vs. Frequency
CPVDD PSRR vs. Frequency
Powerdown Current Draw vs. PVDD
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9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
Figure 90 shows the PCB Layout for the 2.1 System.
To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the
system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the
subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other
channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is
referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a
popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.
9.2.3.1 Basic 2.1 System (TAS5756M Device + Simple Digital Input Amplifier)
In the most basic 2.1 system, a subwoofer is added to a stereo left and right pair of speakers as discussed
above. The audio amplifiers include one TAS5756M device for the high frequency channels and one simple
digital input device without integrated audio processing for the subwoofer channel. A member of the popular
TAS5760xx family of devices is a popular choice for the subwoofer amplifier. In this system, the subwoofer
content is generated by summing the two channels of audio and sending them through a high-pass filter to filter
out the high frequency content. This is then sent to the SDIN pin of the subwoofer amplifier, which is operating in
PBTL, via the SDOUT line of the TAS5756M device . In the basic 2.1 system, only HybridFlows which included
subwoofer signal generation can be used, because the subwoofer amplifier depends on the TAS5756M device to
create its stereo low-frequency input signal.
9.2.3.2 Advanced 2.1 System (Two TAS5756M devices)
In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was
done in the high-frequency channels. To accomplish this, two TAS5756M devices are used- one for the high
frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can
be sent from the TAS5756M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept
the same digital input as the stereo, which might come from a central systems processor. In advanced 2.1
systems, any HybridFlow can be used for the subwoofer, provided the sample rates for the two are the same.
While any of the HybridFlows can be used, it is highly recommended that only mono HybridFlows are used for
the subwoofer. Doing so streamlines development time and effort by minimizing confusion and complexity.
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PVDD
R300
750k
R301
150k
C303
1µF
C300
0.1µF
C301
22µF
C302
22µF
GND
GND
GND
GND
GND
C304
To System Processor
3.3V
0.22µF
L300
L301
2.1-SDA
2.1-SCL
2.1-SPK_OUT1A+
2.1-GPIO0_HF
2.1-GPIO1_HF
2.1-HF_OUTA+
2.1-HF_OUTA-
C305
1µF
C306
2.2µF
C307
2.2µF
2.1-MCLK
2.1-SCLK
2.1-SDIN
3.3V
2.1-SPK_OUT1A-
C308
C309
0.68µF
C310
0.68µF
0.22µF
GND
U300
TAS5754MDCA
TAS5756MDCA
GND
GND
PAD
GND
C311
2.1-LRCK/FS
0.22µF
L302
GND
GND
GND
GND
GND
2.1-SPK_OUT1B-
2.1-HF_OUTB-
L303
C312
1µF
C313
2.2µF
C314
2.2µF
3.3V
2.1-SPK_OUT1B+
C315
2.1-HF_OUTB+
C316
0.68µF
C317
0.68µF
C318
1µF
C319
1µF
C320
1µF
GND
PVDD
0.22µF
GND
GND
2.1-SPK_MUTE
2.1-SPK_FAULT
GND
GND
GND
C321
0.1µF
C322
22µF
C323
22µF
GND
GND
GND
PVDD
R350
750k
R351
150k
C354
390µF
C350
1µF
C351
0.1µF
C352
1µF
C353
22µF
GND
GND
GND
GND
GND
GND
3.3V
C358
2.1-GPIO0_LF
2.1-GPIO1
2.1-SDOUT_LF
0.22µF
L350
C355
1µF
C356
2.2µF
C357
2.2µF
2.1-SPK_OUT2A
C359
2.1_LF+
C370
0.68µF
0.22µF
GND
U301
TAS5754MDCA
TAS5756MDCA
GND
PAD
GND
C364
0.22µF
2.1-SPK_OUT2B
C365
L351
GND
GND
GND
GND
GND
2.1_LF-
C360
1µF
R352
49.9k
C371
0.68µF
3.3V
0.22µF PVDD
C361
1µF
C362
1µF
C363
1µF
GND
C369
390µF
C366
0.1µF
C367
1µF
C368
22µF
GND
GND
GND
GND
GND
GND
GND
Figure 81. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic
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9.2.3.3 Design Requirements
•
Power supplies:
–
–
3.3-V supply
5-V to 24-V supply
Communication: Host processor serving as I2C compliant master
•
•
External memory (EEPROM, flash, and others) used for coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5756M device in a 2.1 (Stereo BTL + External Mono
Amplifier) system is provided in Table 26.
Table 26. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
U300
TAS5756M
48 Pin TSSOP
R300, R350
R301, R351
R352
See Adjustable
Amplifier Gain and
Switching Frequency
Selection section
0402
0402
0402
1%, 0.063 W
1%, 0.063 W
1%, 0.063 W
L300, L301, L302,
L303
See Amplifier Output Filtering section
L350, L351
C394, C395, C396,
C397, C398, C399
0.01 µF
0.1 µF
0603
0402
Ceramic, 0.01 µF, 50 V, +/-10%, X7R
C300, C321, C351,
C366
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C304, C308, C311,
C315, C358, C359,
C364, C365
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
0.22 µF
0603
C309, C310, C316,
C317, C370, C371
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
0.68 µF
1 µF
0805
0603
C303, C350, C312,
C360
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C305, C318, C319,
C320, C355, C361,
C363, C312, C362
1 µF
0402
Ceramic, 1 µF, 6.3V, ±10%, X5R
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C352, C367
1 µF
2.2 µF
22 µF
390 µF
0805
0402
C306, C307, C313,
C314, C356, C357,
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C301, C302, C322,
C323, C353, C368
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
0805
Aluminum, 390 µF, ±20%, 0.08 Ω
Voltage rating must be > 1.45 × VPVDD
C354, C369
10 × 10
9.2.3.4 Detailed Design Procedure
9.2.3.4.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
–
The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are
given precedent as design trade-offs are made is recommended.
–
For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
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9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
•
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.
9.2.3.4.3 Step Three: Software Integration
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
•
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
Table 27. Relevant Performance Plots
DEVICE
PLOT TITLE
FIGURE NUMBER
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 58
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 57
Figure 58
Figure 53
Figure 38
Figure 39
Figure 40
Figure 41
Output Power vs PVDD
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
U300
Efficiency vs Output Power
Idle Current Draw (Filterless) vs PVDD
Idle Current Draw (Traditional LC Filter) vs PVDD
Output Power vs PVDD
THD+N vs Frequency, VPVDD = 12 V
THD+N vs Frequency, VPVDD = 15 V
THD+N vs Frequency, VPVDD = 18 V
THD+N vs Frequency, VPVDD = 24 V
THD+N vs Power, VPVDD = 12 V
THD+N vs Power, VPVDD = 15 V
THD+N vs Power, VPVDD = 18 V
THD+N vs Power, VPVDD = 24 V
Idle Channel Noise vs PVDD
U301
Efficiency vs Output Power
Idle Current Draw (filterless) vs PVDD
Idle Current Draw (traditional LC filter) vs PVDD
PVDD PSRR vs Frequency
DVDD PSRR vs. Frequency
U300
and
U301
AVDD PSRR vs. Frequency
CPVDD PSRR vs. Frequency
Powerdown Current Draw vs. PVDD
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9.2.4 2.2 (Dual Stereo BTL) Systems
For the 2.2 (Dual Stereo BTL) PCB layout, see Figure 92.
A 2.2 system consists of a stereo pair of loudspeakers with a pair of low frequency loudspeakers. In some cases,
this is implemented as two stereo full-range speakers and two subwoofers. In others, it is implemented as two
high frequency speakers and two mid-range speakers.
As in the case of the 2.1 system, the 2.2 system can be created by using the audio processing inside of the
TAS5756M device and creating a subwoofer signal which is sent to a simple digital input amplifier like one of the
TAS5760xx devices (or similar). This requires that a HybridFlow that contains a subwoofer generation processing
block be used in the TAS5756M device. This signal is created by summing the left and right channel, filtering
with a high-pass filter and sending it to the subwoofer amplifier. For this type of system, the TAS5756M device
used for the high-frequency drivers must have a subwoofer generation processing block to provide the
appropriate signal to the subwoofer amplifiers.
Alternatively, the low-frequency drivers can be driven by using two TAS5756M devices; each receiving their input
from a central systems processor. This type of implementation allows for any stereo HybridFlow to be used for
both the low-frequency and high-frequency drivers, increasing the processing options available for the system.
This expands the processing capabilities of the system, introducing digital signal processing to the low-frequency
drivers as well as the high-frequency drivers. This type of 2.2 system is described in Figure 82.
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PVDD
R400
750k
R401
150k
C403
1µF
C400
0.1µF
C401
22µF
C402
22µF
GND
GND
GND
GND
GND
To System Processor
C404
3.3V
0.22µF
L400
L401
2.2-SDA
2.2-SCL
2.2-SPK_OUT1A+
2.2-GPIO0_HF
2.2-GPIO1_HF
2.2-HF_OUTA+
2.2-HF_OUTA-
C405
1µF
C406
2.2µF
C407
2.2µF
2.2-MCLK
2.2-SCLK
2.2-SDIN
3.3V
2.2-SPK_OUT1A-
C408
C409
0.68µF
C410
0.68µF
0.22µF
GND
U400
TAS5754MDCA
TAS5756MDCA
GND
GND
PAD
GND
C411
2.2-LRCK/FS
0.22µF
L402
L403
GND
GND
GND
GND
GND
2.2-SPK_OUT1B-
2.2-HF_OUTB-
C412
1µF
C413
2.2µF
C414
2.2µF
3.3V
2.2-SPK_OUT1B+
C415
2.2-HF_OUTB+
C416
0.68µF
C417
0.68µF
C418
1µF
C419
1µF
C420
1µF
GND
PVDD
0.22µF
GND
GND
2.2-SPK_MUTE
2.2-SPK_FAULT
GND
GND
GND
C421
0.1µF
C422
22µF
C423
22µF
GND
GND
GND
PVDD
R450
750k
R451
150k
C453
1µF
C450
0.1µF
C451
22µF
C452
22µF
GND
GND
GND
GND
GND
C454
3.3V
0.22µF
L450
L451
2.2-SPK_OUT2A+
2.2-GPIO0_LF
2.2-GPIO1_LF
2.2-SDOUT_LF
2.2-LF_OUTA+
C455
1µF
C456
2.2µF
C457
2.2µF
3.3V
2.2-SPK_OUT2A-
C458
2.2-LF_OUTA-
C459
0.68µF
C460
0.68µF
0.22µF
GND
U401
TAS5754MDCA
TAS5756MDCA
GND
GND
PAD
GND
C461
0.22µF
L452
L453
GND
GND
GND
GND
GND
2.2-SPK_OUT2B-
2.2-LF_OUTB-
C462
1µF
C463
2.2µF
C464
2.2µF
3.3V
2.2-SPK_OUT2B+
C465
2.2-LF_OUTB+
C466
0.68µF
C467
0.68µF
C468
1µF
C469
1µF
C470
1µF
GND
PVDD
0.22µF
GND
GND
GND
GND
GND
C471
0.1µF
C472
22µF
C473
22µF
GND
GND
GND
Figure 82. 2.2 (Dual Stereo BTL) Application Schematic
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9.2.4.1 Design Requirements
•
Power Supplies:
–
–
3.3-V Supply
5-V to 24-V Supply
Communication: Host Processor serving as I2C Compliant Master
•
•
External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5756M device in a 2.2 (Dual Stereo BTL) System is
provided in Figure 92.
Table 28. Supporting Component Requirements for 2.2 (Dual Stereo BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
Digital Input, Closed-Loop Class-
D Amplifier with HybridFlow
Processing
U400, U401
TAS5756M device
48-pin TSSOP
R400, R450
R401, R451
See Figure 83
See Figure 83
0402
0402
1%, 0.063 W
1%, 0.063 W
L400, L401, L402, L403, L450,
L451, L452, L453
See the Amplifier Output Filtering section
C492, C493, C494, C495, C496,
C497, C498, C499
Ceramic, 0.01 µF, 50 V, ±10%,
X7R
0.01 µF
0.1 µF
0603
0402
C400, C421, C450, C471
Ceramic, 0.1 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
C404, C408, C411, C415, C454,
C458, C461, C465
Ceramic, 0.22 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
0.22 µF
0.68 µF
0603
0805
C409, C410, C416, C417, C459,
C460, C466, C467
Ceramic, 0.68 µF, ±10%, X7R,
Voltage rating must be > 1.8 ×
VPVDD
C403, C453, C462
Ceramic, 1 µF, ±10%, X7R,
Voltage rating must be > 1.45 ×
VPVDD
1 µF
1 µF
0603
0402
0402
C405, C418, C419, C420, C455,
C468, C469, C470, C412, C462
Ceramic, 1 µF, 6.3V, ±10%, X5R
C406, C407, C413, C414, C456,
C457, C463, C464
Ceramic, 2.2 µF, ±10%, X5R,
Voltage rating must be > 1.45 ×
VPVDD
2.2 µF
C401, C402, C422, C423, C451,
C452, C472, C473
Ceramic, 22 µF, ±20%, X5R,
Voltage rating must be > 1.45 ×
VPVDD
22 µF
0805
9.2.4.2 Detailed Design Procedure
9.2.4.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
–
The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are
given precedent as design trade-offs are made is recommended.
–
For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
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•
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.
9.2.4.2.3 Step Three: Software Integration
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
•
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
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9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems
Table 29. Relevant Performance Plots
PLOT TITLE
Figure 23. Output Power vs PVDD
PLOT NUMBER
C036
C034
C002
C037
C003
C035
C004
C038
C005
C006
C007
C013
C015
C028
C029
C030
C032
Figure 24. THD+N vs Frequency, VPVDD = 12 V
Figure 25. THD+N vs Frequency, VPVDD = 15 V
Figure 26. THD+N vs Frequency, VPVDD = 18 V
Figure 27. THD+N vs Frequency, VPVDD = 24 V
Figure 28. THD+N vs Power, VPVDD = 12 V
Figure 29. THD+N vs Power, VPVDD = 15 V
Figure 30. THD+N vs Power, VPVDD = 18 V
Figure 31. THD+N vs Power, VPVDD = 24 V
Figure 32. Idle Channel Noise vs PVDD
Figure 33. Efficiency vs Output Power
Figure 34. Idle Current Draw (Filterless) vs PVDD
Figure 35. Idle Current Draw (Traditional LC Filter) vs PVDD
Figure 38. DVDD PSRR vs. Frequency
Figure 39. AVDD PSRR vs. Frequency
Figure 40. CPVDD PSRR vs. Frequency
Figure 41. Powerdown Current Draw vs. PVDD
9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
The 1.1 use case is a special application of the 2.0 stereo BTL system. In this system, two channels of an
amplifier are used to reproduce a single channel of an audio signal that has been separated based on frequency.
This configuration removes the need for passive cross-over elements inside of a loudspeaker, because the signal
is separated into a low-frequency and a high-frequency component before it is amplified. Systems which operate
in this configuration, in which separate amplifier channels drive the low and high-frequency loudspeakers directly,
are often called “bi-amped” systems.
Popular applications for this configuration include:
•
•
•
•
Powered near-field monitors
Blue-tooth Speakers
Co-axial Loudspeakers
Surround/Fill Speakers for multi-channel audio
From a hardware perspective, the TAS5756M device is configured in the same way as the Stereo BTL system.
However, special HybridFlows which support 1.1 operation must be used, because HybridFlows that are
designed for stereo applications frequently apply the same equalizer curves to the left and the right hand
channel. Additionally, many 1.1 HybridFlows include a delay element which can improve time alignment between
two loudspeakers that are mounted on the same baffle some distance apart.
For the 1.1 (Dual BTL, Bi-Amped) PCB layout, see Figure 94.
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PVDD
R500
750k
R501
150k
C503
1µF
C500
0.1µF
C501
22µF
C502
22µF
GND
GND
GND
GND
GND
C504
To System Processor
0.22µF
3.3V
L500
1.1-SDA
1.1-SCL
1.1-SPK_OUTA+
1.1-GPIO0
1.1-GPIO1
1.1-SDOUT
1.1-MCLK
1.1-SCLK
1.1-SDIN
1.1_LF+
1.1_LF-
L501
C505
1µF
C506
2.2µF
C507
2.2µF
1.1-SPK_OUTA-
C508
3.3V
C509
0.68µF
C510
0.22µF
GND
U500
TAS5754MDCA
TAS5756MDCA
GND
GND
PAD
GND
C511
1.1-LRCK/FS
0.22µF
L502
L503
GND
GND
GND
GND
GND
1.1-SPK_OUTB-
1.1_HF-
1.1_HF+
C512
1µF
C513
2.2µF
C514
2.2µF
3.3V
1.1-SPK_OUTB+
C515
C516
0.68µF
C517
0.68µF
C518
1µF
C519
1µF
C520
1µF
GND
0.22µF
PVDD
GND
GND
1.1-SPK_MUTE
1.1-SPK_FAULT
GND
GND
GND
C521
0.1µF
C522
22µF
C523
22µF
GND
GND
GND
Figure 83. 1.1 (Dual BTL, Bi-Amped) Application Schematic
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9.2.5.1 Design Requirements
•
Power Supplies:
–
DVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions
table.
–
PVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions
table.
•
•
Communication: Host Processor serving as I2C Compliant Master
External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB
The requirements for the supporting components for the TAS5756M device in a Dual BTL, Bi-Amped System is
provided in Figure 94.
Table 30. Supporting Component Requirements for 1.1 (Dual BTL, Bi-Amped) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
Digital-input, closed-loop class-D amplifier with HybridFlow
processing
U500
TAS5756M
48 Pin TSSOP
0402
R500
R501
See Adjustable
Amplifier Gain and
Switching Frequency
Selection section
1%, 0.063 W
0402
1%, 0.063 W
L500, L501, L502,
L503
See Amplifier Output Filtering section
C596, C597, C598,
C599
0.01 µF
0.1 µF
0.22 µF
0.68 µF
1 µF
0603
0402
0603
0805
0603
0402
Ceramic, 0.01 µF, 50 V, ±10%, X7R
Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C500, C521
C504, C508, C511,
C515
Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C509, C510, C516,
C517
Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C503
C505, C518, C519,
C520, C512
1 µF
Ceramic, 1 µF, 6.3V, ±10%, X5R
C506, C507, C513,
C514
Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
2.2 µF
22 µF
0402
805
C501, C502, C522,
C523
Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
9.2.5.2 Detailed Design Procedure
9.2.5.2.1 Step One: Hardware Integration
•
•
Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
Following the recommended component placement, board layout and routing give in the example layout
above, integrate the device and its supporting components into the system PCB file.
–
The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the
high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are
given precedent as design trade-offs are made is recommended.
–
For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning
•
Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to
select the HybridFlow that meets the needs of the target application.
•
Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the
appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.
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9.2.5.2.3 Step Three: Software Integration
•
•
Use the Register Dump feature of the PPC software to generate a baseline configuration file.
Generate additional configuration files based upon operating modes of the end-equipment and integrate static
configuration information into initialization files.
•
Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems
Table 31. Relevant Performance Plots
PLOT TITLE
Figure 23. Output Power vs PVDD
PLOT NUMBER
C036
Figure 24. THD+N vs Frequency, VPVDD = 12 V
Figure 25. THD+N vs Frequency, VPVDD = 15 V
Figure 26. THD+N vs Frequency, VPVDD = 18 V
Figure 27. THD+N vs Frequency, VPVDD = 24 V
Figure 28. THD+N vs Power, VPVDD = 12 V
Figure 29. THD+N vs Power, VPVDD = 15 V
Figure 30. THD+N vs Power, VPVDD = 18 V
Figure 31. THD+N vs Power, VPVDD = 24 V
Figure 32. Idle Channel Noise vs PVDD
C034
C002
C037
C003
C035
C004
C038
C005
C006
Figure 33. Efficiency vs Output Power
C007
Figure 34. Idle Current Draw (Filterless) vs PVDD
Figure 35. Idle Current Draw (Traditional LC Filter) vs PVDD
Figure 38. DVDD PSRR vs. Frequency
C013
C015
C028
Figure 39. AVDD PSRR vs. Frequency
C029
Figure 40. CPVDD PSRR vs. Frequency
C030
Figure 41. Powerdown Current Draw vs. PVDD
C032
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10 Power Supply Recommendations
10.1 Power Supplies
The TAS5756M device requires two power supplies for proper operation. A high-voltage supply called PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-
voltage power supply called DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating
Conditions table.
AVDD
Internal Analog Circuitry
Internal Mixed
Signal Circuitry
Internal Digital
Circuitry
+
DVDD
DVDD
DVDD_REG
External Filtering/Decoupling
œ
LDO
CPVDD
CPVSS
External Filtering/Decoupling
Charge
Pump
DAC Output Stage
(Positive)
DAC Output Stage
(Negative)
Output Stage
Power Supply
Gate Drive
Voltage
PVDD
GVDD_REG
External Filtering/Decoupling
Linear
Regulator
+
PVDD
œ
Figure 84. Power Supply Functional Block Diagram
10.1.1 DVDD Supply
The DVDD supply required from the system is used to power several portions of the device. As shown in the
Figure 84, it provides power to the DVDD pin, the CPVDD pin, and the AVDD pin. Proper connection, routing,
and decoupling techniques are highlighted in the TAS5756M device EVM User's Guide SLAU583 (as well as the
Application and Implementation section and Layout Example section) and must be followed as closely as
possible for proper operation and performance. Deviation from the guidance offered in the TAS5756M device
EVM User's Guide, which followed the same techniques as those shown in the Application and Implementation
section, may result in reduced performance, errant functionality, or even damage to the TAS5756M device.
Some portions of the device also require a separate power supply which is a lower voltage than the DVDD
supply. To simplify the power supply requirements for the system, the TAS5756M device includes an integrated
low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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Power Supplies (continued)
The outputs of the high-performance DACs used in the TAS5756M device are ground centered, requiring both a
positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output
stage is taken from the AVDD pin, which is connected to the DVDD supply provided by the system. A charge
pump is integrated in the TAS5756M device to generate the negative low-voltage supply. The power supply input
for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of a filter capacitor
on the negative low-voltage supply. As is the case with the other supplies, the component selection, placement,
and routing of the external components for these low voltage supplies are shown in the TAS5756MDCAEVM and
should be followed as closely as possible to ensure proper operation of the device.
10.1.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TAS5756MDCAEVM and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TAS5756M device EVM User's Guide. Lack of proper
decoupling, like that shown in the EVM User's Guide, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG
pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to
note that the linear regulator integrated in the device has only been designed to support the current requirements
of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on
this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
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11 Layout
11.1 Layout Guidelines
11.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in . These examples represent exemplary baseline
balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly
as needed to meet the needs of a given application. In some applications, for instance, solution size can be
compromised to improve thermal performance through the use of additional contiguous copper near the device.
Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces and
incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start from
the guidance shown in the Layout Example section and the TAS5754M-56MEVM, and work with TI field
application engineers or through the E2E community to modify it based upon the application specific goals.
11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. This
applies to DVDD, AVDD, CPVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5756M
device deserve special attention.
It is imperative that the small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins
as possible. Not only does placing these devices far away from the pins increase the electromagnetic
interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these
components too far from the TAS5756M device may cause ringing on the output pins that can cause the voltage
on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table,
damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their
associated PVDD pins than what is shown in the example layouts in the Layout Example section
11.1.3 Optimizing Thermal Performance
Follow the layout examples shown in the Layout Example section of this document to achieve the best balance
of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance
may be required due to design constraints which cannot be avoided. In these instances, the system designer
should ensure that the heat can get out of the device and into the ambient air surrounding the device.
Fortunately, the heat created in the device would prefer to travel away from the device and into the lower
temperature structures around the device.
11.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
•
Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
•
If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5756M device
and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top
and bottom layer.
•
•
Place the TAS5756M device away from the edge of the PCB when possible to ensure that heat can travel
away from the device on all four sides.
Avoid cutting off the flow of heat from the TAS5756M device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
•
Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5756M
device.
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Layout Guidelines (continued)
•
Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
11.1.3.2 Stencil Pattern
The recommended drawings for the TAS5756M device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system. It is important to note that the customer must verify that deviation from the guidance
shown in the package addendum, including the deviation explained in this section, meets the customer’s quality,
reliability, and manufacturability goals.
11.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the TAS5756M device will be soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5756M
device, be made no smaller than what is specified in the package addendum. This ensures that the TAS5756M
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the
Layout Example section, this interface can benefit from improved thermal performance.
NOTE
Vias can obstruct heat flow if they are not constructed properly.
•
•
Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
•
The drill diameter of 8 mils or less. Also, the distance between the via barrel and the surrounding planes
should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
•
•
Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the Layout Example section.
Ensure that vias do not cut-off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias which are farthest from the TAS5756M device to open up the current
path to and from the device.
11.1.3.2.1.1 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself.
However, the thermal pad on the PCB is quite large and depositing a large, single deposition of solder paste
would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the
solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This
structure is called an aperture array, and is shown in the Layout Example section. It is important that the total
area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the
area of the thermal pad itself.
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11.2 Layout Example
11.2.1 2.0 (Stereo BTL) System
Figure 85. 2.0 (Stereo BTL) 3-D View
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Layout Example (continued)
Figure 86. 2.0 (Stereo BTL) Top Copper View
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Layout Example (continued)
11.2.2 Mono (PBTL) System
Figure 87. Mono (PBTL) 3-D View
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Layout Example (continued)
Figure 88. Mono (PBTL) Top Copper View
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Layout Example (continued)
11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
Figure 89. 2.1 (Stereo BTL + Mono PBTL) 3-D View
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Layout Example (continued)
Figure 90. 2.1 (Stereo BTL + Mono PBTL) Top Copper View
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Layout Example (continued)
11.2.4 2.2 (Dual Stereo BTL) Systems
Figure 91. 2.2 (Dual Stereo BTL) 3-D View
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Layout Example (continued)
Figure 92. 2.2 (Dual Stereo BTL) Top Copper View
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Layout Example (continued)
11.2.5 1.1 (Bi-Amped BTL) Systems
Figure 93. 1.1 (Bi-Amped BTL) 3-D View
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Layout Example (continued)
Figure 94. 2. 1.1 (Bi-Amped BTL) Top Copper View
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which
are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-
bridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the TAS5756M) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
HybridFlow uses components which are built in RAM and components which are built in ROM to make a
configurable device that is easier to use than a fully-programmable device while remaining flexible enough to be
used in several applications
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
12.1.2 Development Support
For the PurePath Console Software, go to www.ti.com/tool/purepathconsole.
See the User Guide, Using the TAS5754/6M HybridFlow Processor (SLAU577) for detailed information regarding
the HybridFlow Processing and available HybridFlows.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
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Community Resources (continued)
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
PurePath, PowerPAD, E2E are trademarks of Texas Instruments.
Burr-Brown is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2015, Texas Instruments Incorporated
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97
Product Folder Links: TAS5756M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5756MDCA
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DCA
DCA
48
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-25 to 85
-25 to 85
TAS5756M
TAS5756M
TAS5756MDCAR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5756MDCAR
HTSSOP DCA
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DCA 48
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TAS5756MDCAR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DCA HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TAS5756MDCA
48
40
530
11.89
3600
4.9
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DCA 48
12.5 x 6.1, 0.5 mm pitch
HTSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224608/A
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