TAS5504APAGG4 [TI]
4-Channel Digital Audio PWM Processor; 4通道数字音频PWM处理器
| 型号： | TAS5504APAGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-Channel Digital Audio PWM Processor |
| 文件： | 总97页 (文件大小：1793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5504A
4-Channel Digital Audio PWM Processor
Data Manual
TM
February 2006
DAV - Digital Audio/Speaker
SLES169
TAS5504A
4-Channel Digital Audio PWM Processor
Data Manual
TM
Literature Number: SLES169
February 2006
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Contents
1
Introduction....................................................................................................................... 11
1.1
1.2
1.3
1.4
TAS5504A Features ....................................................................................................... 11
Overview..................................................................................................................... 12
Changes From the TAS5504 to the TAS5504A........................................................................ 13
Physical Characteristics ................................................................................................... 15
1.4.1
1.4.2
1.4.3
Terminal Assigments............................................................................................ 15
Ordering Information ............................................................................................ 15
TERMINAL FUNCTIONS....................................................................................... 15
1.4.4 TAS5504A Functional Description ....................................................................................... 17
1.4.4.1 Power Supply.................................................................................................... 17
1.4.4.2 Clock, PLL, and Serial Data Interface........................................................................ 18
1.4.4.3 I2C Serial Control Interface .................................................................................... 18
1.4.4.4 Device Control................................................................................................... 19
1.4.4.5 Digital Audio Processor (DAP) ................................................................................ 19
1.4.5 TAS5504A DAP Architecture ............................................................................................. 20
1.4.5.1 TAS5504A DAP Architecture Diagrams...................................................................... 20
1.4.5.2 I2C Coefficient Number Formats.............................................................................. 23
1.4.6 Input Crossbar Mixer....................................................................................................... 26
1.4.7 Biquad Filters ............................................................................................................... 27
1.4.8 Bass and Treble Controls ................................................................................................. 27
1.4.9 Volume, Automute, and Mute............................................................................................. 28
1.4.9.1 Automute and Mute Channel Controls ....................................................................... 29
1.4.10 Loudness Compensation ................................................................................................ 30
1.4.10.1 Loudness Example ............................................................................................ 31
1.4.11 Dynamic Range Control (DRC) ........................................................................................ 31
1.4.11.1 DRC Implementation.......................................................................................... 34
1.4.11.2 Compression/Expansion Coefficient Computation Engine Parameters ................................ 35
1.4.12 Output Mixer............................................................................................................... 37
1.4.13 PWM........................................................................................................................ 38
1.4.13.1 DC Blocking (High-Pass Enable/Disable) .................................................................. 39
1.4.13.2 De-Emphasis Filter ............................................................................................ 39
1.4.13.3 Power-Supply Volume Control (PSVC)..................................................................... 39
1.4.13.4 AM Interference Avoidance .................................................................................. 40
TA5504A Controls and Status .............................................................................................. 41
2
2.1
I2C Status Registers ....................................................................................................... 41
2.1.1
General Status Register (0x01)................................................................................ 41
Error Status Register (0x02) ................................................................................... 41
2.1.2
2.2
TAS5504A Pin Controls ................................................................................................... 42
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Reset (RESET) .................................................................................................. 42
Power Down (PDN) ............................................................................................. 43
Back-End Error (BKND_ERR) ................................................................................. 44
Speaker/Headphone Selector (HP_SEL)..................................................................... 44
Mute (MUTE)..................................................................................................... 45
2.3
Device Configuration Controls............................................................................................ 45
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
Channel Configuration Registers.............................................................................. 45
Headphone Configuration Registers .......................................................................... 46
Audio System Configurations .................................................................................. 46
Recovery from Clock Error ..................................................................................... 47
Power-Supply Volume-Control Enable ....................................................................... 47
Volume and Mute Update Rate................................................................................ 47
Modulation Index Limit.......................................................................................... 47
Contents
3
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
2.4
2.5
Master Clock and Serial Data Rate Controls ........................................................................... 47
PLL Operation.................................................................................................... 48
Bank Controls............................................................................................................... 48
2.4.1
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
Manual Bank Selection ......................................................................................... 48
Automatic Bank Selection ...................................................................................... 49
Bank Set .......................................................................................................... 49
Bank-Switch Timeline ........................................................................................... 49
Bank Switching Example 1..................................................................................... 49
Bank Switching Example 2..................................................................................... 50
3
Electrical Specifications...................................................................................................... 51
3.1
Absolute Maximum Ratings............................................................................................... 51
3.2
Dissipation Rating Table (High-k Board, 105°C Junction) ................................................. 51
Dynamic Performance at Recommended Operating Conditions at 25°C................................ 51
Recommended Operating Conditions ........................................................................ 51
Electrical Characteristics ....................................................................................... 52
PWM Operation.................................................................................................. 52
Switching Characteristics....................................................................................... 52
Clock Signals..................................................................................................... 52
Serial Audio Port................................................................................................. 53
3.3
3.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
TAS5504A Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus
Devices ........................................................................................................... 53
3.7.4
TAS5504A Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus
Devices ........................................................................................................... 54
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
Reset Timing (RESET) ......................................................................................... 56
Power-Down (PDN) Timing .................................................................................... 56
Back-End Error (BKND_ERR) ................................................................................. 57
Mute Timing (MUTE)............................................................................................ 57
Headphone Select (HP_SEL).................................................................................. 58
3.7.10 Volume Control .................................................................................................. 58
3.8
Serial Audio Interface Control and Timing ................................................................... 59
I 2S Timing ........................................................................................................ 59
Left-Justified Timing............................................................................................. 60
Right-Justified Timing ........................................................................................... 61
3.8.1
3.8.2
3.8.3
4
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37).................................................. 61
4.1
4.2
4.3
4.4
4.5
4.6
4.7
General I2C Operation ..................................................................................................... 61
Single- and Multiple-Byte Transfers ..................................................................................... 62
Single-Byte Write........................................................................................................... 63
Multiple-Byte Write ......................................................................................................... 63
Incremental Multiple-Byte Write .......................................................................................... 63
Single-Byte Read........................................................................................................... 64
Multiple-Byte Read......................................................................................................... 64
5
6
Serial Control I2C Register Summary .................................................................................... 65
Serial Control Interface Register Definitions .......................................................................... 69
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Clock Control Register (0x00) ............................................................................................ 69
General Status Register 0 (0x01) ........................................................................................ 69
System Control Register 1 (0x03)........................................................................................ 70
System Control Register 2 (0x04)........................................................................................ 70
Channel Configuration Control Registers (0x05, 0x06, 0x0B, and 0x0C) .......................................... 71
Headphone Configuration Control Register (0x0D) ................................................................... 71
Serial Data Interface Control Register (0x0E).......................................................................... 72
Soft-Mute Register (0x0F)................................................................................................. 72
Automute Control Register (0x14) ....................................................................................... 73
6.10 Automute PWM Threshold and Back-End Reset Period (0x15) ..................................................... 74
4
Contents
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.11 Modulation Index Limit Register (0x16) ................................................................................. 75
6.12 Bank Switching Command Register (0x40) ............................................................................ 76
6.13 Input Mixer Registers (0x41, 0x42, 0x47, 0x48, Channels 1–4) ..................................................... 77
6.14 Bass Management Registers (0x49–0x50) ............................................................................. 78
6.15 Biquad Filter Registers (0x51–0x88)..................................................................................... 79
6.16 Bass and Treble Bypass Register (0x89–0x90, Channels 1–4) ..................................................... 79
6.17 Loudness Registers (0x91–0x95) ........................................................................................ 80
6.18 DRC1 Control (0x96, Channels 1–3) .................................................................................... 80
6.19 DRC2 Control (0x97, Channel 4)......................................................................................... 81
6.20 DRC1 Data Registers (0x98–0x9C) ..................................................................................... 81
6.21 DRC2 Data Registers (0x9D–0xA1) ..................................................................................... 82
6.22 DRC Bypass Registers (0xA2, 0xA3, 0xA8, 0xA9) .................................................................... 82
6.23 4 × 2 Output Mixer Registers (0xAA and 0xAB)........................................................................ 83
6.24 4 × 3 Output Mixer Registers (0xB0–0xB1)............................................................................. 84
6.25 PSVC Volume Biquad Register (0xCF) ................................................................................. 85
6.26 Volume, Treble, and Bass Slew Rates Register (0xD0) .............................................................. 86
6.27 Volume Registers (0xD1, 0xD2, 0xD7, and 0xD8)..................................................................... 86
6.28 Bass Filter Set Register (0xDA) ......................................................................................... 88
6.29 Bass Filter Index Register (0xDB) ....................................................................................... 89
6.30 Treble Filter Set Register (0xDC) ........................................................................................ 90
6.31 Treble Filter Index (0xDD)................................................................................................. 91
6.32 AM Mode Register (0xDE) ................................................................................................ 92
6.33 PSVC Range Register (0xDF)............................................................................................ 93
6.34 General Control Register (0xE0) ......................................................................................... 93
6.35 Incremental Multiple-Write Append Register (0xFE)................................................................... 93
TAS5504A Example Application Schematic ........................................................................... 93
7
Contents
5
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
List of Figures
1-1
TAS5504A Functional Structure................................................................................................. 13
1-2
TAS5504A DAP Architecture With I2C Registers (fS ≤ 96 kHz) ............................................................. 21
TAS5504A Architecture With I2C Registers (fS = 176.4 kHz or fS = 192 kHz) ............................................ 22
TAS5504A Detailed Channel Processing...................................................................................... 22
5.23 Format ........................................................................................................................ 23
Conversion Weighting Factors—5.23 Format to Floating Point............................................................. 23
Alignment of 5.23 Coefficient in 32-Bit I2C Word ............................................................................. 24
25.23 Format ...................................................................................................................... 24
Alignment of 25.23 Coefficient in Two 32-Bit I2C Words..................................................................... 25
Alignment of 25.23 Coefficient in Two 32-Bit I2C Words..................................................................... 25
TAS5504A Digital Audio Processing ........................................................................................... 26
Input Crossbar Mixer ............................................................................................................. 26
Biquad Filter Structure............................................................................................................ 27
Automute Threshold .............................................................................................................. 29
Loudness Compensation Functional Block Diagram ......................................................................... 30
Loudness Example Plots......................................................................................................... 31
DRC Positioning in TAS5504A Processing Flow ............................................................................. 33
DRC Transfer Function Structure ............................................................................................... 33
TAS5504A Attack and Decay Definition ....................................................................................... 35
Output Mixers...................................................................................................................... 38
De-Emphasis Filter Characteristics ............................................................................................. 39
Power Supply and Digital Gains (Log Space)................................................................................. 40
Power Supply and Digital Gains (Linear Space).............................................................................. 40
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
Block Diagrams of Typical Systems Requiring TAS5504A
Automatic AM Interference Avoidance Circuit................................................................................. 41
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
4-2
4-3
Slave Mode Serial Data Interface Timing...................................................................................... 53
Start and Stop Conditions Timing Waveforms ................................................................................ 54
I2C Pullup Circuit (With No Series Resistor)................................................................................... 55
I2C Pullup Circuit (With Series Resistor) ....................................................................................... 55
Reset Timing....................................................................................................................... 56
Power-Down Timing .............................................................................................................. 56
Error Recovery Timing ........................................................................................................... 57
Mute Timing........................................................................................................................ 57
HP_SEL Timing ................................................................................................................... 58
I2S 64-fS Format ................................................................................................................... 59
Left-Justified 64-fS Format ....................................................................................................... 60
Right-Justified 64-fS Format ..................................................................................................... 61
Typical I2C Sequence............................................................................................................. 62
Single-Byte Write Transfer....................................................................................................... 63
Multiple-Byte Write Transfer ..................................................................................................... 63
6
List of Figures
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
4-4
4-5
Single-Byte Read Transfer....................................................................................................... 64
Multiple-Byte Read Transfer .................................................................................................... 65
List of Figures
7
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
List of Tables
1-1
I2C Register 0xD0 Bit 30 Usage................................................................................................. 14
1-2
Serial Data Formats .............................................................................................................. 18
TAS5504A Audio-Processing Feature Sets ................................................................................... 20
Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)...................................................... 27
Bass and Treble Filter Selections............................................................................................... 28
Linear Gain Step Size ............................................................................................................ 28
Default Loudness Compensation Parameters................................................................................. 30
Example Loudness Function Parameters...................................................................................... 31
DRC Recommended Changes From TAS5504A Defaultss ................................................................. 32
Device Outputs During Reset ................................................................................................... 42
Values Set During Reset......................................................................................................... 42
Device Outputs During Power Down ........................................................................................... 43
Device Outputs During Back-End Error ........................................................................................ 44
Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C) .......................................... 45
Recommended TAS5504A Configurations for Texas Instruments Power Stages ....................................... 46
Audio System Configuration (General Control Register 0xE0).............................................................. 46
Volume Ramp Rates in ms ...................................................................................................... 47
Clock Control Register ........................................................................................................... 69
General Status Register (0x01) ................................................................................................. 69
System Control Register 1 ....................................................................................................... 70
System Control Register 2 ....................................................................................................... 70
Channel Configuration Control Registers ...................................................................................... 71
Headphone Configuration Control Register ................................................................................... 71
Serial Data Interface Control Register Format ................................................................................ 72
Soft-Mute Register (0x0F) ....................................................................................................... 72
Automute Control Register (0x14) .............................................................................................. 73
Automute PWM Threshold and Back-End Reset Period..................................................................... 74
Modulation Index Limit Register................................................................................................. 75
Bank Switching Command....................................................................................................... 76
Input Mixer Registers Format (Channels 1–4) ................................................................................ 77
Bass Management Registers Format (0x49–0x50)........................................................................... 78
Biquad Filters Register Format (0x51–0x88) .................................................................................. 79
Contents of One 20-Byte Biquad Filter Register Format (Default = All-Pass) ............................................ 79
Bass and Treble Bypass Register Format (0x89–0x90) ..................................................................... 79
Loudness Registers Format (0x91–0x95)...................................................................................... 80
DCR1 Control (0x96, Channels 1–3) ........................................................................................... 80
DRC2 Control (0x97, Channel 4) ............................................................................................... 81
DRC1 Data Registers ............................................................................................................ 81
DRC2 Data Registers ............................................................................................................ 82
1-3
1-4
1-5
1-6
1-7
1-8
1-9
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
8
List of Tables
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
DRC Bypass Registers Format (0xA2–0xA9) ................................................................................. 82
Output Mixer Control Register Format (Upper 4 Bytes)...................................................................... 83
Output Mixer Control (Lower 4 Bytes).......................................................................................... 83
Output Mixer Control (Lower 4 Bytes).......................................................................................... 84
Output Mixer Control (Middle 4 Bytes) ......................................................................................... 84
Output Mixer Control (Lower 4 Bytes).......................................................................................... 85
Volume Biquad Register Format (Default = All-pass) ........................................................................ 85
Volume Gain Update Rate (Slew Rate) ........................................................................................ 86
Treble and Bass Gain Step Size (Slew Rate) ................................................................................. 86
Volume Registers ................................................................................................................. 86
Master and Individual Volume Controls ........................................................................................ 87
Channel 4 Subwoofer............................................................................................................. 88
Channel 3, 2, 1 (Center, Right Front, and Left Front) ........................................................................ 88
Bass Filter Index Register........................................................................................................ 89
Bass Filter Index Table .......................................................................................................... 89
Channel 4 Subwoofer............................................................................................................. 90
Channel 3, 2, 1 (Center, Right Front, and Left Front) ........................................................................ 90
Treble Filter Index Register...................................................................................................... 91
Treble Filter Index ................................................................................................................ 91
AM Mode Register ................................................................................................................ 92
AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE) .................................................. 92
AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE) ................................................ 92
Volume Gain Update Rate (Slew Rate) ........................................................................................ 93
General Control Register......................................................................................................... 93
MATLAB is a trademark of The MathWorks, Inc.
All trademarks are the property of their respective owners.
List of Tables
9
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
10
List of Tables
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1
Introduction
1.1 TAS5504A Features
•
Audio Input/Output
–
•
4 × 2 Output Mixer – Channels 1 and 2.
Each Output Can Be Any Ratio of Any Two
Signal-Processed Channels. It Is
Recommended to Use the Pass-Through
Output Mixer Configuration.
–
Automatic Master Clock Rate and Data
Sample Rate Detection
–
–
–
Four Serial Audio Input Channels
Four PWM Audio Output Channels
Headphone PWM Output to Drive an
External Differential Amplifier Like the
TPA112
4 × 3 Output Mixer – Channels 3 and 4.
Each Output Can Be Any Ratio of Any
Three Signal-Processed Channels. It Is
Recommended to Use the Pass-Through
Output Mixer Configuration.
–
–
–
PWM Outputs Support Single-Ended and
Bridge-Tied Loads
32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and
192-kHz Sampling Rates
Data Formats: 16-, 20-, or 24-Bit
Left-Justified, I2S, or Right-Justified Input
Data
•
Three Coefficient Sets Stored on the Device
Can Be Selected Manually or Automatically
(Based on Specific Data Rates)
•
•
DC Blocking Filters
Able to Support a Variety of
Bass-Management Algorithms
–
–
64 × fS Bit-Clock Rate
128, 192, 256, 384, 512, and 768 × fS Master
Clock Rates (up to a Maximum of 50 MHz)
•
PWM Processing
–
32-Bit Processing PWM Architecture With
40 Bits of Precision
•
Audio Processing
•
48-Bit Processing Architecture With 76 Bits
of Precision for Most Audio-Processing
Features
–
8× Oversampling With 5th-Order Noise
Shaping at 32 kHz–48 kHz, 4×
Oversampling at 88.2 kHz and 96 kHz, and
2× Oversampling at 176.4 kHz and 192 kHz
•
Volume Control Range: 36 dB to –109 dB
•
Master Volume Control Range of 18 dB
to –100 dB
–
–
–
>102-dB Dynamic Range
THD+N < 0.1%
20-Hz–20-kHz Flat Noise Floor for 44.1-, 48-,
88.2-, 96-, 176.4-, and 192-kHz Data Rates
•
Four Individual Channel Volume Control
Ranges of 18-dB to –109-dB
–
–
Digital De-Emphasis for 32-, 44.1-, and
48-kHz Data Rates
Flexible Automute Logic With
Programmable Threshold and Duration for
Noise-Free Operation
Intelligent AM Interference Avoidance
System Provides Clear AM Reception
Power-Supply Volume-Control (PSVC)
Support for Enhanced Dynamic Range in
High-Performance Applications
•
•
Programmable Soft Volume and Mute
Update Rates
Two Bass and Treble Tone Controls With
±18-dB Range, Selectable Corner
Frequencies, and 2nd-Order Slopes
–
–
•
•
L, R, and C
Sub
•
•
Configurable Loudness Compensation
Two Dynamic Range Compressors With
Two Thresholds, Two Offsets, and Three
Slopes
–
Adjustable Modulation Limit
•
General Features
–
Automated Operation With an Easy-to-Use
Control Interface
•
•
Seven Biquads per Channel
8 × 4 Input Crossbar Mixer. Each Signal
Processing Channel Input Can Be Any
Ratio of the Eight Input Channels
–
–
I2C Serial Control Slave Interface
Integrated AM Interference Avoidance
Circuitry
–
–
Single 3.3-V Power Supply
64-Pin TQFP Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
MATLAB is a trademark of The MathWorks, Inc.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2006, Texas Instruments Incorporated
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
–
5-V Tolerant Inputs
1.2 Overview
The TAS5504A is a four-channel digital pulse-width modulator (PWM) that provides both advanced
performance and a high level of system integration. The TAS5504A is designed to interface seamlessly
with most audio digital signal processors. The TAS5504A automatically adjusts control configurations in
response to clock and data-rate changes and idle conditions. This enables the TAS5504A to provide an
easy-to-use control interface with relaxed timing requirements.
The TAS5504A can drive four channels of H-bridge power stages. Texas Instruments power stages are
designed to work seamlessly with the TAS5504A. The TAS5504A supports either the single-ended or
bridge-tied-load configuration. The TAS5504A also provides a high-performance differential output to drive
an external differential-input analog headphone amplifier, such as the TPA112.
The TAS5504A uses AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.
The 8× oversampling combined with the 5th-order noise shaper provides a broad, flat noise floor and
excellent dynamic range from 20 Hz to 20 kHz.
The TAS5504A is a clocked, slave-only device. The TAS5504A receives MCLK, SCLK, and LRCLK from
other system components. The TAS5504A accepts master clock rates of 128, 192, 256, 384, 512, and
768 fS. The TAS5504A accepts a 64-fS bit clock.
The TAS5504A allows for extending the dynamic range by providing a power-supply volume-control
(PSVC) output signal.
12
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Output Control
4 ´ 2 Crossbar Mixer
8 ´ 4 Crossbar Mixer
AVSS
AVDD
DVSS
DVDD
DAP Control
PWM Control
VRD_PLL
VRA_PLL
VBGAP
AVDD_REF
AVSS_PLL
AVDD_PLL
VR_PLL
System Control
Clock, PLL, and Serial Data I/F
Figure 1-1. TAS5504A Functional Structure
1.3 Changes From the TAS5504 to the TAS5504A
•
•
High-pass filter is enabled by default (0x03 bit 7)
I2C register 0xD0 bit 30 is added in TAS5504A to support remapped output mixer configuration. It has
a default value of 0.
Introduction
13
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Table 1-1. I2C Register 0xD0 Bit 30 Usage
0xD0 Bit 30
Output Mixer Configuration
Mode
PWM (Speaker) Operation
Headphone operation
1
Pass-through
4-channel mode
Normal operation
Normal operation
Constraints are placed in
setting the combined volume
below –109 dB and in using
individual channel mute.
0 (default)
Remapped
4-channel mode
Normal Operation
The pass-through output mixer configuration means that each DAP channel is mapped to the same output
PWM channel. For example, DAP channel 1 is routed to PWM channel 1, etc.
The remapped output mixer configuration means that the PWM channel could be a mix or rerouting of the
DAP channels. For example, DAP channel 2 is routed to PWM channel 1. This remapping causes some
complications in operation (see Table 1-1).
The recommended initialization sequence to use the pass-through ouput mixer configuration follows.
1. After TAS5504A reset, the default master volume is muted. It must be updated with a nonmute value
for the system to start.
2. I2C register 0xD0 bit 30 must be set to a value of 1.
Note that for best results, the pass-through ouput mixer configuration is recommended (0xD0 bit
30 = 1).
When remapping or mixing DAP channels to different PWM output channels (remapped output mixer
configuration), consider the following limitations:
•
•
•
Individual channel mute should not be used.
The sum of the minimum channel volume and master volume should not be below –109 dB.
0xD0 bit 30 = 0
14
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4 Physical Characteristics
1.4.1 Terminal Assigments
PAG PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VRA_PLL
VR_PWM
NC
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PLL_FLT_RET
2
PLL_FLTM
NC
3
PLL_FLTP
NC
4
NC
5
AVSS
AVSS
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
6
VRD_PLL
AVSS_PLL
AVDD_PLL
7
8
9
10
11
12
13
14
15
16
VBGAP
RESET
VALID
DVSS
HP_SEL
BKND_ERR
PDN
MUTE
DVDD
DVSS
DVDD
DVSS
DVSS
VR_DIG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0010-02
1.4.2 Ordering Information
TA
PLASTIC 64-PIN PQFP (PN)
TAS5504APAG
0°C to 70°C
1.4.3 TERMINAL FUNCTIONS
TERMINAL
5-V
TOLERANT
TERMIN-
ATION(2)
I/O(1)
DESCRIPTION
NAME
NO.
AVDD_PLL
9
P
3.3-V analog power supply for PLL This terminal can be connected to the same
power source used to drive power terminal DVSS, but to achieve low PLL jitter, this
terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor(3)
.
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic-1 input; pulldowns → logic-0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
Introduction
15
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
TERMINAL
5-V
TOLERANT
TERMIN-
ATION(2)
I/O(1)
DESCRIPTION
NAME
AVSS
NO.
5, 6
8
P
P
Analog ground
AVSS_PLL
Analog ground for PLL. This terminal should reference the same ground as power
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must be
minimized. The availability of the AVSS terminal allows a designer to use optimizing
techniques such as star ground connections, separate ground planes, or other quiet
ground distribution techniques to achieve a quiet ground reference at this terminal.
BKND_ERR
DVDD
37
DI
P
Pullup
Active-low. A back-end error sequence is generated by applying a logic low to this
terminal. BKND_ERR results in no change to any system parameters, with all
H-bridge drive signals going to a hard-mute state (M-state).
15, 36
3.3-V digital power supply. It is recommended that decoupling capacitors of 0.1 µF
and 10 µF be mounted as close to this pin(s) as possible.
DVDD_PWM
DVSS
54
16
P
P
3.3-V digital power supply for PWM
Digital ground for digital core and most of I/O buffers
Digital ground
DVSS
34, 35, 38
53
P
DVSS_PWM
HP_SEL
P
Digital ground for PWM
12
DI
5 V
Pullup
Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected (headphone
is off).
LRCLK
MCLK
26
63
DI
DI
5 V
5 V
Serial audio data left/right clock (sampling rate clock)
Pulldown
Pullup
MCLK is a 3.3-V clock master clock input. The input frequency of this clock can
range from 4 MHz to 50 MHz.
MUTE
NC
14
DI
5 V
Soft mute of outputs, active-low (Muted signal = a logic low, normal operation = a
logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
44, 45, 46,
47, 55, 56,
57, 58
No connection
OSC_CAP
PDN
18
13
AO
DI
Oscillator capacitor
5 V
Pullup
Power down, active-low. PDN powers down all logic and stops all clocks whenever
a logic low is applied. The internal parameters are preserved through a power-down
cycle, as long as RESET is not active. The duration for system recovery from
power down is 100 ms.
PLL_FLTM
PLL_FLTP
PLL_FLT_RET
PSVC
3
AO
AI
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
PLL external filter return
4
2
AO
O
32
59
61
60
62
40
42
49
51
41
43
50
52
Power-supply volume-control PWM output
PWM left-channel headphone (differential –)
PWM right-channel headphone (differential –)
PWM left-channel headphone (differential +)
PWM right-channel headphone (differential +)
PWM 1 output (differential –)
PWM_HPML
PWM_HPMR
PWM_HPPL
PWM_HPPR
PWM_M_1
PWM_M_2
PWM_M_3
PWM_M_4
PWM_P_1
PWM_P_2
PWM_P_3
PWM_P_4
RESERVED
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
PWM 2 output (differential –)
PWM 3 output (differential –)
PWM 4 output (differential –)
PWM 1 output (differential +)
PWM 2 output (differential +)
PWM 3 output (differential +)
PWM 4 output (differential +)
21, 22, 23,
64
Connect to digital ground
RESET
11
DI
5 V
Pullup
System reset input, active-low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that restores the
TAS5504A to its default conditions, sets the VALID output low, and places the
PWM in the M-state. Master volume is immediately set to full attenuation. On the
release of RESET, if PDN is high, the system performs a 4 ms–5 ms device
initialization and sets the volume at mute.
I2C serial control clock input
SCL
25
27
24
DI
DI
5 V
5 V
5 V
SCLK
SDA
Serial audio data clock (shift clock) input
I2C serial control data interface input/output
DIO
16
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
TERMINAL
NAME
SDIN1
5-V
TOLERANT
TERMIN-
ATION(2)
I/O(1)
DESCRIPTION
NO.
31
DI
5 V
5 V
5 V
5 V
Pulldown
Pulldown
Pulldown
Pulldown
Serial audio data-1 input is one of the serial-data input ports. SDIN1 supports four
discrete (stereo) data formats and is capable of inputting data at 64 fS.
SDIN2
SDIN3
SDIN4
30
29
28
DI
DI
DI
Serial audio data-2 input is one of the serial-data input ports. SDIN2 supports four
discrete (stereo) data formats and is capable of inputting data at 64 fS.
Serial audio data-3 input is one of the serial-data input ports. SDIN3 supports four
discrete (stereo) data formats and is capable of inputting data at 64 fS.
Serial audio data-4 input is one of the serial-data input ports. SDIN4 supports four
discrete (stereo) data formats and is capable of inputting data at 64 fS.
VALID
39
10
DO
P
Output indicating validity of PWM outputs, active-high
VBGAP
Band-gap voltage reference. A pinout of the internally regulated 1.2-V reference.
Typically has a 1-nF low-ESR capacitor(3). between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
VRA_PLL
VR_DIG
1
P
P
Voltage reference for PLL analog supply, 1.8 V. A pinout of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low-ESR capacitor(3) should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
33
7
Voltage reference for digital core supply, 1.8 V. A pinout of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low-ESR capacitor(3). should be
connected between this terminal and DVSS. This terminal must not be used to
power external devices.
VRD_PLL
VR_DPLL
VR_PWM
XTL_OUT
XTL_IN
P
Voltage reference for PLL digital supply, 1.8 V. A pinout of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low-ESR capacitor(3). should be
connected between this terminal and AVSS_PLL. This terminal must not be used to
power external devices.
17
48
19
20
P
Voltage reference for digital PLL supply, 1.8 V. A pinout of the internally regulated
1.8-V power used by digital PLL logic. A 0.1-µF low-ESR capacitor(3). should be
connected between this terminal and DVSS_CORE. This terminal must not be used
to power external devices.
P
Voltage reference for digital PWM core supply, 1.8 V. A pinout of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low-ESR
capacitor(3). should be connected between this terminal and DVSS_PWM. This
terminal must not be used to power external devices.
AO
AI
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide
a reference clock for the TAS5504A via use of an external fundamental mode
crystal. XTL_OUT is the 1.8-V output drive to the crystal. A 13.5-MHz crystal
(HCM49) is recommended.
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They provide
a reference clock for the TAS5504A via use of an external fundamental mode
crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. A 13.5-MHz crystal
(HCM49) is recommended.
1.4.4 TAS5504A Functional Description
Figure 1-2 shows the TAS5504A functional structure. The next sections describe the TAS5504A functional
blocks:
•
•
•
•
•
•
Power supply
Clock, PLL, and serial data interface
I2C serial control interface
Device control
Digital audio processor (DAP)
Pulse-width-modulation (PWM) processor
1.4.4.1 Power Supply
The power-supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5504A. The analog supply supports the analog PLL, whereas digital supplies
support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the
output control.
Introduction
17
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.4.2 Clock, PLL, and Serial Data Interface
The TAS5504A is a clocked, slave-only device, and it requires the use of an external 13.5-MHz crystal. It
accepts MCLK, SCLK, and LRCLK as inputs only.
The TAS5504A uses the external crystal to provide a time base for:
•
•
•
•
Continuous data and clock-error detection and management
Automatic data-rate detection and configuration
Automatic MCLK rate detection and configuration (automatic bank switching)
Supporting I2C operation/communication while MCLK is absent
The TAS5504A automatically handles clock errors, data-rate changes, and master-clock frequency
changes without requiring intervention from an external system controller. This feature significantly
reduces system complexity and design.
1.4.4.2.1 Serial Audio Interface
The TAS5504A operates as a slave-only/receive-only serial data interface in all modes. The TAS5504A
has four PCM serial data interfaces to permit eight channels of digital data to be received though the
SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB-first, 2s-complement format.
The serial data input interface of the TAS5504A can be configured in right-justified, I2S, or left-justified
modes. The serial data interface format is specified using the I2C data interface control register. The
supported formats and word lengths are shown in Table 1-2.
Table 1-2. Serial Data Formats
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
Right-justified
Right-justified
Right-justified
I2S
16
20
24
16
20
24
16
20
24
I2S
I2S
Left-justified
Left-justified
Left-justified
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5504A accepts 16-, 20-, or 24-bit data
at 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, or 192-kHz serial data in in left-justified, I2S, right-justified, and
serial data formats using a 64-fS SCLK clock and a 128, 192, 256, 384, 512, or 768 × fS MCLK rates (up to
a maximum of 50 MHz). The parameters of this clock and serial data interface are I2C configurable.
1.4.4.3 I2C Serial Control Interface
The TAS5504A has an I2C serial control slave interface (write address = 0x36 and read address = 0x37)
to receive commands from a system controller. The serial control interface supports both normal-speed
(100 kHz) and high-speed (400 kHz) operations without wait states. Because the TAS5504A has a crystal
time base, this interface operates even when MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data
processing registers, the serial control interface also supports multiple-byte (4-byte) write operations.
18
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data
write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, ..., etc.,
write operations that are composed of a device address, read/write bit, and subaddress and any multiple
of 4 bytes of data. This permits the system to write large register values incrementally without blocking
other I2C transactions. To use this feature, the first block of data is written to the target I2C address and
each subsequent block of data is written to a special append register (0xFE) until all the data is written
and a stop bit is sent. An incremental read operation is not supported.
1.4.4.4 Device Control
The TAS5504A control section provides the control and sequencing for the TAS5504A. The device control
provides both high- and low-level control for the serial control interface, clock and serial-data interfaces,
digital audio processor, and pulse-width-modulator sections.
1.4.4.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio-processing functions—soft volume, loudness
compensation, bass and treble processing, dynamic range control, channel filtering, and input and output
mixing. Figure 1-4 shows the TAS5504A DAP architecture.
The DAP accepts the 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM
section. The DAP supports two configurations, one for 32-kHz–96-kHz data and one for
176.4-kHz–192-kHz data.
1.4.4.5.1 TAS5504A Audio-Processing Configurations
The 32-kHz–96-kHz configuration supports four channels of data processing.
The 176.4-kHz–192-kHz configuration supports three channels of signal processing with one channel
passed though (or derived from the three processed channels).
To support efficiently the processing requirements of both multichannel 32-kHz–96-kHz data and the two
channel 176.4- and 192-kHz data, the TAS5504A supports separate audio-processing features for
32-kHz–96-kHz data rates and for 176.4 kHz and 192 kHz. See Table 1-3 for a summary of the
TAS5504A processing feature sets.
1.4.4.5.2 TAS5504A Audio Signal-Processing Functions
The DAP provides 10 primary signal-processing functions.
1. The data-processing input has an 8 × 4 input crossbar mixer. This enables each input to be any ratio of
the eight input channels.
2. Two I2C-programmable threshold detectors in each channel support automute.
3. Seven biquads per channel
4. Two soft bass and treble tone controls with ±18-dB range, programmable corner frequencies, and
2nd-order slopes. In 4-channel mode, bass and treble controls are normally configured as follows:
–
–
Bass and treble 1: channel 1 (left), channel 2 (right), and channel 3 (center)
Bass and treble 2: channel 4 (subwoofer)
5. Individual channel and master-volume controls. Each control provides an adjustment range of 18 dB to
–109 dB. This permits a total volume device control range of 36 dB to –109 dB plus mute. The DAP
soft-volume and mute update interval is I2C-programmable. The update is performed at a fixed rate
regardless of the sample rate.
6. Programmable loudness compensation that is controlled via the combination of the master and
individual volume settings
7. Two dual-threshold, dual-rate dynamic range compressors (DRCs). The volume gain values provided
are used as input parameters using the maximum RMS (master volume × individual channel volume).
8. 4 × 2 output mixer (channels 1 and 2). Each output can be any ratio of any two signal-processed
channels.
Introduction
19
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
9. 4 × 3 output mixer (channels 3 and 4). Each output can be any ratio of any three signal-processed
channels.
10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of
sample-rate-dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These
can be set to be automatically selected for one or more data sample rates or can be manually selected
under I2C program control. This feature enables coefficients for different sample rates to be stored in
the TAS5504A and then selected when needed.
Table 1-3. TAS5504A Audio-Processing Feature Sets
FEATURE
32 kHz–96 kHz
176.4 AND 192 kHz
FOUR-CHANNEL FEATURE SET
THREE-CHANNEL FEATURE SET
Signal-processing channels
Pass-through channels
4
3
N/A
1
Master volume
One for four channels
4
One for four channels
3
Individual channel volume controls
Bass and treble tone controls
Two bass and treble tone controls with ±18-dB
range, programmable corner frequencies, and
2nd-order slopes
Two bass and treble tone controls with ±18-dB
range, programmable corner frequencies, and
2nd-order slopes
L, R, and C (Ch1, Ch2, and Ch3)
Sub (Ch4)
L and R (Ch1 and Ch2)
Sub (Ch4)
Biquads
28
21
Dynamic range compressors
Input/output mapping/mixing
DRC1 for three satellites and DRC2 for sub
One for two satellites and one for sub
Each of the four signal-processing channels
input can be any ratio of the eight input
channels.
Each of the three signal-processing channels
and the one pass-though channel input can be
any ratio of the eight input channels.
Each of the four outputs can be any ratio of any Each of the four outputs can be any ratio of any
two processed channels.
of the three processed and one bypass
channels.
DC blocking filters (implemented in
the PWM Section)
Four channels
Digital de-emphasis (implemented in
the PWM Section)
Four channels for 32 kHz, 44.1 kHz, and 48 kHz
Four channels
N/A
Loudness
Three channels
Number of coefficient sets stored
Three additional coefficient sets can be stored in memory
1.4.5 TAS5504A DAP Architecture
1.4.5.1 TAS5504A DAP Architecture Diagrams
Figure 1-2 shows the TAS5504A DAP architecture for fS = 96 kHz. Note the TAS5504A bass-management
architecture shown in channels 1, 2, 3, and 4. Note that the I2C registers are shown to help the designer
configure the TAS5504A.
Figure 1-3 shows the TAS5504A architecture for fS = 176.4 kHz or fS = 192 kHz. Note that only channels
1, 2, and 4 contain all the features. Channel 3 is pass-through except for master volume control.
Figure 1-4 shows TAS5504A detailed channel processing. The output mixer is 4 × 2 for channels 1–2 and
4 × 3 for channels 3–4.
20
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Master Vol
(0xD9)
Max Vol
(1)
SDIN1-L (L)
A
B
C
D
E
F
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
IP Mixer 1
(I2C 0x41)
7 DAP 1
BQ
Bass &
Treble 1
(0xDA-
0xDD)
Loud-
ness
OP Mixer 1
(I2C 0xAA)
4 ´ 2 Output
Mixer
DAP 1
Volume
(0xD1)
DRC1
(0x96-
0x9C)
L to
PWM1
(0x51-
0x57)
(0x91-
0x95)
G
H
SDIN4-R (LFE)
Master Vol
(0xD9)
Max Vol
SDIN1-L (L)
(1)
A
B
C
D
E
F
SDIN1-R (R)
IP Mixer 2
(I2C 0x42)
7 DAP 2
BQ
Bass &
Treble 1
(0xDA-
0xDD)
Loud-
ness
OP Mixer 2
(I2C 0xAB)
4 ´ 2 Output
Mixer
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
DAP 2
Volume
(0xD2)
DRC1
(0x96-
0x9C)
R to
PWM2
(0x58-
0x5E)
(0x91-
0x95)
G
H
SDIN4-R (LFE)
Coeff = 0 (lin), (I2C 0x4E)
Master Vol
(0xD9)
Coeff = 0 (lin), (I2C 0x4B)
Max Vol
Coeff = 1 (lin)
(I2C 0x4D)
SDIN1-L (L)
SDIN1-R (R)
A
B
C
D
E
F
IP Mixer 3
(I2C 0x47)
2 DAP 3
BQ
5 DAP 3
BQ
Bass &
Treble 1
(0xDA-
0xDD)
Loud-
ness
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
OP Mixer 3
(I2C 0xB0)
4 ´ 2 Output
Mixer
DAP 3
Volume
(0xD7)
DRC1
(0x96-
0x9C)
C to
PWM3
(0x7B-
0x7C)
(0x7D-
0x81)
(0x91-
0x95)
SDIN3-R (RBS)
(1)
SDIN4-L (C)
G
H
SDIN4-R (LFE)
Coeff = 0 (lin), (I2C 0x4C)
Master Vol
(0xD9)
Coeff = 0 (lin), (I2C 0x49)
Coeff = 0 (lin)
Max Vol
(I2C 0x4A)
Coeff = 1 (lin)
SDIN1-L (L)
SDIN1-R (R)
A
B
C
D
E
F
IP Mixer 4
(I2C 0x48)
(I2C 0x50)
2 DAP 4
5 DAP 4
BQ
Bass &
Treble 4
(0xDA-
0xDD)
Loud-
ness
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
OP Mixer 4
(I2C 0xB1)
4 ´ 2 Output
Mixer
DAP 4
Volume
(0xD8)
DRC2
(0x9D-
0xA1)
Sub to
PWM4
BQ
(0x82-
0x83)
(0x84-
0x88)
(0x91-
0x95)
SDIN4-L (C)
(1)
G
H
SDIN4-R (LFE)
Coeff = 0 (lin), (I2C 0x4F)
B0014-02
(1) Default input
Figure 1-2. TAS5504A DAP Architecture With I2C Registers (fS ≤ 96 kHz)
Introduction
21
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Master Vol
(0xD9)
Max Vol
(1)
SDIN1-L (L)
SDIN1-R (R)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
A
B
C
D
E
F
IP Mixer 1
(I2C 0x41)
7 DAP 1
BQ
Bass &
Treble 1
(0xDA-
0xDD)
Loud-
ness
OP Mixer 1
DAP 1
Volume
(0xD1)
DRC1
(0x96-
0x9C)
L to
(I2C 0xAA)
4 ´ 2 Output
Mixer
PWM1
(0x51-
0x57)
(0x91-
0x95)
G
H
SDIN4-R (LFE)
Master Vol
(0xD9)
Max Vol
SDIN1-L (L)
(1)
A
B
C
D
E
F
SDIN1-R (R)
IP Mixer 2
(I2C 0x42)
7 DAP 2
BQ
Bass &
Treble 1
(0xDA-
0xDD)
Loud-
ness
OP Mixer 2
(I2C 0xAB)
4 ´ 2 Output
Mixer
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
SDIN4-L (C)
DAP 2
Volume
(0xD2)
DRC1
(0x96-
0x9C)
R to
PWM2
(0x58-
0x5E)
(0x91-
0x95)
G
H
SDIN4-R (LFE)
Master Vol
(0xD9)
SDIN1-L (L)
SDIN1-R (R)
A
B
C
D
E
F
IP Mixer 3
(I2C 0x47)
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
OP Mixer 3
(I2C 0xB0)
4 ´ 3 Output
Mixer
DAP 3
Volume
(0xD7)
C to
PWM3
SDIN3-R (RBS)
(1)
SDIN4-L (C)
G
H
SDIN4-R (LFE)
Master Vol
(0xD9)
Max Vol
SDIN1-L (L)
SDIN1-R (R)
A
B
C
D
E
F
IP Mixer 4
(I2C 0x48)
7 DAP 4
BQ
Bass &
Treble 4
(0xDA-
0xDD)
Loud-
ness
SDIN2-L (LS)
SDIN2-R (RS)
SDIN3-L (LBS)
SDIN3-R (RBS)
OP Mixer 4
(I2C 0xB1)
4 ´ 3 Output
Mixer
DAP 4
Volume
(0xD8)
DRC2
(0x9D-
0xA1)
Sub to
PWM4
(0x82-
0x88)
(0x91-
0x95)
SDIN4-L (C)
(1)
G
H
SDIN4-R (LFE)
B0015-02
(1) Default input
Figure 1-3. TAS5504A Architecture With I2C Registers (fS = 176.4 kHz or fS = 192 kHz)
A_to_ipmix
Left
Master
Volume
A
B
SDIN1
Right
B_to_ipmix
Channel Volume
Max
Volume
C_to_ipmix
Bass and Treble
Bypass
DRC
Bypass
Left
C
D
SDIN2
Loudness
Output
Gain
Right
D_to_ipmix
E_to_ipmix
Output Mixer Sums
Any Two Channels
7
Bass
and
Treble
Biquads
in
32-Bit
Trunc
PWM
Proc
PWM
Output
Series
Pre-
Post-
DRC
Inline
Volume Volume
Left
Input
Mixer
Bass
and
Treble
Inline
E
F
SDIN3
1 Other
Channel Output
From 7 Available
Right
F_to_ipmix
G_to_ipmix
DRC
Left
G
H
SDIN4
Right
H_to_ipmix
B0016-01
Figure 1-4. TAS5504A Detailed Channel Processing
22
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.5.2 I2C Coefficient Number Formats
The architecture of the TAS5504A is contained in ROM resources within the TAS5504A and cannot be
altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus
interface, provide a user with the flexibility to set the TAS5504A to a configuration that achieves the
system-level goals.
The firmware is executed in a 48-bit signed, fixed-point arithmetic machine. The most significant bit of the
48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented
by multiplying a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output
product is then truncated to a signed 48-bit number. Level offset operations are implemented by adding a
48-bit signed offset coefficient to a 48-bit signed data value. In most cases, if the addition results in
overflowing the 48-bit signed number format, saturation logic is used. This means that if the summation
results in a positive number that is greater than 0x7FFF FFFF FFFF (the spaces are used to ease the
reading of the hexadecimal number), the number is set to 0x7FFF FFFF FFFF. If the summation results in
a negative number that is less than 0x8000 0000 0000, the number is set to 0x8000 0000 0000.
1.4.5.2.1 28-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal
point. This is shown in the Figure 1-5.
−23
2
Bit
−4
2
Bit
Bit
−1
0
2
2 Bit
3
2 Bit
Sign Bit
S_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0007-01
Figure 1-5. 5.23 Format
The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 1-6. If
the most-significant bit is logic-0, the number is a positive number, and the weighting shown yields the
correct number. If the most-significant bit is a logic-1, then the number is a negative number. In this case,
every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 1-6 applied to
obtain the magnitude of the negative number.
3
2
0
−1
−4
−23
2 Bit
2 Bit
2 Bit
2
Bit
2
Bit
2
Bit
3
2
0
−1
−4
−23
(1 or 0) y 2 + (1 or 0) y 2 + … + (1 or 0) y 2 + (1 or 0) y 2 + … + (1 or 0) y 2 + … + (1 or 0) y 2
M0008-01
Figure 1-6. Conversion Weighting Factors—5.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the
32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 1-7.
Introduction
23
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Fraction
Digit 6
Sign
Bit
Integer
Digit 1
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
0
u
u
u
u
S
x
x
x
x.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0009-01
Figure 1-7. Alignment of 5.23 Coefficient in 32-Bit I2C Word
As Figure 1-7 shows, the hexadecimal value of the integer part of the gain coefficient cannot be
concatenated with the hexadecimal value of the fractional part of the gain coefficient to form the 32-bit I2C
coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of
the coefficient occupies all of one hexadecimal digit and the most significant bit of the second hexadecimal
digit. In the same way, the fractional part occupies the lower 3 bits of the second hexadecimal digit, and
then occupies the other five hexadecimal digits (with the eighth digit being the zero-valued most significant
hexadecimal digit).
1.4.5.2.2 48-Bit 25.23 Number Format
All level-adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format.
Numbers formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23
bits to the right of the decimal point. This is shown in Figure 1-8.
−23
2
Bit
Bit
Bit
−10
−1
2
2
0
2 Bit
16
2
Bit
22
23
2
Bit
Bit
2
Sign Bit
S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0007-02
Figure 1-8. 25.23 Format
Figure 1-9 shows the derivation of the decimal value of a 48-bit, 25.23 format number.
24
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
23
22
0
−1
−23
2
Bit
2
Bit
2 Bit
2
Bit
2
Bit
23
22
0
−1
−23
(1 or 0) y 2 + (1 or 0) y 2 + … + (1 or 0) y 2 + (1 or 0) y 2 + … + (1 or 0) y 2
M0008-02
Figure 1-9. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words
Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the
TAS5504A. The alignment of the 48-bit, 25.23-formatted coefficient in the 8-byte (two 32-bit words) I2C
word is shown in Figure 1-10.
Integer
Sign
Bit
Digit 4
11
9
(Bits 2 − 2 )
Integer
Digit 1
Integer
Digit 2
Integer
Digit 3
Word 1
(Most
Significant
Word)
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
S
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 16
Coefficient
Digit 15
Coefficient
Digit 14
Coefficient
Digit 13
Coefficient
Digit 12
Coefficient
Digit 11
Coefficient
Digit 10
Coefficient
Digit 9
Integer
Digit 4
(Bit 2 )
Fraction
Digit 6
8
Integer
Digit 5
Integer
Digit 6
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
0
Word 2
(Least
Significant
Word)
x
x
x
x
x
x
x
x
x.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0009-02
Figure 1-10. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words
1.4.5.2.3 TAS5504A Audio Processing
The TAS5504A digital audio processing is designed such that noise produced by filter operations is
maintained below the smallest signal amplitude of interest, as shown in Figure 1-11. The TAS5504A
achieves this by increasing the precision of the signal representation substantially above the number of
bits that are absolutely necessary to represent the input signal.
Introduction
25
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Ideal Input
Possible Outputs
Desired Output
Values Retained by
Overflow Bits
Overflow
Maximum Signal Amplitude
Filter
Operation
Reduced
SNR
Signal
Output
Signal
Bits
Output
Signal
Bits
Input
Noise Floor With No
Additional Precision
Noise Floor as a Result
of Additional Precision
M0010-01
Figure 1-11. TAS5504A Digital Audio Processing
Similarly, the TAS5504A carries additional precision in the form of overflow bits to permit the value of
intermediate calculations to exceed the input precision without clipping. The TAS5504A advanced digital
audio processor achieves both of these important performance capabilities by using a high-performance
digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit
accumulator.
1.4.6 Input Crossbar Mixer
The TAS5504A has a full 8 × 4 input crossbar mixer. This mixer permits each signal-processing channel
input to be any ratio of any of the eight input channels. The control parameters for the input crossbar
mixer are programmable via the I2C interface. See the Input Mixer Registers (0x41, 0x42, 0x47, 0x48,
Channels 1–4), Section Section 6.13.
Gain Coefficient
28
48
Input 1
48
Gain Coefficient
28
48
48
Input 2
SUM
•
•
•
48
Gain Coefficient
28
48
Input 8
M0011-03
Figure 1-12. Input Crossbar Mixer
26
Introduction
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.7 Biquad Filters
For 32-kHz to 96-kHz data, the TAS5504A provides 28 biquads across the four channels (seven per
channel).
For 176.4-kHz and 192-kHz data, the TAS5504A has 21 biquads across the three channels (seven per
channel). All of the biquad filters are 2nd-order direct form-I structure.
The direct form-I structure provides a separate delay element and mixer (gain coefficient) for each node in
the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23-format
number) and a signed 28-bit coefficient (5.23-format number). The 76-bit ALU in the TAS5504A allows the
76-bit resolution to be retained when summing the mixer outputs (filter products).
The five 28-bit coefficients for each of the 28 biquads are programmable via the I2C interface. See
Table 1-4.
b
0
b
1
b
2
28
28
28
48
76
76
76
76
48
48
48
Magnitude
Truncation
Σ
a
1
-1
-1
z
z
z
z
28
28
48
48
76
76
a
2
-1
-1
M0012-01
Figure 1-13. Biquad Filter Structure
All five coefficients for one biquad filter structure are written to one I2C register containing 20 bytes (or five
32-bit words). The structure is the same for all biquads in the TAS5504A. Registers 0x51–0x88 show all
the biquads in the TAS5504A. Note that u(31:28) bits are unused and default to 0x0.
Table 1-4. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
INITIALIZATION GAIN COEFFICIENT VALUE
DESCRIPTION
REGISTER FIELD CONTENTS
DECIMAL
1.0
HEX
bo Coefficient
b1 Coefficient
b2 Coefficient
a1 Coefficient
a2 Coefficient
u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)
u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)
u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)
u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)
u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0.0
0.0
0.0
0.0
1.4.8 Bass and Treble Controls
From 32-kHz to 96-kHz data, the TAS5504A has two bass and treble tone controls. Each control has a
±18-dB control range with selectable corner frequencies and 2nd-order slopes. These controls operate four
channel groups:
•
•
L, R, and C (channels 1, 2, and 3)
Sub (channel 4)
Introduction
27
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
For 176.4-kHz and 192-kHz data, the TAS5504A has two bass and treble tone controls. Each control has
a ±18-dB I2C control range with selectable corner frequencies and 2nd-order slopes. These controls
operate two channel groups:
•
•
L and R
Sub
The bass and treble filters use a soft update rate that does not produce artifacts during adjustment.
Table 1-5. Bass and Treble Filter Selections
3-dB CORNER FREQUENCIES
fS
(kHz)
FILTER SET 1
FILTER SET 2
FILTER SET 3
FILTER SET 4
FILTER SET 5
BASS
TREBLE
917
BASS
TREBLE
1833
BASS
TREBLE
3000
BASS
TREBLE
3667
BASS
TREBLE
4333
32
38
42
49
83
125
148
172
188
345
375
689
750
146
173
201
219
402
438
804
875
167
198
230
250
459
500
919
1000
1088
1263
1375
2527
2750
5053
5500
99
2177
3562
4354
5146
44.1
48
57
115
125
230
250
459
500
2527
4134
5053
5972
63
2750
4500
5500
6500
88.2
96
115
125
230
250
5053
8269
10106
11000
20213
22000
11944
13000
23888
26000
5500
9000
176.4
192
10106
11000
16538
18000
The I2C registers that control bass and treble are:
•
•
•
•
•
•
Bass and treble bypass register (0x89–0x90, channels 1–4)
Bass and treble slew rates (0xD0)
Bass filter sets 1–5 (0xDA)
Bass filter index (0xDB)
Treble filter sets 1–5 (0xDC)
Treble filter index (0xDD)
Note that the bass and treble bypass registers (0x89–0x90) are defaulted to the bypass mode. In
order to use the bass and treble, these registers must be in the inline (or enabled) mode for each
channel using bass and treble.
1.4.9 Volume, Automute, and Mute
The TAS5504A provides individual channel and master volume controls. Each control provides an
adjustment range of 18 dB to –109 dB in 0.25-dB increments. This permits a total volume device control
range of 36 dB to –109 dB plus mute.
The TAS5504A has a master soft-mute control that can be enabled by a terminal or I2C command. The
device also has individual channel soft-mute controls that can are enabled via I2C.
The soft volume and mute update rates are programmable. The soft adjustments are performed using a
soft-gain linear update with an I2C programmable linear step size at a fixed temporal rate. The linear
soft-gain step size can be varied from 0.5 to 0.003906.
Table 1-6. Linear Gain Step Size
STEP SIZE (GAIN)
0.5
0.25
0.125
42.67
5.33
0.0625
85.34
10.67
1.33
0.03125
170.67
21.33
0.015625
341.35
42.67
0.007813
682.7
0.003906
1365.4
170.67
21.33
Time to go from 36 db to –127 dB in ms
Time to go from 18 db to –127 dB in ms
Time to go from 0 db to –127 dB in ms
10.67 21.33
1.33
0.17
2.67
0.33
85.33
0.67
2.67
5.33
10.67
28
Introduction
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4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.9.1 Automute and Mute Channel Controls
The TAS5504A has individual channel automute controls that are enabled via I2C register 0x04 bits D5
and D6 (the default setting is enabled). Two separate detectors can trigger the automute:
•
•
Input automute (I2C register 0x14): All channels are muted when all eight inputs to the TAS5504B are
less in magnitude than the input threshold value for a programmable amount of time.
Output automute (I2C register 0x15): A single channel is muted when the output of the DAP section is
less in magnitude than the input threshold value for a programmable amount of time.
The detection period and thresholds for these two detectors are the same.
This time interval is selectable via I2C from 1 ms to 110 ms The increments of time are 1, 2, 3, 4, 5, 10,
20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The
default value is mask programmable.
The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is
adjustable via I2C. The range of the input threshold adjustment is from below the LSB (bit position 0) to
below bit position 12 in a 24-bit input data word (bit positions 8 to 20 in the DSPE). This provides an input
threshold that can be adjusted for 12 to 24 bits of data. The default value is mask programmable.
DVD Data Range
CD Data Range
24-Bit Input
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
9
0
8
32 Bits in DSPE
Representation
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
7
6
5
4
3
2
1
0
Threshold Range
M0013-01
Figure 1-14. Automute Threshold
The automute state is exited when the TAS5504A receives one sample that is greater than that of the
output threshold.
The output threshold can be one of two values:
•
•
Equal to the input threshold
6 dB (one bit position) greater than the input threshold
The value for the output threshold is selectable via I2C. The default value is mask programmable.
The system latency enables the data value that is above the threshold to be preserved and output.
A mute command initiated by automute, master mute, individual I2C mute, the AM interference mute
sequence, or the bank switch mute sequence overrides an unmute command or a volume command.
While a mute command is activated, the commanded channels transition to the mute state. When a
channel is unmuted, it goes to the last commanded volume setting that has been received for that
channel.
Introduction
29
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.10 Loudness Compensation
The loudness compensation function compensates for the Fletcher-Munson loudness curves. The
TAS5504A loudness implementation tracks the volume control setting to provide spectral compensation
for weak low- or high-frequency response at low volume levels. For the volume tracking function, both
linear and log control laws can be implemented. Any biquad filter response can be used to provide the
desired loudness curve. The control parameters for the loudness control are programmable via the I2C
interface.
The TAS5504A has a single set of loudness controls for the four channels. The loudness control input
uses the maximum individual master volume (V) to control the loudness that is applied to all channels. In
192-kHz and 176.4-kHz modes, the loudness function is active only for channels 1, 2, and 4.
V
Audio In
Audio Out
Loudness
Biquad
H(z)
Loudness Function = f(V)
V
B0017-01
Figure 1-15. Loudness Compensation Functional Block Diagram
Loudness function = f (V) = G × [2 [(Log V) × LG + LO]] + O or alternatively,
Loudness function = f (V) = G × [VLG × 2LO] + O
For example, for the default values LG = –0.5, LO = 0, G = 1, and O = 0 then:
Loudness function = 1/SQRT (V) which is the recommended transfer function for loudness. So,
Audio out = (Audio in) × V + H(Z) × SQRT(V). Other transfer functions are possible.
Table 1-7. Default Loudness Compensation Parameters
LOUDNESS
TERM
DEFAULT
DATA
FORMAT
I2C SUB-
ADDRESS
DESCRIPTION
USAGE
HEX
NA
FLOAT
NA
V
Maximum volume
Gains audio
5.23
5.23
NA
NA
Log V
Log2 (maximum
volume)
Loudness function
0000 0000
0.0
H(Z)
Loudness biquad
Controls shape of
loudness curves
5.23
0x95
b0 = 0000 D513
b1 = 0000 0000
b2 = 0FFF 2AED
a1 = 00FE 5045
a2 = 0F81 AA27
b0 = 0.006503
b1 = 0
b2 = –0.006503
a1 = 1.986825
a2 = –0.986995
LG
LO
G
Gain (log space)
Offset (log space)
Gain
Loudness function
Loudness function
5.23
25.23
5.23
0x91
0x92
0x93
FFC0 0000
0000 0000
0000 0000
–0.5
0
Switch to enable
Loudness (ON = 1,
OFF = 0)
0
O
Offset
Offset
25.23
0x94
0000 0000 0000 0000
0
30
Introduction
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4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1.4.10.1 Loudness Example
Problem: Due to the Fletcher-Munson phenomena, compensation for low-frequency attenuation near 60
Hz is desirable. The TAS5504A provides a loudness transfer function with EQ gain = 6, EQ center
frequency = 60 Hz, and EQ bandwidth = 60 Hz.
Solution: Using Texas Instruments' ALE TAS5504A DSP tool, MATLAB™, or other signal-processing tool,
develop a loudness function with the following parameters:
Table 1-8. Example Loudness Function Parameters
LOUDNESS
TERM
EXAMPLES
DATA
FORMAT
I2C SUB-
ADDRESS
DESCRIPTION
USAGE
HEX
FLOAT
H(Z)
Loudness biquad
Controls shape of
loudness curves
5.23
0x95
b0 = 0000 8ACE
b1 = 0000 0000
b2 = FFFF 7532
a1 = FF01 1951
a2 = 007E E914
b0 = 0.004236
b1 = 0
b2 = –0.004236
a1 = –1.991415
a2 = 0.991488
LG
LO
G
Gain (log space)
Offset (log space)
Gain
Loudness function
Loudness function
5.23
25.23
5.23
0x91
0x92
0x93
FFC0 0000
0000 0000
0080 0000
–0.5
0
Switch to enable
loudness (ON = 1,
OFF = 0)
1
O
Offset
Offset
25.23
0x94
0000 0000
0
See Figure 1-16 for the resulting loudness function at different gains.
20
10
0
−10
−20
−30
−40
10
100
1k
f − Frequency − Hz
10k
20k
G001
Figure 1-16. Loudness Example Plots
1.4.11 Dynamic Range Control (DRC)
The DRC provides both compression and expansion capabilities over three separate and definable
regions of audio signal levels. Programmable threshold levels set the boundaries of the three regions.
Within each of the three regions, a distinct compression or expansion transfer function can be established,
and the slope of each transfer function is determined by programmable parameters. The offset (boost or
cut) at the two boundaries defining the three regions can also be set by programmable offset coefficients.
The DRC implements the composite transfer function by computing a 5.23-format gain coefficient from
each sample output from the rms estimator. This gain coefficient is then applied to a mixer element,
whose other input is the audio data stream. The mixer output is the DRC-adjusted audio data.
The TAS5504A has two distinct DRC blocks. DRC1 services channels 1–3. This DRC computes rms
Introduction
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estimates of the audio data streams on all channels that it controls. The estimates are then compared on
a sample-by-sample basis and the larger of the estimates is used to compute the compression/expansion
gain coefficient. The gain coefficient is then applied to the appropriate channel audio stream. DRC2
services only channel 4. This DRC also computes an rms estimate of the signal level on channel 4 and
this estimate is used to compute the compression/expansion gain coefficient applied to the channel-4
audio stream.
All the TAS5504A default values for DRC can be used except for the DRC1 decay and DRC2 decay.
Table 1-9 shows the recommended time constants and their hexadecimal values. If the user wants to
implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker
equalization (ALE) tool available from Texas Instruments. The ALE tool allows the user to select the DRC
transfer function graphically. It then outputs the TAS5504A hexadecimal coefficients for download to the
TAS5504A.
Table 1-9. DRC Recommended Changes From TAS5504A Defaultss
I2C
REGISTER FIELDS
RECOMMENDED TIME
CONSTANT (ms)
RECOMMENDED
HEX VALUE
DEFAULT HEX
SUBADDRESS
0x98
0x9C
DRC1 energy
DRC1 (1 – energy)
DRC1 attack
5
5
2
5
5
2
0000 883F
007F 77C0
0000 883F
007F 77C0
0001 538F
007E AC70
0000 883F
007F 77C0
0000 883F
007F 77C0
0001 538F
007E AC70
0000 883F
007F 77C0
0000 883F
007F 77C0
0000 00AE
007F FF51
0000 883F
007F 77C0
0000 883F
007F 77C0
0000 0056
003F FFA8
DRC1 (1 – attack)
DRC1 decay
DRC1 (1 – decay)
DRC2 energy
0x9D
0xA1
DRC2 (1 – energy)
DRC2 attack
DRC2 (1 – attack)
DRC2 decay
DRC2 (1 – decay)
Recommended DRC setup flow if the defaults are used:
1. After power up, load the recommended hexadecimal value for DRC1 and DRC2 decay and (1 –
decay). See Table 1-9.
2. Enable either the pre-volume or post-volume DRC using I2C registers 0x96 and 0x97. Note that to
avoid a potential timing problem, a 10-ms delay is required between a write to 0x96 and a write to
0x97.
Recommended DRC set-up flow if the DRC design uses values different from the defaults:
1. After power up, load all DRC coefficients per the DRC design.
2. Enable either the pre-volume or post-volume DRC.
Figure 1-17 shows the positioning of the DRC block in the TAS5504A processing flow. As seen, the DRC
input can come from either before or after soft-volume control and loudness processing.
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Master
Volume
Channel Volume
Max
Volume
Bass and Treble
Bypass
DRC
Bypass
Loudness
7
Bass
and
Treble
Biquads
in
From Input Mixer
To Output Mixer
Series
Pre-
Post-
DRC
Inline
Volume Volume
Bass
and
Treble
Inline
DRC
B0016-02
Figure 1-17. DRC Positioning in TAS5504A Processing Flow
Figure 1-18 illustrates a typical DRC transfer function.
Region
0
Region
1
Region
2
k2
k1
1:1 Transfer Function
Implemented Transfer Function
k0
O2
O1
T1
T2
DRC Input Level
M0014-01
Figure 1-18. DRC Transfer Function Structure
The three regions shown in Figure 1-18 are defined by three sets of programmable coefficients:
•
•
•
Thresholds T1 and T2—define region boundaries.
Offsets O1 and O2—define the DRC gain coefficient settings at thresholds T1 and T2, respectively.
Slopes k0, k1, and k2—define whether compression or expansion is to be performed within a given
region. The magnitudes of the slopes define the degree of compression or expansion to be performed.
The three sets of parameters are all defined in logarithmic space and adhere to the following rules:
•
The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value
then have negative values in logarithmic (dB) space.
•
The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word
format used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial
data received at the serial audio receive port by adding 8 bits of headroom above the 32-bit word and
8 bits of computational precision below the 32-bit word. If the audio processing steps between the SAP
input and the DRC input result in no accumulative boost or cut, the DRC operates on the 8 bits of
headroom and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value)
audio sample (0x7FFF FFFF) is seen at the DRC input as a –48-dB sample (8 bits × –6 dB/bit = –48
dB).
Introduction
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•
Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to
the rms value of the data in the DRC. Zero-valued threshold settings reference the maximum-valued
rms input into the DRC, and negative-valued thresholds reference all other rms input levels.
Positive-valued thresholds have no physical meaning and are not allowed. In addition, zero-valued
threshold settings are not allowed.
Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of
the DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space.
This means that the threshold settings must be programmed as 48-bit (25.23 format) numbers.
CAUTION
Zero-valued and positive-valued threshold settings are not allowed and cause
unpredictable behavior if used.
•
•
Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain
coefficient at the threshold points T1 and T2, respectively. Positive offsets are defined as cuts, and
thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit
(25.23-format) numbers.
Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given
region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit
(5.23-format) numbers.
1.4.11.1 DRC Implementation
The three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient
computation engine, and (3) an attack/decay controller. DRC1 applies to channels 1–3, and DRC2 applies
only to channel 4. DRC1 uses I2C registers 0x98–0x9C and DRC2 uses I2C registers 0x9D–0xA1.
•
RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into
the DRC. For DRC1 (Ch1–Ch3), the individual channel estimates are computed. The outputs of the
estimators are then compared, sample-by-sample, and the larger-valued sample is forwarded to the
compression/expansion coefficient computation engine.
Two programmable parameters (I2C 0x98), E and (1 – E), set the effective time window over which the
rms estimate is made. For the DRC1 block, the programmable parameters apply to all rms estimators.
The time window over which the rms estimation is computed can be determined by:
*1
t
+
window
f
ȏn(1 * E)
S
•
•
Compression/expansion coefficient computation—This DRC element converts the output of the rms
estimator to a logarithmic number, determines the region where the input resides, and then computes
and outputs the appropriate coefficient to the attack/decay element. Seven programmable
parameters—T1, T2, O1, O2, k0, k1, and k2—define the three compression/expansion regions
implemented by this element.
Attack/decay control—This DRC element controls the transition time of changes in the coefficient
computed in the compression/expansion coefficient computation element. Four programmable
parameters define the operation of this element. Parameters D and (1 – D) set the decay or release
time constant to be used for volume boost (expansion). Parameters A and (1 – A) set the attack time
constant to be used for volume cuts. The transition time constants can be determined by:
*1
ȏn(1 * A)
*1
ȏn(1 * D)
t +
t +
d
a
f
f
S
S
Figure 1-19 shows how the TAS5504A attack and decay are defined. Note that this is opposite of some
definitions of attack and decay.
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t = –1/[f ´ ℓn(1 – D)]
d
t = –1/[f ´ ℓn(1 – A)]
a
S
S
Decay
Attack
Time
T0115-01
Figure 1-19. TAS5504A Attack and Decay Definition
1.4.11.2 Compression/Expansion Coefficient Computation Engine Parameters
Seven programmable parameters are assigned to each DRC block: two threshold parameters—T1 and
T2, two offset parameters—O1 and O2, and three slope parameters—k0, k1, and k2. The threshold
parameters establish the three regions of the DRC transfer curve; the offsets anchor the transfer curve by
establishing known gain settings at the threshold levels; and the slope parameters define whether a given
region is a compression or an expansion region.
The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers.
These mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the
audio data in the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input
and the DRC. The selection of threshold values must take the gain (attenuation) of these mixers into
account. The DRC implementation examples that follow illustrate the effect these mixers have on
establishing the threshold settings.
T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes
the boundary between the mid-volume region and the low-volume region. Both thresholds are set in
logarithmic space, and which region is active for any given rms estimator output sample is determined by
the logarithmic value of the sample.
Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost
(> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If
O2 = 0 dB, the value of the derived gain coefficient is 1 (0x0080 0000 in 5.23 format). k2 is the slope of
the DRC transfer function for rms input levels above T2, and k1 is the slope of the DRC transfer function
for rms input levels below T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that
there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC
parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no
discontinuity is desired at T1, the value for the offset term O1 must obey the following equation.
Introduction
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4-Channel Digital Audio PWM Processor
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SLES169–FEBRUARY 2006
O1No Discontinuity = |T1 – T2| × k1 + O2 For ( |T1| ≥ |T2| )
T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If
the user chooses to select a value of O1 that does not obey the preceding equation, a discontinuity at T1
is realized.
Going down in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this
input level, the offset of the transfer function curve from the 1:1 transfer curve does not equal O1, a
discontinuity occurs at this input level as the transfer function is snapped to the offset called for by O1. If
no discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at the
input level T1 is offset from the 1:1 transfer curve by the value O1. The examples that follow illustrate both
continuous and discontinuous transfer curves at T1.
Going down in volume from T1, starting at the offset level O1, the slope k0 defines the
compression/expansion activity in the lower region of the DRC transfer curve.
1.4.11.2.1 Threshold Parameter Computation
For thresholds,
TdB = –6.0206TINPUT = –6.0206TSUB_ADDRESS_ENTRY
If, for example, it is desired to set T1 = –64 dB, then the subaddress entry required to set T1 to –64 dB is:
64
*6.0206
T1
+
+ 10.63
SUB_ADDRESS_ENTRY
T1 is entered as a 48-bit number in 25.23 format. Therefore:
T1 = 10.63 = 0 1010.1010 0001 0100 0111 1010 111
= 0x0000 0550 A3D7 in 25.23 format
1.4.11.2.2 Offset Parameter Computation
The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An
equivalent statement is that offsets represent the departure of the actual transfer function from a 1:1
transfer at the threshold point. Offsets are 25.23-formatted, 48-bit logarithmic numbers. They are
computed by the following equation.
O
) 24.0824 dB
DESIRED
6.0206
O
+
INPUT
Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive
numbers. For example, to achieve a boost of 21 dB at threshold T1, the I2C coefficient value entered for
O1 must be:
*21 dB ) 24.0824 dB
O1
+
+ 0.51197555
INPUT
6.0206
+ 0.1000 0011 0001 1101 0100
+ 0x0000 0041 886A in 25.23 format
More examples of offset computations are included in the following examples.
1.4.11.2.3 Slope Parameter Computations
In developing the equations used to determine the subaddress of the input value required to realize a
given compression or expansion within a given region of the DRC, the following convention is adopted.
DRC transfer = Input increase : Output increase
If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the
DRC, a 1 : n expansion is being performed. If the DRC realizes a 1-dB increase in output level for every
n-dB increase in the rms value of the audio into the DRC, an n : 1 compression is being performed.
For 1 : n expansion, the slope k can be found by:
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k = n – 1
For n : 1 compression, the slope k can be found by:
1
k + * 1
n
In both expansion (1 : n) and compression (n : 1), n is implied to be greater than 1. Thus, for expansion:
1
k + * 1
n
k = n – 1 means k > 0 for n > 1. Likewise, for compression,
it appears that k must always lie in the range k > –1.
means –1 < k < 0 for n > 1. Thus,
The DRC imposes no such restriction, and k can be programmed to values as negative as –15.999. To
determine what results when such values of k are entered, it is first helpful to note that the compression
and expansion equations for k are actually the same equation. For example, a 1 : 2 expansion is also a
0.5 : 1 compression.
1
0.5
0.5 : 1 compression å k +
*
1 + 1
1 : 2 expansion å k + 2 * 1 + 1
As can be seen, the same value for k is obtained either way. The ability to choose values of k less than –1
allows the DRC to implement negative-slope transfer curves within a given region. Negative-slope transfer
curves are usually not associated with compression and expansion operations, but the definition of these
operations can be expanded to include negative-slope transfer functions. For example, if k = –4
1
n
1
3
Compression equation: k + * 4 +
* 1 å n + *
å * 0.3333 : 1 compression
Expansion equation: k + * 4 + n * 1 å n + * 3 å 1 : * 3 expansion
With k = –4, the output decreases 3 dB for every 1-dB increase in the rms value of the audio into the
DRC. As the input increases in volume, the output decreases in volume.
1.4.12 Output Mixer
The TAS5504A provides a 4 × 2 output mixer for channels 1 and 2. For channels 3 and 4, the TAS5504A
provides a 4 × 3 output mixer. These mixers allow each output to be any ratio of any two (three)
signal-processed channels. The control parameters for the output crossbar mixer are programmable via
the I2C interface. All of the TAS5504A features are available when the 8 × 2 and 8 × 3 output mixers are
configured in the pass-through output mixer configuration, where the audio data from each DAP channel
maps directly to the corresponding PWM channel (i.e., DAP channel 1 to PWM channel 1, etc).
It is recommended to use the default settings for the output mixers. However, If the DAP channels are
remapped from the default certain limitations must be considered:
•
•
Individual channel mute should not be used.
The sum of the minimum channel volume and master colume should not be below –109 dB.
Introduction
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4-Channel Digital Audio PWM Processor
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SLES169–FEBRUARY 2006
Gain Coefficient
28
48
Select
Output
N
48
Gain Coefficient
28
48
48
Select
Output
1 or 2
Output
N
Gain Coefficient
28
48
Select
Output
N
48
Gain Coefficient
28
48
48
Select
Output
3 or 4
Output
N
48
Gain Coefficient
28
48
Select
Output
N
M0011-04
Figure 1-20. Output Mixers
1.4.13 PWM
The TAS5504A has four channels of high-performance digital PWM modulators that are designed to drive
switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied load)
configurations. The TAS5504A device uses noise-shaping and sophisticated error correction algorithms to
achieve high power efficiency and high-performance digital audio reproduction. The TAS5504A uses an
AD1 PWM modulation combined with a 5th-order noise shaper to provide a 102-dB SNR from 20 Hz to
20 kHz.
The PWM section accepts 32-bit PCM data from the DAP and outputs four PWM audio output channels.
The TAS5504A PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the
TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone does not
operate while the back-end drive channels are operating. The headphone is enabled via a headphone
select terminal or I2C command.
The PWM section has individual channel dc-blocking filters that can be enabled and disabled. The filter
cutoff frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled
and disabled.
The PWM section also contains the power-supply volume control (PSVC) PWM.
The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
38
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4-Channel Digital Audio PWM Processor
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SLES169–FEBRUARY 2006
•
Up to 8× oversampling.
–
–
–
8× at fS = 44.1 kHz, 48 kHz, 32 kHz, 38 kHz
4× at fS = 88.2 kHz, 96 kHz
2× at fS = 176.4 kHz, 192 kHz
•
•
•
•
•
5th-order noise shaping
102-dB dynamic range 0–20 kHz (TAS5504A + TAS5111 system measured at speaker terminals)
THD < 0.01%
Adjustable maximum modulation limit of 93.8% to 99.2%
3.3-V digital signal
1.4.13.1 DC Blocking (High-Pass Enable/Disable)
Each input channel incorporates a 1st-order digital high-pass filter to block potential dc components. The
filter –3-dB point is approximately 0.89 Hz at the 44.1-kHz sampling rate. The high-pass filter can be
enabled and disabled via I2C system control register 1 (0x03 bit D7). The default setting is 1 (high-pass
filter enabled).
1.4.13.2 De-Emphasis Filter
For audio sources that have been preemphasized, a precision 50-µs/15-µs de-emphasis filter is provided
to support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 1-21 shows a graph of the
de-emphasis filtering characteristics. De-emphasis is set using 2 bits in the system control register.
0
De-emphasis
−10
3.18 (50 µs)
10.6 (15 µs)
f – Frequency – kHz
M0015-01
Figure 1-21. De-Emphasis Filter Characteristics
1.4.13.3 Power-Supply Volume Control (PSVC)
The TAS5504A supports volume control by both conventional digital gain/attenuation and by a
combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs
the analog volume control function. The benefits of using PSVC are reduced idle channel noise, improved
signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at
reduced power levels. The PSVC is enabled via I2C. When enabled, the PSCV provides a PWM output
that is filtered to provide a reference voltage for the power supply. The power-supply adjustment range
can be set for –12, –18, or –24 dB, to accommodate a range of variable power-supply designs.
Figure 1-22 and Figure 1-23 show how power supply and digital gains can be used together.
The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to
match the PSVC volume transfer function.
Introduction
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4-Channel Digital Audio PWM Processor
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SLES169–FEBRUARY 2006
100
10
Digital Gain
1
0.1
Power-Supply Gain
0.01
0.001
0.0001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
Desired Gain − Linear
G003
Figure 1-22. Power Supply and Digital Gains (Log Space)
30
20
10
Digital Gain
0
−10
−20
−30
−40
−50
−60
Power-Supply Gain
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
Desired Gain − dB
G002
Figure 1-23. Power Supply and Digital Gains (Linear Space)
1.4.13.4 AM Interference Avoidance
Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments patented
AM interference avoidance circuit provides a flexible system solution for a wide variety of digital audio
architectures. During AM reception, the TAS5504A adjusts the radiated emissions to provide an
emission-clear zone for the tuned AM frequency. The inputs to the TAS5504A for this operation are the
tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected.
40
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4-Channel Digital Audio PWM Processor
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Analog
Receiver
ADC
Audio
TAS5504A
TAS5111
TAS5111
TAS5111
TAS5111
PCM1802
DSP
Audio DSP Provides the
Master and Bit Clocks
Digital
Audio
TAS5504A
TAS5111
TAS5111
TAS5111
TAS5111
Receiver
DSP
The Digital Receiver or the Audio DSP
Provides the Master and Bit Clocks
B0018-04
Figure 1-24. Block Diagrams of Typical Systems Requiring TAS5504A
Automatic AM Interference Avoidance Circuit
2
TA5504A Controls and Status
The TAS5504A provides control and status information from both the I2C registers and device pins.
This section describes some of these controls and status functions. The I2C summary and detailed
register descriptions are contained in Section 5 and Section 6 of this document, respectively.
2.1 I2C Status Registers
The TAS5504A has two status registers that provide general device information. These are the general
status register 0 (0x01) and the error status register (0x02).
2.1.1 General Status Register (0x01)
•
•
Device identification code
Clip indicator – The TAS5504A has a clipping indicator. Writing to the register clears the indicator.
2.1.2 Error Status Register (0x02)
•
•
No internal errors (the valid signal is high)
A clock error has occurred – These are sticky bits that are cleared by writing to the register.
–
–
–
–
LRCLK error – When the number of MCLKs per LRCLK is incorrect
SCLK error – When the number of SCLKS per LRCLK is incorrect
Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
PLL phase-lock error
•
This error status register is normally used for system development only.
TA5504A Controls and Status
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2.2 TAS5504A Pin Controls
The TAS5504A provides a number of terminal controls to manage the device operation. These controls
are:
•
•
•
•
•
RESET
PDN
BKND_ERR
HP_SEL
MUTE
2.2.1 Reset (RESET)
The TAS5504A is placed in the reset mode by setting the RESET terminal low or by the power-up-reset
circuitry when power is applied.
RESET is an asynchronous control signal that restores the TAS5504A to the hard-mute state (M-state).
Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device
reset without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state.
During reset, all I2C and serial data bus operations are ignored.
Table 2-1 shows the device output signals while RESET is active.
Table 2-1. Device Outputs During Reset
SIGNAL
Valid
SIGNAL STATE
Low
PWM P-outputs
PWM M-outputs
SDA
Low (M-State)
Low (M-State)
Signal input (not driven)
Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading
edge) of RESET cannot be avoided. However, the transition from the M-state to the operational state is
performed using a quiet start-up sequence to minimize noise. This control uses the PWM reset and
unmute sequence to shut down and start up the PWM. A detailed description of these sequences is
contained in the PWM section. If a completely quiet reset or power-down sequence is desired, MUTE
should be applied before applying RESET.
The rising edge of the reset pulse begins device initialization before the transition to the operational mode.
During device initialization, all controls are reset to their initial states. Table 2-2 shows the default control
settings following a reset.
Table 2-2. Values Set During Reset
CONTROL
Output mixer configuration
High pass
SETTING
0xD0 bit 30 = 0 (remapped output mixer configuration)
Enabled
Unmute from clock error
Input automute
Hard unmute
Enabled
Output automute
Enabled
De-emphasis
De-emphasis disabled
I2S, 24-bit
Serial data interface format
Individual channel mute
Automute delay
No channels are muted
5 ms
Automute threshold 1
< 8 bits
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TA5504A Controls and Status
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4-Channel Digital Audio PWM Processor
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SLES169–FEBRUARY 2006
Table 2-2. Values Set During Reset (continued)
CONTROL
Automute threshold 2
SETTING
Same as automute threshold 1
Modulation limit
Maximum modulation limit of 97.7% (NOTE: some power
stages)
Volume and mute update rate
Treble and bass slew rate
Bank switching
Volume ramp 88.2 ms
Update every 1.31 ms
Manual bank selection is enabled
Biquad coefficients
Set to all pass
Input mixer coefficients
Output mixer coefficients
Subwoofer sum into Ch1 and Ch2
Ch1 and Ch2 sum in subwoofer
Bass and treble bypass/inline
DRC bypass/inline
Input N –> Channel N, no attenuation
Channel N –> Output N, no attenuation
Gain of 0
Gain of 0
Bypass
Bypass
DRC
DRC disabled, default values
Master volume
Mute
Individual channel volumes
All bass and treble indexes
Treble filter sets
0 dB
0x12 neutral
Filter set 3
Bass filter sets
Filter set 3
Loudness
Loudness disabled, default values
AM interference enable
AM interference IF
Disabled
455 kHz
1
AM interference select sequence
Tuned frequency and mode
0000, BCD
After the initialization time, the TAS5504A starts the transition to the operational state with the master
volume set at mute.
Because the TAS5504A has an external crystal time base, following the release of reset, the TAS5504A
sets the MCLK and data rates and performs the initialization sequences. The PWM outputs are held at a
mute state until the master volume is set to a value other than mute via I2C.
2.2.2 Power Down (PDN)
The TAS5504A can be placed into the power-down mode by holding the PDN terminal low. When
power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to
full attenuation (there is no ramp down). This control uses the PWM mute sequence that provides a
low-click-and-pop transition to the M-state. A detailed description of the PWM mute sequence is contained
in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power-down state.
To initiate the power-up sequence requires MCLK to be operational and the TAS5504A to receive five
MCLKs prior to the release of PDN.
As long as the PDN terminal is held low, the device is in the power-down state with the PWM outputs in
the M-state. During power down, all I2C and serial data bus operations are ignored. Table 2-3 shows the
device output signals while PDN is active.
Table 2-3. Device Outputs During Power Down
SIGNAL
SIGNAL STATE
Valid
Low
TA5504A Controls and Status
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4-Channel Digital Audio PWM Processor
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Table 2-3. Device Outputs During Power Down (continued)
SIGNAL
PWM P-outputs
PWM M-outputs
SDA
SIGNAL STATE
M-state = low
M-state = low
Signal input
PSVC
M-state = low
Following the application of PDN, the TAS5504A does not perform a quiet shutdown to prevent clicks and
pops produced during the application (the leading edge) of this command. The application of PDN
immediately performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE
before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and
the I2C register settings.
The crystal time base allows the TAS5504A to determine the CLK rates. Once these rates are determined,
the TAS5504A unmutes the audio.
2.2.3 Back-End Error (BKND_ERR)
Back-end error is used to provide error management for back-end error conditions. Back-end error is a
level-sensitive signal. Back-end error can be initiated by bringing the BKND_ERR terminal low for a
minimum of five MCLK cycles. When BKND_ERR is brought low, the PWM sets all channels into the
PWM back-end error state. This state is described in the PWM section. Once the back-end error
sequence is initiated, a delay of 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5504A begins normal operation. Back-end error does not
affect other PWM modulator operations
When BKND_ERR is low, the TAS5504A brings the PWM outputs 1–4 to a back-end error state, while not
affecting any other internal settings or operations. Table 2-4 shows the device output signal states during
back-end error.
Table 2-4. Device Outputs During Back-End Error
SIGNAL
Valid
SIGNAL STATE
Low
PWM P-outputs
PWM M-outputs
HPPWM P-outputs
HPPWM M-outputs
SDA
M-state = low
M-state = low
M-state - low
M-state - low
Signal input (not driven)
2.2.4 Speaker/Headphone Selector (HP_SEL)
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output
receives the processed data output from DAP and PWM channels 1 and 2.
When low, the headphone output is enabled. In this mode, the speaker outputs are disabled. When high,
the speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level results in a state change sequence using soft mute to the M-state for both
speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 is defined by the headphone configuration
register. When HP_SEL is high, the channel 1 and 2 configuration registers define the configuration of
channels 1 and 2.
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2.2.5 Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS5504A has both a master and individual channel mute commands. A terminal
also is provided for the master MUTE. The active-low master mute I2C register and the MUTE terminal are
logically ORed together. If either is set to low, a mute on all channels is performed. The master mute
command operates on all channels.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master mute terminal is used to support a variety of other operations in the TAS5504A, such as
setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A
mute command by the master mute terminal, individual I2C mute, the AM interference mute sequence, the
bank-switch mute sequence, or automute overrides an unmute command or a volume command. While a
mute is active, the commanded channels are placed in a mute state. When a channel is unmuted, it goes
to the last commanded volume setting that has been received for that channel.
2.3 Device Configuration Controls
The TAS5504A provides a number of system configuration controls that are set at initialization and
following a reset.
•
•
•
•
•
•
•
•
•
Channel configuration
Headphone configuration
Audio system configurations
Recovery from clock error
Power-supply volume-control enable
Volume and mute update rate
Modulation index limit
Master clock and data-rate controls
Bank controls
2.3.1 Channel Configuration Registers
In order for the TAS5504A to have full control of the power stages, registers 0x05, 0x06, 0x0B, and 0x0C
must be programmed to reflect the proper power stage and how each one should be controlled. Channel
configuration registers consist of four registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling
during start up, mute/unmute, shutdown, and error recovery. The TAS5504A must select the sequence
that gives the best click and pop performance and insure that the bootstrap capacitor is charged correctly
during start-up. This sequence depends on which power stage is present at the TAS5504A output.
Table 2-5. Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C)
BIT
DESCRIPTION
D7 Enable/disable error recovery sequence. In case the BKND_ERR pin is pulled low, this register determines if this channel is to follow
the error recovery sequence or to continue with no interruption.
D6 Determines if the power stage needs the TAS5504A VALID pin to go low to reset the power stage. Some power stages can be reset
by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is shared for
power stages. This provides better control of each power stage.
D5 Determines if the power stage needs the TAS5504A VALID pin to go low to mute the power stage. Some power stages can be
muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is shared
for power stages. This provides better control of each power stage.
D4 Inverts the PWM output. Inverting the PWM output can be an advantage if the power-stage input pins are opposite the TAS5504A
PWM pinout. This makes routing on the PCB easier. To keep the phase of the output, the speaker terminals also must be inverted.
D3 When using the TAS5182 power stage, this bit must be set.
D2 Can be used to handle click and pop for some applications.
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Table 2-5. Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C) (continued)
BIT
DESCRIPTION
D1 This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of
both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0 Not used
Table 2-6 lists the optimal setting for each output stage configuration. Note that the default value is
applicable in all configurations except the TAS5182 SE/BTL configuration.
Table 2-6. Recommended TAS5504A Configurations for Texas Instruments Power Stages
DEVICE
ERROR RECOVERY
RES
CONFIGURATION
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
BTL
SE
1
1
1
0
0
0
0
0
TAS5111
(default)
BTL
SE
0
1
1
0
0
0
0
0
AUT
RES
AUT
RES
0
1
1
0
0
0
0
0
BTL
SE
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
TAS5112
TAS5182
BTL
SE
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
BTL
SE
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
RES: The output stage requires VALID to go low to recover from a shutdown.
AUT: The power stage can autorecover from a shutdown.
BTL: Bridge-tied load configuration
SE: Single-ended configuration
2.3.2 Headphone Configuration Registers
The headphone configuration controls are identical to the speaker configuration controls. The headphone
configuration control settings are used in place of the speaker configuration control settings for channels 1
and 2 when the headphones are selected. In reality, however, only one configuration setting is used for
headphones, and that is the default setting.
2.3.3 Audio System Configurations
The TAS5504A can be configured to comply with various audio systems.
The audio system configuration is set in the general control register (0xE0). Bits D31–D4 must be zero
and D0 is don't care.
D3—Must always be 0 (default). Note that the subwoofer cannot be used as lineout when the PSVC is
enabled (D3 is a write-only bit).
D2—Enable/disable power-supply volume control
D3–D1 must be configured for the audio system in the application, as shown in Table 2-7.
Table 2-7. Audio System Configuration (General Control Register 0xE0)
AUDIO SYSTEM
DEFAULT
D31–D4
D3
0
D2
0
D1
0
D0
X
0
0
0
0
3.1 channels NOT using PSVC
4 channels using PSVC
3.1 channels using PSVC
0
0
1
X
0
1
1
X
0
1
1
X
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2.3.4 Recovery from Clock Error
The TAS5504A can be set either to perform a volume ramp-up during the recovery sequence of a clock
error or simply to come up in the last state (or desired state if a volume or tone update was in progress).
This feature is enabled via I2C system control register 0x03.
2.3.5 Power-Supply Volume-Control Enable
The power-supply volume control (PSVC) can be enabled and disabled via I2C register 0xE0. The
subwoofer PWM output is always controlled by the PSVC. When using PSVC, the subwoofer cannot be
used as lineout.
2.3.6 Volume and Mute Update Rate
The TAS5504A has fixed soft-volume and mute-ramp durations. The ramps are linear. The soft-volume
and mute-ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of
steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
•
•
•
In normal speed, the update rate is 1 step every 4/fS seconds.
In double speed, the update is 1 step every 8/fS seconds.
In quad speed, the update is 1 step every 16/fS seconds.
Because of processor loading, the update rate can increase for some increments by 1/fS to 3/fS. However,
the variance of the total time to go from 18 dB to mute is less than 25%.
Table 2-8. Volume Ramp Rates in ms
NUMBER OF STEPS
SAMPLE RATE (kHz)
44.1, 88.2, 176.4
32, 48, 96, 192
42.67 ms
512
1024
2048
46.44 ms
92.88 ms
185.76 ms
85.33 ms
170.67 ms
2.3.7 Modulation Index Limit
Pulse-width modulation (PWM) is a linear function of the audio signal. When the audio signal is 0, the
PWM is 50%. When the audio signal increases toward full scale, the PWM increases toward 100%. For
negative signals, the PWM falls below 50% towards 0%.
However, there is a limit to the maximum modulation possible. During the off-time period, the power stage
connected to the TAS5504A output must get ready for the next on-time period. The maximum possible
modulation is then set by the power-stage requirements. The modulation index limit setting is 97.7%;
however, some power stages require a lower modulation index limit. See the applicable power-stage data
sheet for details on setting the modulation index limit.
2.4 Master Clock and Serial Data Rate Controls
The TAS5504A functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5504A to detect MCLK and the data rate automatically.
The MCLK frequency can be 64 × fS, 128 × fS, 196 × fS, 256 × fS, 384 × fS, 512 × fS, or 768 × fS.
The TAS5504A operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5504A accepts a
64 × fS SCLK rate and a 1 × fS LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last reset, the TAS5504A
senses a clock error and resynchronizes the clock timing.
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The clock and serial data interface have several control parameters:
•
•
•
MCLK ratio (64 fS, 128 fS, 196 fS, 256 fS, 384 fS, 512 fS, or 768 fS) – I2C parameter
Data rate (32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz) – I2C parameter
AM mode enable/disable – I2C parameter
During AM interference avoidance, the clock control circuitry uses three other configuration inputs:
•
•
•
Tuned AM frequency (for AM interference avoidance) (550 kHz–1750 kHz) – I2C parameter
Frequency set select (1–4) – I2C parameter
Sample rate – I2C parameter or autodetected
2.4.1 PLL Operation
The TAS5504A uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital
PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL
provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz
crystal provides the input reference clock for the DPLL. The crystal provides a time base to support a
number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions.
The crystal time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5504A can receive and store I2C commands and provide status.
2.5 Bank Controls
The TAS5504A permits the user to specify and assign sample-rate-dependent parameters for biquad,
loudness, DRC, and tone in one of three banks that can be manually selected or selected automatically
based on the data sample rate. Each bank can be enabled for one or more specific sample rates via I2C
bank control register 0x40. Each bank set holds the following values:
•
Coefficients for seven biquads (7 × 5 = 35 coefficients) for each of the four channels (registers
0x51–0x88)
•
•
•
•
•
•
•
Coefficients for one loudness biquad (register 0x95)
DRC1 energy and (1 – energy) values (register 0x98)
DRC1 attack, (1 – attack), decay, (1 – decay) values (register 0x9C)
DRC2 energy and (1 – energy) values (register 0x9D)
DRC2 attack, (1 – attack), decay, (1 – decay) values (register 0xA1)
Five bass filter-set selections (register 0xDA)
Five treble filter-set selections (register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is
used, bank 2 and bank 3 must be programmed on power up because the default values are all zeroes. If
bank switching is used and bank 2 and bank 3 are not programmed correctly, then the output of the
TAS5504A could be muted when switching to those banks.
2.5.1 Manual Bank Selection
The three bank selection bits of the bank control register allow the appropriate bank to be manually
selected (000 = bank 1, 001 = bank 2, 010 = bank 3). In the manual mode, when a write occurs to the
biquad, DRC, or loudness coefficients, the currently selected bank is updated. If audio data is streaming to
the TAS5504A during a manual bank selection, the TAS5504A first performs a mute sequence, then
performs the bank switch, and finally restores the volume using an unmute sequence.
A mute command initiated by the bank-switch mute sequence overrides an unmute command or a volume
command. While a mute is active, the commanded channels are muted. When a channel is unmuted, the
volume level goes to the last commanded volume setting that has been received for that channel.
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If MCLK or SCLK is stopped, the TAS5504A performs a bank-switch operation. If the clocks should start
up once the manual bank-switch command has been received, the bank switch operation is performed
during the 5-ms silent start sequence.
2.5.2 Automatic Bank Selection
To enable automatic bank selection, a value of 3 is written into the bank selection bits of the bank control
register. Banks are associated with one or more sample rates by writing values into the bank 1 or bank 2
data-rate selection registers. The automatic base selection is performed when a frequency change is
detected according to the following scheme:
1. The system scans bank-1 data rate associations to see if the bank 1 is assigned for that data rate.
2. If bank 1 is assigned, then the bank-1 coefficients are loaded.
3. If bank 1 is not assigned, the system scans the bank 2 to see if bank 2 is assigned for that data rate.
4. If bank 2 is assigned, then the bank-2 coefficients are loaded.
5. If bank 2 is not assigned, the system loads the bank-3 coefficients.
The default is that all frequencies are enabled for bank 1. This default is expressed as a value of all 1s in
the bank-1 autoselection byte and all 0s in the bank-2 autosection byte.
2.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled
In automatic mode, if a write occurs to the tone, EQ, DRC, or loudness coefficients, the bank that is
written to is the current bank.
2.5.3 Bank Set
Bank set is used to provide a secure way to update the bank coefficients in both the manual and
automatic switching modes without causing a bank switch to occur. Bank-set mode does not alter the
current bank register mapping. It simply enables any bank’s coefficients to be updated while inhibiting any
bank switches from taking place. In manual mode, this enables the coefficients to be set without switching
banks. In automatic mode, this prevents a clock error or data-rate change from corrupting a bank
coefficient write.
To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the
bank control register. This enables the tone, EQ, DRC, and loudness coefficient values of bank 1, 2, or 3,
respectively, to be updated.
Once the coefficients of the bank have been updated, the bank selection bits are then returned to the
desired manual or automatic bank selection mode.
2.5.4 Bank-Switch Timeline
After a bank switch is initiated (manual or automatic), no I2C writes to the TAS5504A should occur before
a minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.
2.5.5 Bank Switching Example 1
Problem: The audio unit containing a TAS5504A needs to handle different audio formats with different
sample rates. Format #1 requires fS = 32 kHz, format #2 requires fS = 44.1 kHz, and format #3 requires fS
= 48 kHz. The sample-rate dependent parameters in the TAS5504A require different coefficients and data,
depending on the sample rate.
Strategy: Use the TAS5504A bank switching feature to allow for managing and switching three banks
associated with the three sample rates, 32 kHz (bank 1), 44.1 kHz (bank 2), and 48 kHz (bank 3).
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
1. Generate bank-related coefficients for sample rates of 32 kHz, 44.1 kHz, and 48 kHz and include the
same in the microprocessor-based TAS5504A I2C firmware.
2. On TAS5504A power up or reset, the microprocessor runs the following TAS5504A initialization code:
TA5504A Controls and Status
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a. Update bank 1 (write 0x0004 8040 to register 0x40).
b. Write bank-related I2C registers with appropriate values for bank 1.
c. Write bank 2 (write 0x0005 8040 to register 0x40).
d. Load bank-related I2C registers with appropriate values for bank 2.
e. Write bank 3 (write 0x0006 8040 to register 0x40).
f. Load bank-related I2C registers with appropriate values for bank 3.
g. Select automatic bank switching (write 0x0003 8040 to register 0x40).
3. Now when the audio media changes, the TAS5504A automatically detects the incoming sample rate
and automatically switches to the appropriate bank.
In this example, any sample rates other then 32 kHz and 44.1 kHz use bank 3. If other sample rates are
used, then the banks must be set up differently.
2.5.6 Bank Switching Example 2
Problem: The audio system uses all of the sample rates supported by the TAS5504A. How can the
automatic bank switching be set up to handle this situation?
Strategy: Use the TAS5504A bank switching feature to allow for managing and switching three banks
associated with sample rates as follows:
•
•
•
Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz
Bank 2: Coefficients for 88.2kHz and 96 kHz
Bank 3: Coefficients for 176.4 kHz and 192 kHz
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
1. Generate bank-related coefficients for sample rates 48 kHz (bank 1), 96 kHz (bank 2), and 192 kHz
(bank 3) and include the same in the microprocessor-based TAS5504A I2C firmware.,
2. On TAS5504A power up or reset, the microprocessor runs the following TAS5504A initialization code:
a. Update bank 1 (write 0x0004 F00C to register 0x40).
b. Write bank-related I2C registers with appropriate values for bank 1.
c. Write bank 2 (write 0x0005 F00C to register 0x40).
d. Load bank-related I2C registers with appropriate values for bank 2.
e. Write bank 3 (write 0x0006 F00C to register 0x40).
f. Load bank-related I2C registers with appropriate values for bank 3.
g. Select automatic bank switching (write 0x0003 F00C to register 0x40).
3. Now when the audio media changes, the TAS5504A automatically detects the incoming sample rate
and automatically switches to the appropriate bank.
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3
Electrical Specifications
3.1 Absolute Maximum Ratings(1)
Supply voltage, DVDD and DVD_PWM
Supply voltage, AVDD_PLL
–0.3 V to 3.6 V
–0.3 V to 3.6 V
–0.5 V to DVDD + 0.5 V
–0.5 V to 6 V
3.3-V digital input
Input voltage
5-V tolerant(2) digital input
1.8-V LVCMOS(3)
–0.5 V to VREF(4) + 0.5 V
IIK
Input clamp current (VI < 0 or VI > 1.8 V
Output clamp current (VO < 0 or VO > 1.8 V)
Operating free-air temperature
±20 µA
IOK
TA
±20 µA
0°C to 70°C
Tstg
Storage temperature range
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
(3) VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM
(4) VREF is a 1.8-V supply derived from regulators internal to the TAS5504A chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL,
VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power
to external devices.
3.2
Dissipation Rating Table (High-k Board, 105°C Junction)
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
PACKAGE
POWER RATING
PAG
1869 mW
23.36 mW/°C
818 mW
3.3
Dynamic Performance at Recommended Operating Conditions at 25°C
PARAMETER
TEST CONDITIONS
TAS5504A + TAS5111 A-weighted (fS = 48 kHz)
TAS5111 at 1 W
MIN
NOM
102
MAX UNIT
Dynamic range
dB
0.1%
0.01%
±0.1
Total harmonic distortion
Frequency response
TAS5504A output
32-kHz to 96-kHz sample rates
176.4-, 192-kHz sample rates
dB
±0.2
3.4
Recommended Operating Conditions
MIN
3
NOM
3.3
MAX UNIT
Digital supply voltage, DVDD and DVDD_PWM
Analog supply voltage, AVDD_PLL
3.3 V
3.6
3.6
V
V
3
3.3
2
VIH
High-level input voltage
5-V tolerant(1)
1.8-V LVCMOS (XTL_IN)
3.3 V
2
V
V
1.26
0.8
0.8
VIL
Low-level input voltage
5-V tolerant(1)
1.8-V (XTL_IN)
0.54
70
TA
TJ
Operating ambient-air temperature range
Operating junction temperature range
0
0
25
°C
°C
105
(1) 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
Electrical Specifications
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3.5
Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA
MIN
2.4
TYP
MAX UNIT
3.3-V TTL and 5-V(1) tolerant
VOH High-level output voltage
V
1.8-V LVCMOS (XTL_OUT)
IOH = –0.55 mA
IOL = 4 mA
1.44
3.3-V TTL and 5-V(1) tolerant
VOL Low-level output voltage
0.5
V
1.8-V LVCMOS (XTL_OUT)
IOL = 0.75 mA
0.5
IOZ
High-impedance output current
Low-level input current
3.3-V TTL
±20
±1
µA
µA
3.3-V TTL
VI = VIL
IIL
1.8-V LVCMOS (XTL_IN)
5-V tolerant(2)
VI = VIL
±1
VI = 0 V, DVDD = 3 V
VI = VIH
±1
3.3-V TTL
±1
IIH
High-level input current
Input supply current
1.8-V LVCMOS (XTL_IN)
5-V tolerant(2)
VI = VIH
±1
µA
VI = 5.5 V, DVDD = 3 V
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Power down
Normal
±20
140
150
155
8
Digital supply voltage, DVDD
IDD
mA
20
2
Analog supply voltage, AVDD
Power down
(1) 5-V tolerant outputs are SCL and SDA.
(2) 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
3.6
PWM Operation
Over recommended operating conditions
PARAMETER
TEST CONDITIONS
32-kHz data rate ±2%
MODE
VALUE
384
UNIT
kHz
kHz
kHz
12× sample rate
Output sample rate 1×–8× oversampled
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±1%
8×, 4×, or 2× sample rate
8×, 4×, or 2× sample rate
352.8
384
3.7
Switching Characteristics
3.7.1 Clock Signals
PLL input parameters and external filter components over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
MHz
fXTALI
fMCLKI
Frequency, XTAL IN
Only use 13.5-MHz crystal ≤1000 ppm
13.5
Frequency, MCLK (1/tcyc2
)
2
50
MCLK duty cycle
40%
50%
60%
≥2-V MCLK = 49.152 MHz, within the min
and max duty cycle constraints
MCLK minimum high time
MCLK minimum low time
5
ns
ns
≤0.8-V MCLK = 49.152 MHz, within the min
and max duty cycle constraints
5
LRCLK allowable drift before LRCLK reset
External PLL filter capacitors C11 and C12
External PLL filter capacitors C10 and C13
External PLL filter resistors R10 and R11
External VRA_PLL decoupling C14
–10
10 MCLKs
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
SMD, Y5V
100
10
nF
nF
Ω
200
100
nF
(1) See the TAS5504A Example Application Schematic, Section 7.
52 Electrical Specifications
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.2 Serial Audio Port
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
MHz
ns
fSCLKIN SCLK input frequency
CL = 30 pF, SCLK = 64 fS
2.048
12.288
tsu1
th1
tsu2
th2
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
10
10
10
10
32
ns
ns
ns
48
192
60%
60%
kHz
SCLK duty cycle
40% 50%
40% 50%
LRCLK duty cycle
SCLK
edges
SCLK rising edges between LRCLK rising edges
64
64
LRCLK clock edge with respect to the falling edge of
SCLK
SCLK
period
–1/4
1/4
SCLK
(Input)
t
h1
t
su1
LRCLK
(Input)
t
h2
t
su2
SDIN1
SDIN2
SDIN3
T0026-01
Figure 3-1. Slave Mode Serial Data Interface Timing
3.7.3 TAS5504A Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode
I2C-Bus Devices
STANDARD MODE
FAST MODE
PARAMETER
TEST CONDITIONS
UNIT
MIN
–0.5
MAX
MIN MAX
VIL
LOW-level input voltage
0.3 VDD
–0.5
0.7 VDD
0.05 VDD
0
0.3 VDD
V
V
V
V
VIH
HIGH-level input voltage
0.7 VDD
N/A
Vhys
VOL1
Hysteresis of Schmitt-trigger inputs
N/A
LOW-level output voltage (open drain or 3-mA sink current
open collector)
0.4
(1)
tof
Output fall time from VIHmin to VILmax
Bus capacitance from 10 pF
to 400 pF
250 7 + 0.1 Cb
250
ns
tSP
Ii
Pulse duration of spikes suppressed(2)
Input current, each I/O pin
N/A
–30
N/A
30
0
30
30(3)
10
ns
µA
pF
–30(3)
Ci
Capacitance, each I/O pin
10
(1) Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I2C specification.
(2) SCL and SDA have a 30-ns glitch filter.
(3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
Electrical Specifications
53
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.4 TAS5504A Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode
I2C-Bus Devices
All values are referred to VIHmin and VILmax (see Section 3.7.3).
A
STANDARD MODE
MIN MAX
100
FAST MODE
MIN MAX
PARAMETER
TEST CONDITIONS
UNIT
fSCL
SCL clock frequency
0
4
0
400
kHz
Hold time (repeated) START condition.
tHD-STA After this period, the first clock pulse is
generated.
0.6
µs
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4
1.3
0.6
0.6
100
µs
µs
µs
µs
µs
ns
ns
µs
µs
tSU-STA Setup time for repeated START
tSU-DAT Data setup time
4.7
250
0
(1)(2)
tHD-DAT Data hold time
3.45
0
0.9
500(4)
300
(3)
tr
tf
Rise time of both SDA and SCL
Fall time of both SDA and SCL
1000 20 + 0.1 Cb
300 20 + 0.1 Cb
(3)
tSU-STO Setup time for STOP condition
4
0.6
1.3
tBUF
Bus free time between a STOP and
START condition
4.7
Cb
Capacitive loads for each bus line
400
400
pF
V
VnL
Noise margin at the LOW level for each
connected device (including hysteresis)
0.1 VDD
0.2 VDD
0.1 VDD
0.2 VDD
VnH
Noise margin at the HIGH level for each
connected device (including hysteresis)
V
(1) Note that SDA does not have the standard I2C specification 300-ns hold time and that SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 3.3-kΩ pullup resistor be used to avoid potential timing issues.
(2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
(3) Cb = total capacitance of one bus line in pF.
(4) Rise time varies with pullup resistor.
SDA
t
f
t
t
t
r
SU-DAT
HD-STA
t
t
SP
t
BUF
LOW
t
r
t
f
SCL
t
t
t
SU-STO
HD-DAT
SU-STA
t
t
HIGH
HD-STA
S
Sr
P
S
T0114-01
Figure 3-2. Start and Stop Conditions Timing Waveforms
54
Electrical Specifications
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.4.1 Recommemded I2C Pullup Resistors
It is recommended that the I2C pullup resistors RP be 3.3 kΩ (see Figure 3-3). If the circuit has a series resistor
(see Figure 3-4), then the series resistor RS should be less than or equal to 300 Ω.
5 V
TAS5504A
External
Microcontroller
I
I
P
P
R
R
P
P
V
I(SDA)
SDA
V
I(SCL)
SCL
B0099-02
Figure 3-3. I2C Pullup Circuit (With No Series Resistor)
5 V
TAS5504A
External
Microcontroller
I
P
R
P
(2)
(2)
R
R
S
S
SDA
or
SCL
V
I
(1)
V
S
B0100-02
(1) VS = 5 × RS/(RS = RP). When driven low, VS << VIL requirements.
(2) S ≤ 300 Ω
R
Figure 3-4. I2C Pullup Circuit (With Series Resistor)
Electrical Specifications
55
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.5 Reset Timing (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
400
10
TYP
MAX
370
UNIT
ns
td(PWM_off)
tw(RESET)
td(I2C_ready)
td(run)
Time from reset to PWM_EN low (PWM outputs disabled)
Pulse duration, RESET active
Time to enable I2C
ns
3
ms
ms
Device start-up time
Earliest time
RESET
that PWM outputs
could be enabled
t
w(RESET)
VALID
t
d(I2C_ready)
t
t
3 370 ns
d(run)
d(PWM_off)
Start system
Determine SCLK rate
and MCLK ratio. Enable via I C.
2
T0029-04
NOTE: Because a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock ratio
is determined, the system outputs audio if a master volume command is issued at the beginning of td(run)
.
Figure 3-5. Reset Timing
3.7.6 Power-Down (PDN) Timing
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
Time from reset to PWM_EN low (PWM outputs disabled)
Number of MCLKs preceding the release of PDN
Device start-up time
MIN
TYP
MAX
UNIT
td(PWM_off)
300
µs
5
tsu
120
ms
PDN
VALID
t
< 300 µs
t
su
d(PWM_off)
T0030-03
Figure 3-6. Power-Down Timing
56
Electrical Specifications
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.7 Back-End Error (BKND_ERR)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN TYP
MAX
None
100
UNIT
tw(ER)
Pulse duration, BKND_ERR active
350
–25
ns
µs
td(valid_low)
td(valid_high)
Time from back-end error to PWM_EN low (PWM outputs disabled)
I2C programmable to be between 1 to 10 ms
25
% of interval
t
w(ER)
BKND_ERR
VALID
Normal
Normal
Operation
Operation
t
d(valid_high)
t
d(valid_low)
T0031-03
Figure 3-7. Error Recovery Timing
3.7.8 Mute Timing (MUTE)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
td(VOL) Volume ramp time
Defined by rate setting(1)
ms
(1) See the Volume, Treble, and Base Slew Rates Register (0xD0), Section 6.26.
MUTE
Normal
Operation
Normal
Operation
VOLUME
t
t
d(VOL)
d(VOL)
T0032-02
Figure 3-8. Mute Timing
Electrical Specifications
57
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.7.9 Headphone Select (HP_SEL)
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(HP_SEL) Pulse duration, HP_SEL active
350
ns
ms
ms
td(VOL)
t(SW)
Soft-volume update time
Switchover time
Defined by rate setting(1)
0.2
1
(1) See the Volume, Treble, and Base Slew Rates Register (0xD0), Section 6.26.
HP_SEL
t
w(HP_SEL)
Spkr Volume
HP Volume
t
t
d(VOL)
d(VOL)
t
d(VOL)
t
t
(SW)
(SW)
t
d(VOL)
T0033-02
Figure 3-9. HP_SEL Timing
3.7.10 Volume Control
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Individual volume, master volume, or a
combination of both
Maximum attenuation before mute
–109
dB
Maximum gain
Individual volume, master volume
0-dB input, any modulation limit
PSVC enabled
18
0
dB
dB
dB
Maximum volume before the onset of clipping
PSVC range
12, 18, or 24
fS
PSVC rate
PSVC modulation
Single sided
2048
PSVC quantization
Steps
dB
6%
(120 : 2048)
95%
(1944 : 2048)
PSVC PWM modulation limits
PSVC range = 24 dB
58
Electrical Specifications
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.8
Serial Audio Interface Control and Timing
3.8.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used
to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a
delay of one bit clock. The data is written MSB-first and is valid on the rising edge of the bit clock. The
TAS5504A masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
1
0
23 22
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
0
19 18
16-Bit Mode
15 14
15 14
T0034-01
Figure 3-10. I2S 64-fS Format
Electrical Specifications
59
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.8.2 Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
64 fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS5504A masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
LRCLK
Right Channel
Left Channel
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
0
1
0
23 22
19 18
15 14
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
Figure 3-11. Left-Justified 64-fS Format
60
Electrical Specifications
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
3.8.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
64 fS is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit
data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK
transitions. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS5504A masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
Right Channel
Left Channel
MSB
LSB MSB
LSB
0
24-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
0
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
20-Bit Mode
16-Bit Mode
0
0
0
0
T0034-03
Figure 3-12. Right-Justified 64-fS Format
4
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37)
The TAS5504A has a bidirectional I2C interface that is compatible with the I2C (Inter IC) bus protocol and
supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5504A supports standard-mode I2C bus operation (100 kHz maximum) and fast I2C bus operation
(400 kHz maximum). The TAS5504A performs all I2C operations without I2C wait cycles.
The I2C write address is 0x36, and the I2C read address is 0x37.
4.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated
circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be
transferred in byte (8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the
clock is high to indicate a start and stop conditions. A high-to-low transition on SDA indicates a start and a
low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37)
61
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
clock period. These conditions are shown in Figure 4-1. The master generates the 7-bit slave address and
the read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The TAS5504A holds SDA low during the acknowledge clock period to indicate an
acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus an R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be
used for the SDA and SCL signals to set the high level for the bus.
R/
W
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
SDA
SCL
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Start
Stop
T0035-01
Figure 4-1. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is shown in Figure 4-1.
The 7-bit address for the TAS5504A is 0011011.
4.2 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data
processing registers, the serial control interface supports only multiple-byte (4-byte) read/write operations.
During multiple-byte read operations, the TAS5504A responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a
particular subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the TAS5504A compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5504A expects to receive five 32-bit words. If fewer than five 32-bit data
words have been received when a stop command (or another start command) is received, the data
received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5504A
expects to receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5504A also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS5504A. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As was true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data
is discarded.
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37)
62
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
4.3 Single-Byte Write
As shown in Figure 4-2, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
I2C device address and the read/write bit, the TAS5504A device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5504A internal memory address
being accessed. After receiving the address byte, the TAS5504A again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5504A again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Stop
Condition
2
I C Device Address and
Subaddress
Data Byte
Read/Write Bit
T0036-01
Figure 4-2. Single-Byte Write Transfer
4.4 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5504A as shown in Figure 4-3. After receiving each
data byte, the TAS5504A responds with an acknowledge bit.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
Stop
Condition
2
Other Data Bytes
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
T0036-02
Figure 4-3. Multiple-Byte Write Transfer
4.5 Incremental Multiple-Byte Write
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data
write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, ... etc.,
write operations that are composed of a device address, read/write bit, and subaddress and any multiple
of 4 bytes of data. This permits the system to write large register values incrementally without blocking
other I2C transactions.
This feature is enabled by the append subaddress function in the TAS5504A. This function enables the
TAS5504A to append 4 bytes of data to a register that was opened by a previous I2C register write
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of 4 bytes, using 4-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5504A starts processing the data.
The procedure to perform an incremental multibyte write operation is as follows:
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37)
63
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing 4-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to transfer the remaining number of
bytes incrementally in sequential order to complete the register write operation. Each of these append
operations is composed of the device address, write bit, append subaddress (0xFE), and four bytes of
data followed by a stop condition.
3. The operation is terminated due to one of the following error conditions and the data is flushed:
a. If a new subaddress is written to the TAS5504A before the correct number of bytes have been
written.
b. If more or less than 4 bytes are data written at the beginning or during any of the append
operations.
c. If a read bit is sent.
4.6 Single-Byte Read
As shown in Figure 4-4, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes
of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the
TAS5504A address and the read/write bit, the TAS5504A responds with an acknowledge bit. In addition,
after sending the internal memory address byte or bytes, the master device transmits another start
condition followed by the TAS5504A address and the read/write bit again. This time the read/write bit is a
1, indicating a read transfer. After receiving the TAS5504A and the read/write bit, the TAS5504A again
responds with an acknowledge bit. Next, the TAS5504A transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a
stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A0 ACK
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
T0036-03
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Data Byte
Figure 4-4. Single-Byte Read Transfer
4.7 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data
bytes are transmitted by the TAS5504A to the master device as shown in Figure 4-5. Except for the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
I2C Serial Control Interface (Slave Addresses 0x36 and 0x37)
64
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SLES169–FEBRUARY 2006
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Stop
Condition
T0036-04
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Figure 4-5. Multiple-Byte Read Transfer
5
Serial Control I2C Register Summary
The TAS5504A slave address is 0x36. See Serial Control Interface Register Definitions, Section 6, for
complete bit definitions.
Note that u indicates unused bits.
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF
CONTENTS
DEFAULT STATE
0x00
1
Clock control register
Set data rate and MCLK frequency
1. fS = 48 kHz
2. MCLK = 256 fS = 12.288 MHz
0x03
0x01
1
General status register
Clip indicator and ID code for the
TAS5504A
0x02
0x03
1
1
Reserved
System control register 1
System control register 2
PWM high pass, clock set, un-mute
select, PSVC select
1. PWM high-pass disabled
2. Auto clock set
3. Hard unmute on clock error recovery
4. PSVC HIZ disable
0x04
1
1
Automute and de-emphasis control
1. Automute timeout disable
2. Post-DAP detection automute enabled
3. 4-Ch device input detection automute enabled
4. Unmute threshold 6 dB over input
5. No de-emphasis
0x05–0x06
Channel configuration
registers
Configure channels 1 and 2
1. Enable back-end reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Do not remap the output for the TAS5182
6. Do not go low-low in mute
7. Do not remap Hi-Z state to low-low state
0x07–0x0A
0x0B–0x0C
Reserved
1
Channel configuration
registers
Configure channels 3 and 4
1. Enable back-end reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Do not remap the output for the TAS5182
6. Do not go low-low in mute
7. Do not remap Hi-Z state to low-low state
0x0D
1
Headphone configuration
register
Configure headphone output
1. Disable back-end reset sequence
2. Valid does not have to be low for reset
3. Valid does not have to be low for mute
4. Normal BEPolarity
5. Do not remap output to comply with 5182
6. Do not go low-low in mute
7. Do not remap Hi-Z state to low-low state
Serial Control I2C Register Summary
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I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF
CONTENTS
DEFAULT STATE
24-bit I2S
0x0E
1
Serial data interface register Set serial data interface to
right-justified, I2S, or left-justified
0x0F
0x10–0x13
0x14
1
Soft-mute register
Soft mute for channels 1, 2, 3, and 4 Unmute all channels
Reserved
1
1
Automute control
Set automute delay and threshold
1. Set automute delay = 5 ms
2. Set automute threshold less than bit 8.
0x15
Automute PWM threshold
and back-end reset period
Set PWM automute threshold, set
back-end reset period 1.
1. Set the PWM threshold the same as the
TAS5504A input threshold.
2. Set the back-end reset period = 5 ms.
97.7%
0x16
0x17–0x3F
0x40
1
Modulation limit register
Set modulation index
Reserved
4
Bank-switching command
register
Set up DAP coefficients bank
switching for banks 1, 2, and 3
Manual selection – bank 1
0x41–0x42
32/Reg
See Input Mixer Registers
(0x41 and 0x42, Channels 1
and 2), Section 6.13
8 × 4 input crossbar mixer setup
SDIN1-left to input mixer 1
SDIN1-right to input mixer 2
0x43–0x46
0x47–0x48
Reserved
32/Reg
See Input Mixer Registers
(0x47 and 0x48, Channels 3
and 4), Section 6.13
8 × 4 input crossbar mixer setup
SDIN4-left to input mixer 3
SDIN4-right to input mixer 4
0x49
0x4A
0x4B
4
4
4
ipmix_1_to_ch4
ipmix_2_to_ch4
ipmix_3_to_ch2
Input mixer 1 to Ch4 mixer
coefficient
0.0
0.0
0.0
Input mixer 2 to Ch4 mixer
coefficient
Input mixer 3 to Ch2 mixer
coefficient
0x4C
0x4D
0x4E
4
4
4
Ch3_bp_bq2 Bypass
Ch3_bq2
Ch3 biquad 2 coefficient
Ch3 biquad 2 coefficient
0.0
1.0
0.0
ipmix_4_to_ch12
Ch4 biquad 2 output to Ch1 mixer
and Ch2 mixer coefficient
0x4F
0x50
4
4
Ch4_bp_bq2
Ch4_bq2
Bypass Ch4 biquad 2 coefficient 0
Ch4 biquad 2 coefficient
0.0
1.0
0x51–0x5E
20/Reg.
See Biquad Filter Registers Channels 1, 2, 3, and 4 biquad filter All biquads = all pass
(0x51–0x88), Section 6.15 coefficients
0x89–0x8A
8
8
Bass and treble bypass Ch1 Bypass bass and treble for Ch1 and Bass and treble bypassed for Ch1 and Ch2
and Ch2
Ch21 and 2
0x8B–0x8E
0x8F–0x90
Reserved
Bass and treble bypass Ch3 Bypass bass and treble for Ch3 and Bass and treble bypassed for Ch3 and Ch4
and Ch4
Ch4
0x91
0x92
0x93
0x94
4
8
4
8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness Log2 LG
0.5
Loudness Log2 LO
0.0
Loudness G
0.0
Loudness O
Loudness O
0.0
Loudness biquad coefficient b0
Loudness biquad coefficient b1
Loudness biquad coefficient b2
Loudness biquad coefficient a0
Loudness biquad coefficient a1
DRC1 control Ch1, Ch2, and Ch3
DRC1 control Ch4
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
DRC1 disabled in Ch1, Ch2, and Ch3
DRC2 disabled (Ch4)
0.0041579
0x95
20
Loudness biquad
0x96
0x97
4
4
DRC1 Ch1, Ch2, and Ch3
DRC2 Ch4 control
Ch1, Ch2, and Ch3 DRC1
energy
DRC1 energy
0x98
8
Ch1, Ch2, Ch3, and Ch4
DRC1 (1 – energy)
DRC1 (1 – energy)
0.9958421
Serial Control I2C Register Summary
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SLES169–FEBRUARY 2006
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF
CONTENTS
DEFAULT STATE
DRC1 threshold (T1) – upper 4
bytes
0x00, 0x00, 0x00, 0x00
Channels 1, 2, and 3 DRC1
threshold T1
DRC1 threshold (T1) – lower 4 bytes 0x0B, 0x20, 0xE2, 0xB2
0x99
16
DRC1 threshold (T2) – upper 4
bytes
0x00, 0x00, 0x00, 0x00
Channels 1, 2, and 3 DRC1
threshold T2
DRC1 threshold (T2) – lower 4 bytes 0x06, 0xF9, 0xDE, 0x58
Channels 1, 2, and 3, DRC1 DRC1 slope (k0)
slope k0
0x0F, 0xC0, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
Channels 1, 2, and 3, DRC1 DRC1 slope (k1)
slope k1
0x9A
0x9B
12
16
Channels 1, 2, and 3, DRC1 DRC1 slope (k2)
slope k2
Channels 1, 2, and 3 DRC1 DRC1 offset 1 (O1) – upper 4 bytes 0x00, 0x00, 0xFF, 0xFF
offset 1
DRC1 offset 1 (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
Channels 1, 2, and 3 DRC1 DRC1 offset 2 (O2) – upper 4 bytes 0x00, 0x00, 0x00, 0x00
offset 2
DRC1 offset 2 (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
Channels 1, 2, and 3, DRC1 DRC1 attack
attack
Channels 1, 2, and 3, DRC1 DRC1 (1 – attack)
(1– attack)
0x00, 0x7F, 0x77, 0xC0
0x9C
16
Channels 1, 2, and 4, DRC1 Delay DRC1 decay
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
Channels 1, 2, 3, and 3,
DRC1 (1 – decay)
DRC1 (1 – decay)
Ch4 DRC2 energy
DRC2 energy
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x9D
0x9E
8
Ch4 DRC2 (1 – energy)
Ch4 DRC2 threshold T1
DRC2 (1 – energy)
DRC2 threshold (T1) – upper 4
bytes
DRC2 threshold (T1) – lower 4 bytes 0x0B, 0x20, 0xE2, 0xB2
16
Ch4 DRC2 threshold T2
DRC2 threshold (T2) – upper 4
bytes
0x00, 0x00, 0x00, 0x00
DRC2 threshold (T2) – lower 4 bytes 0x06, 0xF9, 0xDE, 0x58
Ch4 DRC2 slope k0
Ch4 DRC2 slope k1
Ch4 DRC2 slope k2
Ch4 DRC2 offset 1
DRC2 slope (k0)
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
0x9F
0xA0
12
16
DRC2 slope (k1)
DRC2 slope (k2)
DRC2 offset (O1) – upper 4 bytes
DRC2 offset (O1) – lower 4 bytes
DRC2 offset (O2) – upper 4 bytes
DRC2 offset (O2) – lower 4 bytes
DRC 2 attack
Ch4 DRC2 offset 2
Ch4 DRC2 attack
Ch4 DRC2 (1 – attack)
Ch4 DRC2
DRC2 (1 – attack)
0xA1
16
Delay DRC2 decay
Ch4 DRC2 (1 – decay)
DRC bypass 1
DRC2 (1 – decay)
Channel 1 DRC1 bypass coefficient 1.0
Channel 1 DRC1 inline coefficient 0.0
Channel 2 DRC1 bypass coefficient 1.0
0xA2
0xA3
8
8
DRC inline 1
DRC bypass 2
DRC inline 2
Channel 2 DRC1 inline coefficient
Reserved
0.0
0xA4–0xA7
0xA8
8
8
Reserved
DRC bypass 3
DRC inline 3
Channel 3 DRC1 bypass coefficient 1.0
Channel 3 DRC1 inline coefficient 0.0
Channel 4 DRC2 bypass coefficient 1.0
0xA9
8
DRC bypass 4
DRC inline 4
Channel 4 DRC2 inline coefficient
0.0
0xAA
0xAB
8
8
sel op1–4 and mix to S
Select 0 to 2 of four DAP channels
to output mixer S
Select channel 1 to PWM 1
sel op1–4 and mix to T
Select 0 to 2 of four DAP channels
to output mixer T
Select channel 2 to PWM 2
0xAC–0xAF
Reserved
Serial Control I2C Register Summary
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SLES169–FEBRUARY 2006
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF
CONTENTS
DEFAULT STATE
Select channel 3 to PWM 3
0xB0
0xB1
12
sel op1–4 and mix to Y
Select 0 to 3 of four DAP channels
to output mixer Y
12
sel op1-4 and mix to Z
Select 0 to 3 of four DAP channels
to output mixer Z
Select channel 4 to PWM 4
0xB2–0xCE
0xCF
Reserved
20
4
Volume biquad
Volume biquad
All pass
0xD0
Vol, T, and B slew rates
u(31:24), u(23:16), u(15:12)
VSR(11:8), TBSR(7:0)
0x00, 0x00, 0x02, 0x3F
0xD1
0xD2
4
4
Ch1 volume
Ch2 volume
Ch1 volume
0 dB
0 dB
Ch2 volume
0xD3–0xD6
0xD7
Reserved
4
4
4
4
4
4
4
4
Ch3 volume
Ch3 volume
0 dB
0xD8
Ch4 volume
Channel 4 volume
Master volume
0 dB
0xD9
Master volume
Bass filter set
Bass filter index
Treble filter set
Treble filter index
Mute
0xDA
Bass filter set (all channels)
Bass filter level (all channels)
Treble filter set (all channels)
Treble filter level (all channels)
Filter set 3
0 dB
0xDB
0xDC
Filter set 3
0 dB
0xDD
0xDE
AM mode and tuned
frequency register
Set up AM mode for AM-interference AM mode disabled
reduction
Select sequence 1
IF frequency = 455 kHz
Use BCD-tuned frequency
0xDF
0xE0
4
4
PSVC control range
Set PSVC control range
12-dB control range
General control register
Four-channel configuration, PSVC
enabled
Four-channel configuration, power-supply volume
control disabled
0xE1–0xFD
0xFE
Reserved
4 (min)
Multiple-byte-write append
register
Special register
N/A
0xFF
Reserved
Serial Control I2C Register Summary
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6
Serial Control Interface Register Definitions
Unless otherwise noted, the I2C register default values are in bold font.
Note that u indicates unused bits.
6.1 Clock Control Register (0x00)
Bit D1 is don't care.
Table 6-1. Clock Control Register
D7
0
0
0
0
1
1
1
1
–
–
–
–
–
–
–
–
–
–
D6
0
0
1
1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
D5
0
1
0
1
0
1
0
1
–
–
–
–
–
–
–
–
–
–
D4
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
–
–
D3
–
–
–
–
–
–
–
–
0
0
1
1
0
0
1
1
–
–
D2
–
–
–
–
–
–
–
–
0
1
0
1
0
1
0
1
–
–
D1
D0
–
FUNCTION
32-kHz data rate
–
38-kHz data rate
–
44.1-kHz data rate
48-kHz data rate
–
–
88.2-kHz data rate
96-kHz data rate
–
–
176.4-kHz data rate
192-kHz data rate
MCLK frequency = 64
MCLK frequency = 128
MCLK frequency = 192
MCLK frequency = 256
MCLK frequency = 384
MCLK frequency = 512
MCLK frequency = 768
Reserved
–
1
Clock register is valid (read only)
0
Clock register is not valid (read only)
6.2 General Status Register 0 (0x01)
Table 6-2. General Status Register (0x01)
D7
1
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
Clip indicator
–
1
–
–
–
–
–
–
Bank switching busy
–
–
0
0
0
0
1
1
Identification code for TAS5504A
Serial Control Interface Register Definitions
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6.3 System Control Register 1 (0x03)
Bits D6, D5, D2, D1, and D0 are don't care.
Table 6-3. System Control Register 1
D7
0
D6
–
D5
D4
–
D3
–
D2
D1
D0
FUNCTION
PWM high pass disabled
1
–
–
–
PWM high pass enabled
–
–
0
Soft unmute on recovery from clock error
Hard unmute on recovery from clock error
PSVC Hi-Z enable
–
–
1
–
–
–
1
–
–
–
0
PSVC Hi-Z disabled
6.4 System Control Register 2 (0x04)
Bit D3 and D2 are don't care.
Table 6-4. System Control Register 2
D7
0
D6
–
D5
–
D4
–
D3
D2
D1
–
D0
–
FUNCTION
Reserved
–
0
–
–
–
–
PWM automute detection enabled
PWM automute detection disabled
4-Ch device input detection automute enabled
4-Ch device input detection automute disabled
Unmute threshold 6 dB over input threshold
Unmute threshold equal to input threshold
No de-emphasis
–
1
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
0
–
–
–
1
–
–
–
–
0
0
–
–
0
1
De-emphasis for fS = 32 kHz
–
–
1
0
De-emphasis for fS = 44.1 kHz
–
–
1
1
De-emphasis for fS = 48 kHz
70
Serial Control Interface Register Definitions
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6.5 Channel Configuration Control Registers (0x05, 0x06, 0x0B, and 0x0C)
Channels 1, 2, 3, and 4 are mapped into 0x05, 0x06, 0x0B, and 0x0C.
Bit D0 is don't care.
Table 6-5. Channel Configuration Control Registers
D7
0
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
FUNCTION
Disable back-end reset sequence for a channel – BEErrorRecEn
Enable back-end reset sequence for a channel
1
–
–
–
–
–
–
–
0
–
–
–
–
–
VALID does not have to be low for this channel to be reset – BEValidRst
VALID must be low for this channel to be reset
–
1
–
–
–
–
–
–
–
0
–
–
–
–
VALID does not have to be low for this channel to be muted –
BEValidMute
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
0
1
VALID must be low for this channel to be muted
Normal BEPolarity
Switches PWM+ and PWM– and inverts audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
Do not go to low-low in mute – BELowMute
Go to low-low in mute
Do not remap Hi-Z state to low-low state – BE5111BsMute
Remap Hi-Z state to low-low state
6.6 Headphone Configuration Control Register (0x0D)
Bit D0 is don't care.
Table 6-6. Headphone Configuration Control Register
D7
0
1
–
–
–
–
–
–
–
–
–
–
–
–
D6
–
–
0
1
–
–
–
–
–
–
–
–
–
–
D5
–
–
–
–
0
1
–
–
–
–
–
–
–
–
D4
–
–
–
–
–
–
0
1
–
–
–
–
–
–
D3
–
–
–
–
–
–
–
–
0
1
–
–
–
–
D2
–
–
–
–
–
–
–
–
–
–
0
1
–
–
D1
–
–
–
–
–
–
–
–
–
–
–
–
0
1
D0
FUNCTION
Disable back-end reset sequence for a channel – BEErrorRecEn
Enable back-end reset sequence for a channel
VALID does not have to be low for this channel to be reset – BEValidRst
VALID must be low for this channel to be reset
VALID does not have to be low for this channel to be muted – BEValidMute
VALID must be low for this channel to be muted
Normal BEPolarity
Switches PWM+ and PWM– and inverts audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
Do not go to low-low in mute – BELowMute
Go to low-low in mute
Do not remap Hi-Z state to low-low state – BE5111BsMute
Remap Hi-Z state to low-low state
Serial Control Interface Register Definitions
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6.7 Serial Data Interface Control Register (0x0E)
Nine serial modes can be programmed I2C.
Table 6-7. Serial Data Interface Control Register Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD
LENGTHS
D7–D4
D3
D2
D1
D0
Right-justified
Right-justified
Right-justified
I2S
16
20
24
16
20
24
16
20
24
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
I2S
I2S
Left-justified
Left-justified
Left-Justified
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6.8 Soft-Mute Register (0x0F)
Do not use this register if using the remapped output mixer configuration.
Table 6-8. Soft-Mute Register (0x0F)
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
1
FUNCTION
Soft-mute Ch1
–
–
–
–
–
–
1
–
Soft-mute Ch2
–
1
–
–
–
–
–
–
Soft-mute Ch3
1
–
–
–
–
–
–
–
Soft-mute Ch4
0
0
0
0
0
0
0
0
Unmute all channels
72
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.9 Automute Control Register (0x14)
For more information on how to use this register, see Automute and Mute Channel Controls,
Section 1.4.9.1.
Table 6-9. Automute Control Register (0x14)
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Set input automute and PWM automute delay to 1 ms
Set input automute and PWM automute delay to 2 ms
Set input automute and PWM automute delay to 3 ms
Set input automute and PWM automute delay to 4 ms
Set input automute and PWM automute delay to 5 ms
Set input automute and PWM automute delay to 10 ms
Set input automute and PWM automute delay to 20 ms
Set input automute and PWM automute delay to 30 ms
Set input automute and PWM automute delay to 40 ms
Set input automute and PWM automute delay to 50 ms
Set input automute and PWM automute delay to 60 ms
Set input automute and PWM automute delay to 70ms
Set input automute and PWM automute delay to 80 ms
Set input automute and PWM automute delay to 90 ms
Set input automute and PWM automute delay to 100 ms
Set input automute and PWM automute delay to 110 ms
Set input automute threshold less than bit 1 (zero input signal), lowest
automute threshold.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Set input automute threshold less than bit 2
Set input automute threshold less than bit 3
Set input automute threshold less than bit 4
Set input automute threshold less than bit 5
Set input automute threshold less than bit 6
Set input automute threshold less than bit 7
Set input automute threshold less than bit 8
Set input automute threshold less than bit 9
Set input automute threshold less than bit 10
Set input automute threshold less than bit 11
Set input automute threshold less than bit 12
Set input automute threshold less than bit 13
Set input automute threshold less than bit 14
Set input automute threshold less than bit 15
Serial Control Interface Register Definitions
73
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.10 Automute PWM Threshold and Back-End Reset Period (0x15)
For more information on how to use this regiater, see Automute and Mute Channel Controls,
Section 1.4.9.1.
Table 6-10. Automute PWM Threshold and Back-End Reset Period
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
D3
–
–
–
–
–
–
–
–
–
–
–
–
–
D2
–
–
–
–
–
–
–
–
–
–
–
–
–
D1
–
–
–
–
–
–
–
–
–
–
–
–
–
D0
–
–
–
–
–
–
–
–
–
–
–
–
–
FUNCTION
Set PWM automute threshold equals input automute threshold
Set PWM automute threshold 1 bit more than input automute threshold
Set PWM automute threshold 2 bits more than input automute threshold
Set PWM automute threshold 3 bits more than input automute threshold
Set PWM automute threshold 4 bits more than input automute threshold
Set PWM automute threshold 5 bits more than input automute threshold
Set PWM automute threshold 6 bits more than input automute threshold
Set PWM automute threshold 7 bits more than input automute threshold
Set PWM automute threshold equals input automute threshold
Set PWM automute threshold 1 bit less than input automute threshold
Set PWM automute threshold 2 bits less than input automute threshold
Set PWM automute threshold 3 bits less than input automute threshold
Set PWM automute threshold 4 bits less than input automute threshold
Set PWM automute threshold 5 bits less than input automute threshold
Set PWM automute threshold 6 bits less than input automute threshold
Set PWM automute threshold 7 bits less than input automute threshold
Set back-end reset period < 1 ms
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Set back-end reset period 1 ms
Set back-end reset period 2 ms
Set back-end reset period 3 ms
Set back-end reset period 4 ms
Set back-end reset period 5 ms
Set back-end reset period 6 ms
Set back-end reset period 7 ms
Set back-end reset period 8 ms
Set back-end reset period 9 ms
Set back-end reset period 10 ms
Set back-end reset period 10 ms
Set back-end reset period 10 ms
74
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.11 Modulation Index Limit Register (0x16)
Bits D7–D3 are don't care. Note that some power stages require a lower modulation limit than the default
of 97.7%. Contact Texas Instruments for more details about the requirements for a particular power stage.
Table 6-11. Modulation Index Limit Register
D7
D6
D5
D4
D3
D2
D1
D0
LIMIT
DCLKS]
MIN WIDTH
[DCLKS]
MODULATION
INDEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
2
4
99.2%
98.4%
97.7%
96.9%
96.1%
95.3%
95.5%
93.8%
6
8
10
12
14
16
Serial Control Interface Register Definitions
75
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.12 Bank Switching Command Register (0x40)
Bits D31-D24, D22-D19 are don't care.
Table 6-12. Bank Switching Command
D31
D30
D22
D29
D21
D28
D20
D27
D19
D26
D25
D24
FUNCTION
FUNCTION
Unused bits
D23
–
D18
0
D17
0
D16
0
Manual selection bank 1
Manual selection bank 2
Manual selection bank 3
Automatic bank selection
Update the values in bank 1
Update the values in bank 2
Update the values in bank 3
Update only the bank map
–
0
0
1
–
0
1
0
–
0
1
1
–
1
0
0
–
1
0
1
–
1
1
0
0
1
1
1
0
x
x
x
Update the bank map using values in D15–D0
1
x
x
x
Do not update the bank map using values in D15–D0
D15
1
D14
–
D13
–
D12
–
D11
–
D10
–
D9
–
D8
–
FUNCTION
32-kHz data rate – use bank 1
38-kHz data rate – use bank 1
44.1-kHz data rate – use bank 1
48-kHz data rate – use bank 1
88.2-kHz data rate – use bank 1
96-kHz data rate – use bank 1
176.4-kHz data rate – use bank 1
192-kHz data rate – use bank 1
Default
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
D7
1
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
32-kHz data rate – use bank 2
38-kHz data rate – use bank 2
44.1-kHz data rate – use bank 2
48-kHz data rate – use bank 2
88.2-kHz data rate – use bank 2
96-kHz data rate – use bank 2
176.4-kHz data rate – use bank 2
192-kHz data rate – use bank 2
Default
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
76
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.13 Input Mixer Registers (0x41, 0x42, 0x47, 0x48, Channels 1–4)
Input mixers 1, 2, 3, and 4 are mapped into registers 0x41, 0x42, 0x47, and 0x48.
Each gain coefficient is in 28-bit (5.23) format, so 0x8000 0000 is a gain of 1. Each gain coefficient is
written as a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
Table 6-13. Input Mixer Registers Format (Channels 1–4)
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
SDIN1-left A to input mixer 1 coefficient (default = 1)
u(31:28), A_1(27:24), A_1(23:16), A_1(15:8), A_1(7:0)
A_to_ipmix[1]
B_to_ipmix[1]
C_to_ipmix[1]
D_to_ipmix[1]
E_to_ipmix[1]
F_to_ipmix[1]
G_to_ipmix[1]
H_to_ipmix[1]
A_to_ipmix[2]
B_to_ipmix[2]
C_to_ipmix[2]
D_to_ipmix[2]
E_to_ipmix[2]
F_to_ipmix[2]
G_to_ipmix[2]
H_to_ipmix[2]
A_to_ipmix[3]
B_to_ipmix[3]
C_to_ipmix[3]
D_to_ipmix[3]
E_to_ipmix[3]
F_to_ipmix[3]
G_to_ipmix[3]
H_to_ipmix[3]
SDIN1-right B to input mixer 1 coefficient (default = 0)
u(31:28), B_1(27:24), B_1(23:16), B_1(15:8), B_1(7:0)
SDIN2-left C to input mixer 1 coefficient (default = 0)
u(31:28), C_1(27:24), C_1(23:16), C_1(15:8), C_1(7:0)
SDIN2-right D to input mixer 1 coefficient (default = 0)
u(31:28), D_1(27:24), D_1(23:16), D_1(15:8), D_1(7:0)
0x41
0x42
0x47
32
32
32
SDIN3-left E to input mixer 1 coefficient (default = 0)
u(31:28), E_1(27:24), E_1(23:16), E_1(15:8), E_1(7:0)
SDIN3-right F to input mixer 1 coefficient (default = 0)
u(31:28), F_1(27:24), F_1(23:16), F_1(15:8), F_1(7:0)
SDIN4-left G to input mixer 1 coefficient (default = 0)
u(31:28), G_1(27:24), G_1(23:16), G_1(15:8), G_1(7:0)
SDIN4-right H to input mixer 1 coefficient (default = 0)
u(31:28), H_1(27:24), H_1(23:16), H_1(15:8), H_1(7:0)
SDIN1-left A to input mixer 2 coefficient (default = 0)
u(31:28), A_2(27:24), A_2(23:16), A_2(15:8), A_2(7:0)
SDIN1-right B to input mixer 2 coefficient (default = 1)
u(31:28), B_2(27:24), B_2(23:16), B_2(15:8), B_2(7:0)
SDIN2-left C to input mixer 2 coefficient (default = 0)
u(31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)
SDIN2-right D to input mixer 2 coefficient (default = 0)
u(31:28), D_2(27:24), D_2(23:16), D_2(15:8), D_2(7:0)
SDIN3-left E to input mixer 2 coefficient (default = 0)
u(31:28), E_2(27:24), E_2(23:16), E_2(15:8), E_2(7:0)
SDIN3-right F to input mixer 2 coefficient (default = 0)
u(31:28), F_2(27:24), F_2(23:16), F_2(15:8), F_2(7:0)
SDIN4-left G to input mixer 2 coefficient (default = 0)
u(31:28), G_2(27:24), G_2(23:16), G_2(15:8), G_2(7:0)
SDIN4-right H to input mixer 2 coefficient (default = 0)
u(31:28), H_2(27:24), H_2(23:16), H_2(15:8), H_2(7:0)
SDIN1-left A to input mixer 3 coefficient (default = 0)
u(31:28), A_3(27:24), A_3(23:16), A_3(15:8), A_3(7:0)
SDIN1-right B to input mixer 3 coefficient (default = 0)
u(31:28), B_3(27:24), B_3(23:16), B_3(15:8), B_3(7:0)
SDIN2-left C to input mixer 3 coefficient (default = 0)
u(31:28), C_3(27:24), C_3(23:16), C_3(15:8), C_3(7:0)
SDIN2-right D to input mixer 3 coefficient (default = 0)
u(31:28), D_3(27:24), D_3(23:16), D_3(15:8), D_3(7:0)
SDIN3-left E to input mixer 3 coefficient (default = 0)
u(31:28), E_3(27:24), E_3(23:16), E_3(15:8), E_3(7:0)
SDIN3-right F to input mixer 3 coefficient (default = 0)
u(31:28), F_3(27:24), F_3(23:16), F_3(15:8), F_3(7:0)
SDIN4-left G to input mixer 3 coefficient (default = 1)
u(31:28), G_3(27:24), G_3(23:16), G_3(15:8), G_3(7:0)
SDIN4-right H to input mixer 3 coefficient (default = 0)
u(31:28), H_3(27:24), H_3(23:16), H_3(15:8), H_3(7:0)
Serial Control Interface Register Definitions
77
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Table 6-13. Input Mixer Registers Format (Channels 1–4) (continued)
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
SDIN1-left A to input mixer 4 coefficient (default = 0)
u(31:28), A_4(27:24), A_4(23:16), A_4(15:8), A_4(7:0)
A_to_ipmix[4]
B_to_ipmix[4]
C_to_ipmix[4]
D_to_ipmix[4]
E_to_ipmix[4]
F_to_ipmix[4]
G_to_ipmix[4]
H_to_ipmix[4]
SDIN1-right B to input mixer 4 coefficient (default = 0)
u(31:28), B_4(27:24), B_4(23:16), B_4(15:8), B_4(7:0)
SDIN2-left C to input mixer 4 coefficient (default = 0)
u(31:28), C_4(27:24), C_4(23:16), C_4(15:8), C_4(7:0)
SDIN2-right D to input mixer 4 coefficient (default = 0)
u(31:28), D_4(27:24), D_4(23:16), D_4(15:8), D_4(7:0)
0x48
32
SDIN3-left E to input mixer 4 coefficient (default = 0)
u(31:28), E_4(27:24), E_4(23:16), E_4(15:8), E_4(7:0)
SDIN3-right F to input mixer 4 coefficient (default = 0)
u(31:28), F_4(27:24), F_4(23:16), F_4(15:8), F_4(7:0)
SDIN4-left G to input mixer 4 coefficient (default = 0)
u(31:28), G_4(27:24), G_4(23:16), G_4(15:8), G_4(7:0)
SDIN4-right H to input mixer 4 coefficient (default = 1)
u(31:28), H_4(27:24), H_4(23:16), H_4(15:8), H_4(7:0)
6.14 Bass Management Registers (0x49–0x50)
Registers 0x49–0x50 provide configuration control for bass management.
Each gain coefficient is in 28-bit (5.23) format so 0x8000 0000 is a gain of 1. Each gain coefficient is
written as a 32-bit word with the upper four bits not used.
Table 6-14. Bass Management Registers Format (0x49–0x50)
SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x49
0x4A
0x4B
0x4C
4
4
4
4
ipmix_1_to_ch4
ipmix_2_to_ch4
ipmix_3_to_ch12
Ch3_bp_bq2
Input mixer 1 to Ch4 mixer coefficient (default = 0)
u(31:28), ipmix14(27:24), ipmix14(23:16), ipmix14(15:8), ipmix14(7:0)
Input mixer 2 to Ch4 mixer coefficient (default = 0)
u(31:28), ipmix24(27:24), ipmix24(23:16), ipmix24(15:8), ipmix24(7:0)
Input mixer 3 to Ch1 and Ch2 mixer coefficient (default = 0)
u(31:28), ipmix32(27:24), ipmix32(23:16), ipmix32(15:8), ipmix32(7:0):
Ch3 Biquad-2 bypass coefficient (default = 0)
u(31:28), ch3_bp_bq2(27:24), ch3_bp_bq2(23:16), ch3_bp_bq2(15:8),
ch3_bp_bq2(7:0)
0x4D
0x4E
4
4
Ch3_bq2
Ch3 Biquad-2 Inline coefficient (default = 1)
u(31:28), ch3_bq2(27:24), ch3_bq2(23:16), ch3_bq2(15:8), ch3_bq2(7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
ipmix_4_to_ch12
Ch4 Biquad-2 output to Ch1 mixer and Ch2 mixer coefficient (default = 0)
u(31:28), ipmix4_12(27:24), ipmix4_12(23:16), ipmix4_12 (15:8),
ipmix4_12(7:0)
0x4F
0x50
4
4
Ch4_bp_bq2
Ch4_bq2
Ch4 Biquad-2 bypass coefficient (default = 0)
u(31:28), ch4_bp_bq2(27:24), ch4_bp_bq2(23:16), ch4_bp_bq2(15:8),
ch4_bp_bq2(7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
Ch4 biquad-2 inline coefficient (default = 1)
u(31:28), ch4_bq2(27:24), ch4_bq2(23:16), ch4_bq2(15:8), ch4_bq2(7:0)
78
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.15 Biquad Filter Registers (0x51–0x88)
Table 6-15. Biquad Filters Register Format (0x51–0x88)
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF
CONTENTS
DEFAULT STATE
See Table 6-16
0x51–0x57
0x58–0x5E
0x7B–0x81
0x82–0x88
20/reg.
20/reg.
20/reg.
20/reg.
Ch1_bq[1] – [7]
Ch2_bq[1] – [7]
Ch3_bq[1] – [7]
Ch4_bq[1] – [7]
Ch1 biquads 1–7. See Table 6-16 for bit definition.
Ch2 biquads 1–7. See Table 6-16for bit definition.
Ch3 biquads 1–7. See Table 6-16 for bit definition.
Ch4 biquads 1–7. See Table 6-16 for bit definition.
See Table 6-16
See Table 6-16
See Table 6-16
Each gain coefficient is in 28-bit (5.23) format so 0x8000 0000 is a gain of 1. Each gain coefficient is
written as a 32-bit word with the upper four bits not used.
Table 6-16. Contents of One 20-Byte Biquad Filter Register Format (Default = All-Pass)
DESCRIPTION
REGISTER FIELD CONTENTS
DEFAULT GAIN COEFFICIENT VALUES
DECIMAL
1.0
HEX
b0 coefficient
u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)
u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)
u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)
u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)
u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
b1 coefficient
b2 coefficient
a1 coefficient
a2 coefficient
0.0
0.0
0.0
0.0
6.16 Bass and Treble Bypass Register (0x89–0x90, Channels 1–4)
Channels 1, 2, 3, and 4 are mapped into registers 0x89, 0x8A, 0x8F, and 0x90. Eight bytes are written for
each channel. Each gain coefficient is in 28-bit (5.23) format, so 0x8000 0000 is a gain of 1. Each gain
coefficient is written as a 32-bit word with the upper four bits not used.
Table 6-17. Bass and Treble Bypass Register Format (0x89–0x90)
REGISTER
NAME
TOTAL
BYTES
CONTENTS
INITIALIZATION
VALUE
Channel bass and treble bypass
u(31:28), bypass(27:24), bypass(23:16), bypass(15:8),
bypass(7:0)
0x00, 0x00, 0x00, 0x00
8
Channel bass and treble inline
u(31:28), inline(27:24), inline(23:16), inline(15:8), inline(7:0)
0x00, 0x80, 0x00, 0x00
Serial Control Interface Register Definitions
79
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SLES169–FEBRUARY 2006
6.17 Loudness Registers (0x91–0x95)
Table 6-18. Loudness Registers Format (0x91–0x95)
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF
CONTENTS
DEFAULT STATE
0x91
0x92
0x93
0x94
4
8
4
8
Loudness Log2 gain (LG)
Loudness Log2 offset (LO)
Loudness Log2 LO
u(31:28), LG(27:24), LG(23:16), LG(15:8), LG(7:0)
u(31:24), u(23:16), LO(15:8), LO(7:0)
0xFF, 0xC0, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
LO(31:24), LO(23:16), LO(15:8), LO(7:0)
u(31:28), G(27:24), G(23:16), G(15:8), G(7:0)
u(31:24), u(23:16), O(15:8), O(7:0)
Loudness gain (G)
Loudness offset upper 16 bits (O)
Loudness offset lower 32 bits (O)
Loudness biquad (b0)
O(31:24), O(23:16), O(15:8), O(7:0)
u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)
u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)
u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)
u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)
u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
Loudness biquad (b1)
0x95
20
Loudness biquad (b2)
Loudness biquad (a1)
Loudness biquad (a2)
6.18 DRC1 Control (0x96, Channels 1–3)
Bits D31–D14 and D7–D6 are don't care. Note that there must be a 10-ms delay between a write to
register 0x96 and a write to register 0x97.
Table 6-19. DCR1 Control (0x96, Channels 1–3)
D31
D23
D15
D30
D22
D14
D29
D21
D28
D20
D27
D26
D25
D24
FUNCTION
FUNCTION
FUNCTION
Unused bits
Unused bits
D19
D18
D17
D16
D13
0
D12
0
D11
–
D10
–
D9
–
D8
–
Channel 1: No DRC
0
1
–
–
–
–
Channel 1: Pre-volume DRC
Channel 1: Post-volume DRC
Channel 1: No DRC
1
0
–
–
–
–
1
1
–
–
–
–
–
–
0
0
–
–
Channel 2: No DRC
–
–
0
1
–
–
Channel 2: Pre-volume DRC
Channel 2: Post-volume DRC
Channel 2: No DRC
–
–
1
0
–
–
–
–
1
1
–
–
D7
D6
D5
–
D4
–
D3
–
D2
–
D1
0
D0
0
FUNCTION
Channel 3: No DRC
–
–
–
–
0
1
Channel 3: Pre-volume DRC
Channel 3: Post-volume DRC
Channel 3: No DRC
–
–
–
–
1
0
–
–
–
–
1
1
80
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.19 DRC2 Control (0x97, Channel 4)
Note that there must be a 10-ms delay between a write to register 0x96 and a write to register 0x97.
Table 6-20. DRC2 Control (0x97, Channel 4)
D31–D2
D1
0
D0
0
FUNCTION
0
0
0
0
0
Channel 4: No DRC
0
0
0
0
1
Channel 4: Pre-volume DRC
Channel 4: Post-volume DRC
Channel 4: No DRC
1
0
1
1
6.20 DRC1 Data Registers (0x98–0x9C)
DRC1 applies to channels 1, 2, and 3.
Table 6-21. DRC1 Data Registers
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
Channel 1, 2, and 3 DRC1 energy
u(31:28), E(27:24), E(23:16), E(15:8), E(7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x98
8
Channel 1, 2, and 3 DRC1 (1 – energy) u(31:28), 1-E(27:24), 1-E(23:16), 1-E(15:8), 1-E(7:0)
Channel 1, 2, and 3 DRC1 threshold
upper 16 bits (T1)
u(31:24), u(23:16), T1(15:8), T1(7:0)
T1(31:24), T1(23:16), T1(15:8), T1(7:0)
u(31:24), u(23:16), T2(15:8), T2(7:0)
T2(31:24), T2(23:16), T2(15:8), T2(7:0)
Channel 1, 2, and 3 DRC1 threshold
lower 32 bits (T1)
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x99
16
Channel 1, 2, and 3 DRC1 threshold
upper 16 bits (T2)
Channel 1, 2, and 3 DRC1 threshold
lower 32 bits (T2)
Channel 1, 2, and 3 DRC1 slope (k0)
Channel 1, 2, and 3 DRC1 slope (k1)
Channel 1, 2, and 3 DRC1 slope (k2)
u(31:24), u(23:16), T2(15:8), T2(7:0) T2(31:24), T2(23:16),
T2(15:8), T2(7:0)
0x9A
12
u(31:24), u(23:16), T1(15:8), T1(7:0) T1(31:24), T1(23:16),
T1(15:8), T1(7:0)
u(31:28), k0(27:24), k0(23:16), k0(15:8), k0(7:0)
u(31:28), k1(27:24), k1(23:16), k1(15:8), k1(7:0)
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
Channel 1, 2, and 3 DRC1 offset 1
upper 16 bits (O1)
Channel 1, 2, and 3 DRC1 offset 1
lower 32 bits (O1)
u(31:28), k2(27:24), k2(23:16), k2(15:8), k2(7:0)
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x9B
0x9C
16
16
Channel 1, 2, and 3 DRC1 offset 2
upper 16 bits (O2)
u(31:24), u(23:16), O1(15:8), O1(7:0) O1(31:24), O1(23:16),
O1(15:8), O1(7:0)
Channel 1, 2, and 3 DRC1 offset 2
lower 32 bits (O2)
u(31:24), u(23:16), O2(15:8), O2(7:0) O2(31:24), O2(23:16),
O2(15:8), O2(7:0)
Channel 1, 2, and 3 DRC1 attack
Channel 1, 2, and 3 DRC1 (1 – attack)
Channel 1, 2, and 3 DRC1 decay
Channel 1, 2, and 3 DRC1 (1 – decay)
u(31:28), A(27:24), A(23:16), A(15:8), A(7:0)
u(31:28), 1-A(27:24), 1-A(23:16), 1-A(15:8), 1-A(7:0)
u(31:28), D(27:24), D(23:16), D(15:8), D(7:0)
u(31:28), 1-D(27:24), 1-D(23:16), 1-D(15:8), 1-D(7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x56
0x00, 0x3F, 0xFF, 0xA8
Serial Control Interface Register Definitions
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SLES169–FEBRUARY 2006
6.21 DRC2 Data Registers (0x9D–0xA1)
DRC1 applies to channel 4.
Table 6-22. DRC2 Data Registers
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF
DEFAULT STATE
CONTENTS
Channel 4 DRC2 energy
u(31:28), E(27:24), E(23:16), E(15:8), E(7:0)
u(31:28), 1-E(27:24), 1-E(23:16), 1-E(15:8), 1-E(7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x9D
8
Channel 4 DRC2 (1 – Energy)
Channel 4 DRC2 threshold upper 16 bits u(31:24), u(23:16), T1(15:8), T1(7:0)
(T1)
Channel 4 DRC2 threshold lower 32 bits T1(31:24), T1(23:16), T1(15:8), T1(7:0)
(T1)
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x9E
16
Channel 4 DRC2 threshold upper 16 bits u(31:24), u(23:16), T2(15:8), T2(7:0)
(T2)
Channel 4 DRC2 threshold lower 32 bits T2(31:24), T2(23:16), T2(15:8), T2(7:0)
(T2)
Channel 4 DRC2 slope (k0)
Channel 4 DRC2 slope (k1)
Channel 4 DRC2 slope (k2)
u(31:28), k0(27:24), k0(23:16), k0(15:8), k0(7:0)
u(31:28), k1(27:24), k1(23:16), k1(15:8), k1(7:0)
u(31:28), k2(27:24), k2(23:16), k2(15:8), k2(7:0)
u(31:24), u(23:16), O1(15:8), O1(7:0)
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0x9F
0xA0
12
16
Channel 4 DRC2 offset 1 upper 16 bits
(O1)
Channel 4 DRC2 offset 1 lower 32 bits
(O1)
O1(31:24), O1(23:16), O1(15:8), O1(7:0)
u(31:24), u(23:16), O2(15:8), O2(7:0)
O2(31:24), O2(23:16), O2(15:8), O2(7:0)
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
Channel 4 DRC2 offset 2 upper 16 bits
(O2)
Channel 4 DRC2 offset 2 lower 32 bits
(O2)
Channel 4 DRC2 attack
u(31:28), A(27:24), A(23:16), A(15:8), A(7:0)
u(31:28), 1-A(27:24), 1-A(23:16), 1-A(15:8), 1-A(7:0)
u(31:28), D(27:24), D(23:16), D(15:8), D(7:0)
u(31:28), 1-D(27:24), 1-D(23:16), 1-D(15:8), 1-D(7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x56
0x00, 0x3F, 0xFF, 0xA8
Channel 4 DRC2 (1 – attack)
Channel 4 DRC2 decay
0xA1
16
Channel 4 DRC2 (1 – decay)
6.22 DRC Bypass Registers (0xA2, 0xA3, 0xA8, 0xA9)
DRC bypass/inline for channels 1, 2, 3, and 4 are mapped into registers 0xA2, 0xA3, 0xA8, and 0xA9.
8-bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x0080 0000 is a
gain of 1. Each gain coefficient is written as a 32-bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x0000 0000 and inline = 0x0080 0000.
To disable DRC for a given channel, bypass = 0x0080 0000 and inline = 0x0000 0000.
Table 6-23. DRC Bypass Registers Format (0xA2–0xA9)
REGISTER
NAME
TOTAL
BYTES
CONTENTS
INITIALIZATION
VALUE
Channel bass DRC bypass
Channel DRC inline
u(31:28), bypass(27:24), bypass(23:16), bypass(15:8), bypass(7:0)
u(31:28), inline(27:24), inline(23:16), inline(15:8), inline(7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
8
82
Serial Control Interface Register Definitions
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SLES169–FEBRUARY 2006
6.23 4 × 2 Output Mixer Registers (0xAA and 0xAB)
The pass-through output mixer setting is:
•
•
DAP channel 1 is mapped though the 8 × 2 crossbar mixer (0xAA) to PWM channel 1
DAP channel 2 is mapped though the 8 × 2 crossbar mixer (0xAB) to PWM channel 2
Total data per register is 8 bytes.
Note that the pass-through output mixer configuration (0xD0 bit 30 = 1) is recommended. Using the
remapped output mixer configuration (0xD0 bit 30 = 0) increases the complexity of using some features
such as volume and mute. See TAS5504A Errata (SLEZ006).
Table 6-24. Output Mixer Control Register Format (Upper 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
Table 6-25. Output Mixer Control (Lower 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
Serial Control Interface Register Definitions
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TAS5504A
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SLES169–FEBRUARY 2006
6.24 4 × 3 Output Mixer Registers (0xB0–0xB1)
The pass-through output mixer setting is:
•
•
DAP channel 3 is mapped though the 8 × 3 crossbar mixer (0xB0) to PWM channel 3.
DAP channel 4 is mapped though the 8 × 3 crossbar mixer (0xB1) to PWM channel 4.
Note that the default setting is recommended for most systems. Any variation from this setting increases
the complexity of using some features such as volume and mute. See TAS5504A Errata (SLEZ009).
Total data per register is 12 bytes.
Table 6-26. Output Mixer Control (Lower 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
Table 6-27. Output Mixer Control (Middle 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
84
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Table 6-28. Output Mixer Control (Lower 4 Bytes)
D31
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
0
0
0
0
0
0
1
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
1
1
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
6.25 PSVC Volume Biquad Register (0xCF)
Each gain coefficient is in 28-bit (5.23) format, so 0x8000 0000 is a gain of 1. Each gain coefficient is
written as a 32-bit word with the upper four bits not used. Note that this register should be used only with
the PSVC feature. For systems not using this feature, it is recommended that this biquad be set to all-pass
(default).
Table 6-29. Volume Biquad Register Format (Default = All-pass)
DESCRIPTION
REGISTER FIELD CONTENTS
DEFAULT GAIN COEFFICIENT VALUES
DECIMAL
1.0
HEX
b0 coefficient
u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)
u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)
u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)
u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)
u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
b1 coefficient
b2 coefficient
a1 coefficient
a2 coefficient
0.0
0.0
0.0
0.0
Serial Control Interface Register Definitions
85
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.26 Volume, Treble, and Bass Slew Rates Register (0xD0)
Table 6-30. Volume Gain Update Rate (Slew Rate)
D31
0
D30
0
D29-D10
D9
x
D8
x
FUNCTION
Remapped output mixer configuration (not recommended)
Pass-through output mixer configuration (recommended)
512-step update at 4 fS, 42.6 ms at 48 kHz
0
0
0
0
0
0
0
1
x
x
0
0
0
0
0
1
1024-step update at 4 fS, 85.3 ms at 48 kHz
2048-step update at 4 fS, 170 ms at 48 kHz
0
1
0
0
1
1
2048-step update at 4 fS, 170 ms at 48 kHz
Table 6-31. Treble and Bass Gain Step Size (Slew Rate)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
0
0
0
0
No operation
0
0
0
0
1
0
0
Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz)
Update ever 0.67 ms (32 LRCLKs at 48 kHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Default rate – Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the
maximum constant time that can be set for all sample rates.
1
1
1
1
1
1
1
1
Minimum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)
6.27 Volume Registers (0xD1, 0xD2, 0xD7, and 0xD8)
Channels 1, 2, 3, and 4 are mapped into registers 0xD1, 0xD2, 0xD7, and 0xD8. The default for all
channels is 0 dB.
Master volume is mapped into register 0xD9. The default for the master volume is mute.
Bits D31–D12 are don't care.
Table 6-32. Volume Registers
D31
D23
D15
D30
D22
D14
D29
D21
D13
D28
D20
D12
D27
D19
D26
D18
D25
D24
FUNCTION
FUNCTION
FUNCTION
FUNCTION
Unused bits
Unused bits
Volume
D17
D16
D11
V11
D10
D9
D8
V8
V10
V9
D7
V7
D6
V6
D5
V5
D4
V4
D3
V3
D2
V2
D1
V1
D0
V0
Volume
86
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
Table 6-33. Master and Individual Volume Controls
VOLUME INDEX (H)
GAIN (dB)
17.75
17.5
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
17.25
17
16.75
16.5
16.25
16
15.75
15.5
15.25
15
14.75
14.5
14.25
14
TO
044
045
046
047
048
049
04A
04B
04C
1
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1
TO
1F8
1F9
1FA
1FB
1FC
1FD
–108
–108.25
–108.5
–108.75
-109
Mute
TO
245
Mute
Serial Control Interface Register Definitions
87
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.28 Bass Filter Set Register (0xDA)
The bass and treble bypass registers (0x89–0x90) must be configured as inline (default is bypass).
Table 6-34. Channel 4 Subwoofer
D31
0
D30
0
D29
0
D28
0
D27
0
D26
0
D25
0
D24
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Reserved
Table 6-35. Channel 3, 2, 1 (Center, Right Front, and Left Front)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Reserved
88
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.29 Bass Filter Index Register (0xDB)
Index values above 0x24 are invalid. The bass and treble bypass registers (0x89–0x90) must be
configured as inline (default is bypass).
Table 6-36. Bass Filter Index Register
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF
CONTENTS
DEFAULT STATE
Bass filter index (BFI) Ch4_BFI(31:24), NONE(23:16), NONE(15:8),
Ch321_BFI(7:0)
0x12, 0xxx, 0xxx, 0x12
0xDB
4
Table 6-37. Bass Filter Index Table
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
18
17
16
15
14
13
12
11
10
9
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
8
7
6
5
4
3
2
1
0
Serial Control Interface Register Definitions
89
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.30 Treble Filter Set Register (0xDC)
Bits D31–D27 are don't care. The bass and treble bypass registers (0x89–0x90) must be configured as
inline (default is bypass).
Table 6-38. Channel 4 Subwoofer
D31
0
D30
0
D29
0
D28
0
D27
0
D26
0
D25
0
D24
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Reserved
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Reserved
Table 6-39. Channel 3, 2, 1 (Center, Right Front, and Left Front)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Reserved
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Reserved
90
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.31 Treble Filter Index (0xDD)
Index values above 0x24 are invalid. The bass and treble bypass registers (0x89–0x90) must be
configured as inline (default is bypass).
Table 6-40. Treble Filter Index Register
I2C SUB-
ADDRESS
TOTAL
BYTES
REGISTER
NAME
DESCRIPTION OF
CONTENTS
DEFAULT STATE
Treble filter index
(BFI)
Ch4_TFI(31:24), NONE(23:16), NONE(15:8),
Ch321_TFI(7:0)
0x12, 0x12, 0x12, 0x128
0xDD
4
Table 6-41. Treble Filter Index
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
18
17
16
15
14
13
12
11
10
9
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
8
7
6
5
4
3
2
1
0
Serial Control Interface Register Definitions
91
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.32 AM Mode Register (0xDE)
Bits D31–D21 are don't care.
Table 6-42. AM Mode Register
D31
D23
D30
D22
D29
D21
D28
D27
D26
D25
D24
FUNCTION
FUNCTION
Unused bits
D20
0
D19
–
D18
–
D17
–
D16
–
AM mode disabled
AM mode enabled
1
–
–
–
–
–
0
0
–
–
Select sequence 1
Select sequence 2
–
0
1
–
–
–
1
0
–
–
Select sequence 3
–
1
1
–
–
Select sequence 4
–
–
–
0
–
IF frequency 455
–
–
–
1
–
IF frequency 262.5
Use BCD tuned frequency
Use binary tuned frequency
–
–
–
–
0
–
–
–
–
1
Table 6-43. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)
D15
0
D14
0
D13
0
D12
B0
–
D11
–
D10
–
D9
–
D8
–
FUNCTION
BCD frequency (1000s kHz)
BCD frequency (100s kHz)
Default value
–
–
–
B3
0
B2
0
B1
0
B0
0
0
0
0
0
D7
0
D6
0
D5
0
D4
B0
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
BCD frequency (100s kHz)
BCD frequency (1s kHz)
Default value
–
–
–
B3
0
B2
0
B1
0
B0
0
0
0
0
0
Table 6-44. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)
D15
0
D14
0
D13
0
D12
0
D11
0
D10
B10
0
D9
B9
0
D8
B8
0
FUNCTION
Binary frequency (upper 3 bits)
0
0
0
0
0
Default value
D7
B7
0
D6
B6
0
D5
B5
0
D4
B4
0
D3
B3
0
D2
B2
0
D1
B1
0
D0
B0
0
FUNCTION
Binary frequency (lower 8 bits)
Default value
92
Serial Control Interface Register Definitions
TAS5504A
4-Channel Digital Audio PWM Processor
www.ti.com
SLES169–FEBRUARY 2006
6.33 PSVC Range Register (0xDF)
Bits D31–D2 are zero.
Table 6-45. Volume Gain Update Rate (Slew Rate)
D31–D2
D1
0
D0
0
FUNCTION
0
0
0
0
12-dB control range for PSVC
18-dB control range for PSVC
24-dB control range for PSVC
Ignore – retain last value
0
1
1
0
1
1
6.34 General Control Register (0xE0)
Bits D31–D4 are zero. Bits D1 and D0 are don't care.
Table 6-46. General Control Register
D31–D4
D3
0
D2
0
D1
–
D0
–
FUNCTION
Power supply volume control disable
0
0
0
1
–
–
Power-supply volume-control enable
–
–
–
Subwoofer part of PSVC. This bit must always be 0 (D3 is a write-only bit).
6.35 Incremental Multiple-Write Append Register (0xFE)
This is a special register used to append data to a previously opened register. See Multiple-Byte Write,
Section 4.4, for programming details.
7
TAS5504A Example Application Schematic
The following page contains an example application schematic for the TAS5504A.
TAS5504A Example Application Schematic
93
5
4
3
2
1
D
C
B
A
D
C
B
A
Left + Right Headphone
+5.0V
+5.0V
+3.3V
2
R20
22.0R
1
PWM_HPM_L
PWM_HPP_L
PWM_HPM_R
PWM_HPP_R
J900
C25
220nF
C26
10uF
V-HBRIDGE
4
3
2
1
OUT_R
GVDD
HEADPHONE OUTPUT
/SD2_TAS5121
/OTW_TAS5121
OUT_GND
OUT_L
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
Mini-Jack (3.5mm)
GND
2 Channel Headphone Design (TPA112)
PWM_P
PWM_M
/VALID
1
2
SUBWOOFER
SPEAKER
OUTPUT
OUT_1
OUT_2
/VALID
J800
CH4 TAS5121 H-Bridge Output Stage
V-HBRIDGE
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
MCLK
PWM_P
PWM_M
/VALID
1
2
CENTER
SPEAKER
OUTPUT
OUT_1
OUT_2
/VALID
J700
CH3 TAS5121 H-Bridge Output Stage
C29
100nF
C10
10nF
R10
200R
R11
200R
C13
10nF
C14
100nF
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VRA_PLL
VR_PWM
NC
C11
100nF
C12
100nF
2
PLL_FLT_RET
3
4
PLL_FLTM
PLL_FLTP
AVSS
NC
NC
5
NC
6
AVSS
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VAILD
7
VRD_PLL
AVSS_PLL
AVDD_PLL
VBGAP
RESET
HP_SEL
PDN
U10
+3.3V R12
8
2R
TAS5504
1
2
9
10
11
12
13
14
15
16
/VALID
/RESET_TAS5504
/HP_SEL
DVSS
C15
C16
C17
100nF
C18
100nF
10uF
1nF
/BKND_ERR_TAS5504
BKND_ERR
DVDD
+3.3V
/PDN_TAS5504
/MUTE_TAS5504
MUTE
DVSS
R13
R18
1R
3.30R
DVDD
DVSS
V-HBRIDGE
DVSS
VR_DIG
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
GND
+3.3V
C22
100nF
C23
10uF
C24
100nF
PWM_P
PWM_M
/VALID
R14
1
2
RIGHT
SPEAKER
OUTPUT
1R
OUT_1
OUT_2
/VALID
GND
J200
C19
C20
C21
CH2 TAS5121 H-Bridge Output Stage
10uF
100nF
100nF
V-HBRIDGE
GVDD
+5.0V +3.3V
V-HBRIDGE
GND
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GND
PSVC_TAS5504
SDIN1
SDIN2
SDIN3
SDIN4
SCLK
GVDD
/RESET
/RESET
PWM_P
PWM_M
/VALID
X10
1
2
LEFT
SPEAKER
OUTPUT
/RESET_TAS5504
/RESET_TAS5504
OUT_1
OUT_2
/VALID
J100
13.5MHz
/BKND_ERR
/BKND_ERR
CH1 TAS5121 H-Bridge Output Stage
2
1
/BKND_ERR_TAS5504
/BKND_ERR_TAS5504
LRCLK
SCL
R21
1M
C27
15pF
C28
15pF
/SD1_TAS5121
/SD1
/SD1_TAS5121
/SD1
PSVC_TAS5504
SDA
PSVC_TAS5504
/SD2_TAS5121
/SD2
/SD2_TAS5121
/SD2
TAS5504 Example Application Schematic
/VALID
/VALID
/OTW_TAS5121
/OTW
/OTW_TAS5121
/OTW
(Circuit is Subject To Change Without Notice)
PSU and Interface Logic
5
4
3
2
1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2006
PACKAGING INFORMATION
Orderable Device
TAS5504APAG
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PAG
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5504APAGG4
TAS5504APAGR
TAS5504APAGRG4
TQFP
TQFP
TQFP
PAG
PAG
PAG
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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