TAS5504PAGR [TI]
4 Channel Digital Audio PWM Processor; 4通道数字音频PWM处理器
| 型号： | TAS5504PAGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4 Channel Digital Audio PWM Processor |
| 文件： | 总96页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
TAS5504
4 Channel Digital Audio PWM Processor
Data Manual
2004
DAV−Digital Audio/Speaker
SLES123
IMPORTANT NOTICE
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Copyright 2004, Texas Instruments Incorporated
Contents
Page
Contents
Section
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
TAS5504 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1
1.1.2
1.1.3
1.1.4
Audio Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PWM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
1.3
Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1
1.2.2
1.2.3
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TAS5504 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock, PLL, and Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I C Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Audio Processor (DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
1.4
TAS5504 DAP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1
1.4.2
TAS5504 DAP Architecture Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I C Coefficient Number Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
1.5
1.6
1.7
1.8
Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bass and Treble Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Volume, Auto Mute, and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.8.1
Auto Mute and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.9
Loudness Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.9.1
1.10.2
Loudness Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Compression/Expansion Coefficient Computation Engine Parameters . . . . . . . . . . . . . . 25
1.11
1.12
Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.12.1
1.12.2
1.12.3
1.12.4
DC Blocking (High Pass Enable/ Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Supply Volume Control (PSVC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AM Interference Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
TAS5504 Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
2.1
I C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1.1
2.1.2
General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2
TAS5504 Pin Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Down (PDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Speaker/Headphone Selector (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Mute (MUTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3
Device Configuration Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.1
2.3.2
Channel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Headphone Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
iii
October 2004
SLES123
Contents
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Audio System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Recovery from Clock Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power Supply Volume Control Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Volume and Mute Update Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Modulation Index Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Inter-channel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4
2.5
Master Clock and Serial Data Rate Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.1 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bank Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
Manual Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Automatic Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bank Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bank Switch Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bank Switching Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bank Switching Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1
3.2
3.3
3.4
3.5
3.6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Dynamic Performance (At Recommended Operating Conditions at 25°C) . . . . . . . . . . . . . . . . . . . . 43
Recommended Operating Conditions (over 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44
PWM Operation at Recommended Operating Conditions Over 0°C to 70°C . . . . . . . . . . . . . . . . . . . 44
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.9
Clock Signals Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 44
Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I C Serial Control Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reset Timing (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-Down (PDN) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
MUTE Timing—MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Headphone Select (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2
3.7
Serial Audio Interface Control and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2
3.7.1
3.7.2
3.7.3
I S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Left Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Right Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2
4
I C Serial Control Interface (Slave Address 0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
General I C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Single and Multiple Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Single Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Incremental Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2
5
6
Serial Control I C Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Serial Control Interface Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1
6.2
6.3
6.4
Clock Control Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
General Status Register 0 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
iv
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6.5
6.6
6.7
6.8
System Control Register 2 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Channel Configuration Control Register (0x05−X0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Headphone Configuration Control Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Serial Data Interface Control Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Soft Mute Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Automute Control Register(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Automute PWM Threshold and Backend Reset Period (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Modulation Index Limit Register (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23) . . . . . . . . . . . . . . 68
Bank Switching Command (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Input Mixer Registers (0x41, 0x42, 0x47, 0x48, Channels 1−4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Bass Management Registers (0x49–0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Biquad Filters Register (0x51 – 0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Loudness Registers (0x91 – 0x95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DRC1 Control (0x96, Channels 1−3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DRC2 Control (0x97, Channel 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DRC1 Data Registers (0x98 – 0x9C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DRC2 Data Registers (0x9D – 0xA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DRC Bypass Registers (0xA2, 0xA3, 0xA8, 0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4x2 Output Mixer Registers (0xAA and 0xAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4x3 Output Mixer Registers (0xB0 – 0xB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Volume Biquad Register (0xCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Volume Treble and Bass Slew Rates (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Volume Registers (0xD1, 0xD2, 0xD7, and 0xD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Bass Filter Set Register (0xDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Bass Filter Index Register (0xDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Treble Filter Set Register (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Treble Filter Index (0xDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
AM Mode Register (0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PSVC Range Register (0xDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
General Control Register (0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Incremental Multiple Write Append Register (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
6.33
6.34
6.35
6.36
6.37
7
TAS5504 Example Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
v
October 2004
SLES123
List of Illustrations
List of Illustrations
Figure
Title
Page
1−1 TAS5504 Functional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
1−2 TAS5504 DAP Architecture With I C Registers (Fs ≤ 96 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
1−3 TAS5504 Architecture With I C Registers (Fs = 176.4 kHz or Fs = 192 kHz) . . . . . . . . . . . . . . . . . . . . 11
1−4 TAS5504 Detailed Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1−5 5.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1−6 Conversion Weighting Factors—5.23 Format to Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
1−7 Alignment of 5.23 Coefficient in 32-Bit I C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1−8 25.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
1−9 Alignment of 5.23 Coefficient in 32-Bit I C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
1−10 Alignment of 25.23 Coefficient in Two 32-Bit I C Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1−11 TAS5504 Digital Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1−12 Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1−13 Biquad Filter Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1−14 Auto Mute Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1−15 Loudness Compensation Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1−16 Loudness Example Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1−17 DRC Positioning in TAS5504 Processing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1−18 Dynamic Range Compression (DRC) Transfer Function Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1−19 TAS5504 Attack and Decay Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1−20 Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1−21 De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1−22 Power Supply and Digital Gains (Log Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1−23 Power Supply and Digital Gains (Linear Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1−24 Block Diagrams of Typical Systems Requiring TAS5504 Automatic AM Interference
Avoidance Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3−1 Slave Mode Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3−2 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3−3 Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3−4 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3−5 Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3−6 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3−7 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3−8 HP_SEL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2
3−9 I S Format 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3−10 Left Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3−11 Right Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2
4−1 Typical I C Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4−2 Single Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4−3 Multiple Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4−4 Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4−5 Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
vi
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October 2004
List of Tables
List of Tables
Table
Title
Page
1−1 Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1−2 TAS5504 Audio Processing Feature Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1−3 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1−4 Bass and Treble Filter Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1−5 Linear Gain Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1−6 Default Loudness Compensation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1−7 Loudness Function Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1−8 DRC Recommended Changes From TAS5504 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2−1 Device Outputs During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2−2 Values Set During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2−3 Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2−4 Device Outputs During Backend Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2−5 Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C) . . . . . . . . . . . . . . . . . . . . . . . 37
2−6 Recommended TAS5504 Configurations for Texas Instruments Power Stages . . . . . . . . . . . . . . . . . . . . . . . 37
2−7 Audio System Configuration (General Control Register 0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2−8 Volume Ramp Rates in ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2−9 Inter-Channel Delay Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6−1 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6−2 General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6−3 Error Status Register (0X02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6−4 System Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6−5 System Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6−6 Channel Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6−7 Headphone Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6−8 Serial Data Interface Control Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6−9 Soft Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6−10 Automute Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6−11 Automute PWM Threshold and Backend Reset Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6−12 Modulation Index Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6−13 Interchannel Channel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6−14 Channel Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6−15 Bank Switching Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6−16 Input Mixer Registers Format (Channels 1−4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6−17 Bass Management Registers Format (0x49 – 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6−18 Biquad Filters Registers Format (0x51 – 0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6−19 Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass) . . . . . . . . . . . . . . . . . . . . . . . . 73
6−20 Bass and Treble Bypass Register Format (0x89−0x90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6−21 Loudness Registers Format (0x91 – 0x95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6−22 DCR1 Control (0x96, Channels 1−3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6−23 DRC2 Control (0x97, Channel 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6−24 DRC1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6−25 DRC2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6−26 DRC Bypass Registers Format (0xA2−0xA9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6−27 Output Mixer Control Register Format (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6−28 Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6−29 Output Mixer Control (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6−30 Output Mixer Control (Middle 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
vii
October 2004
SLES123
List of Tables
6−31 Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6−32 Volume Biquad Register Format (Default = All-pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6−33 Volume Gain Update Rate (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6−34 Treble and Bass Gain Step Size (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6−35 Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6−36 Master and Individual Volume Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6−37 Channel 4 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6−38 Channel 3, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6−39 Bass Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6−40 Bass Filter Index Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6−41 Channel 4 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6−42 Channel 3, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6−43 Treble Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6−44 Treble Filter Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6−45 AM Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6−46 AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6−47 AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6−48 PSVC Range Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6−49 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
viii
SLES123
October 2004
Introduction
1
Introduction
The TAS5504 is a four channel digital pulse width modulator (PWM) that provides both advanced performance
and a high level of system integration. The TAS5504 is designed to interface seamlessly with most audio digital
signal processors. The TAS5504 automatically adjusts control configurations in response to clock and data
rate changes and idle conditions. This enables the TAS5504 to provide an easy to use control interface with
relaxed timing requirements.
The TAS5504 can drive four channels of H-bridge power stages. Texas Instruments H-bridge parts TAS5111,
TAS5112, or TAS5182 + FETs are designed to work seamlessly with the TAS5504. The TAS5504 supports
both single-ended or bridge tied load configurations. The TAS5504 also provides a high performance
differential output to drive an external differential input analog headphone amplifier (such as the TPA112).
The TAS5504’s uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.
th
The 8x over sampling combined with the 5 order noise shaper provides a broad flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
The TAS5504 is clock slave only device. The TAS5504 receives MCLK, SCLK and LRCLK from other system
components. The TAS5504 accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs. The TAS5504
accepts a 64-Fs bit clock.
The TAS5504 allows for extending the dynamic range by providing a power supply volume control (PSVC)
output signal.
Power Supply
MCLK
XTL_OUT
XTL_IN
PLL_FLTM
PLL_FLTP
OSC_CAP
SCLK
PWM_HPPR
PWM_HPMR
Digital Audio Processor
PWM Section
PWM_HPPL
PWM_HPML
0
7
Soft Loud
Vol Comp
DC
De− Interpo−
Block Emph late
Soft
Tone
DRC
DRC
DRC
DRC
SRC NS PWM
SRC NS PWM
SRC NS PWM
PWM_P_1
PWM_M_1
Det Biquads
LRCLK
SDIN1
Control
SDIN2
0
7
Soft Loud
Vol Comp
DC
De− Interpo−
Block Emph late
Soft
Tone
PWM_P_2
PWM_M_2
Det Biquads
SDIN3
SDIN4
Serial
Control
I/F
SDA
SCL
0
7
Soft
Tone
Soft Loud
Vol Comp
DC
De− Interpo−
Block Emph late
PWM_P_3
PWM_M_3
Det Biquads
/RESET
/PDN
0
7
Soft Loud
Vol Comp
DC
De− Interpo−
Block Emph late
Soft
Tone
PWM_P_4
PWM_M_4
SRC NS PWM
4
/MUTE
/HP_SEL
Det Biquads
4
2
4
4
2
2
8
/BKND_ERR
VALID
PSVC
5
Volume
Control
PSVC
Figure 1−1. TAS5504 Functional Structure
1
SLES123 − October 2004
TAS5504
Introduction
1.1 TAS5504 Features
1.1.1 Audio Input / Output
•
•
•
•
•
•
•
•
•
Automatic Master Clock Rate and Data Sample Rate Detection
Four Serial Audio Input Channels
Four PWM Audio Output Channels
Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112
PWM Outputs Support Single Ended and Bridge Tied Loads
32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates
2
Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I S,
64 x Fs Bit Clock Rate
128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates (Up to a Maximum of 50 MHz)
1.1.2 Audio Processing
•
•
48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features
Volume Control Range +36 dB to – 127 dB
−
−
Master Volume Control Range of +18 dB to –100 dB
Four Individual Channel Volume Control Range of +18-dB to −127-dB
•
•
Programmable Soft Volume and Mute Update Rates
nd
Four Bass and Treble Tone Controls with 18-dB Range, Selectable Corner Frequencies, and 2 Order
Slopes
−
−
L, R, and C
LS, RS
•
•
•
•
Configurable Loudness Compensation
Two Dynamic Range Compressors With Two Thresholds, Two Offsets, and Three Slopes
Seven Bi-quads Per Channel
8x4 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input
Channels
•
•
•
4x2 Output Mixer – Channels 1 and 2. Each Output Can Be Any Ratio of Any Two Signal Processed
Channels
4x3 Output Mixer – Channels 3 and 4. Each Output can be Any Ratio of Any Three Signal Processed
Channels
Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically (Based on
Specific Data Rates)
•
•
DC Blocking Filters
Able to Support a Variety of Bass Management Algorithms
2
TAS5504
SLES123 − October 2004
Introduction
1.1.3 PWM Processing
•
•
32-Bit Processing PWM Architecture With 40 Bits of Precision
th
8x Oversampling With 5 Order Noise Shaping at 32 – 48 kHz, 4x Oversampling at 88.2 kHz, and 96 kHz
and 2x Oversampling at 176.4 kHz and 192 kHz
•
•
•
•
•
•
•
>102-dB Dynamic Range
THD+N < 0.1%
20 – 20-kHz Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates
Digital De-emphasis for 32-, 44.1-, and 48-kHz Data Rates
Flexible Automute Logic With Programmable Threshold and Duration for Noise Free Operation
Intelligent AM Interference Avoidance System Provides Clear AM Reception
Power Supply Volume Control (PSVC) Support for Enhanced Dynamic Range in High Performance
Applications
•
Adjustable Modulation Limit
1.1.4 General Features
•
•
•
•
•
•
Automated Operation With an Easy to Use Control Interface
2
I C Serial Control Slave Interface
Integrated AM Interference Avoidance Circuitry
Single 3.3-V Power Supply
64-Pin TQFP Package
5-V Tolerant Inputs
3
SLES123 − October 2004
TAS5504
Introduction
1.2 Physical Characteristics
1.2.1 Terminal Assignments
TQFP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
VRA_PLL
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
AVSS
VR_PWM
NC
NC
NC
NC
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VALID
DVSS
BKND_ERR
DVDD
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
5
6
AVSS
7
VRD_PLL
AVSS_PLL
AVDD_PLL
VBGAP
8
9
10
11
12
13
14
15
16
RESET
HP_SEL
PDN
MUTE
DVDD
DVSS
DVSS
VR_DIG
DVSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1.2.2 Ordering Information
T
A
PLASTIC 64-PIN PQFP (PN)
0°C to 70°C
TAS5504PAG
1.2.3 Terminal Descriptions
TERMINAL
5-V
TOLERANT
TERMIN-
ATION
I/O
DESCRIPTION
NO.
NAME
1
VRA_PLL
Voltage reference for PLL analog supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
2
3
4
5
6
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
AVSS
AO
AO
AI
P
PLL external filter return
PLL negative input. Connected to PLL_FLT_RTN via an RC network
PLL positive input. Connected to PLL_FLT_RTN via an RC network
Analog ground
AVSS
P
Analog ground
4
TAS5504
SLES123 − October 2004
Introduction
TERMINAL
NAME
5-V
TOLERANT
TERMIN-
ATION
I/O
DESCRIPTION
NO.
7
VRD_PLL
P
Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
8
AVSS_PLL
P
Analog ground for PLL. This terminal should reference the same ground as power
terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be
minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground distribution techniques to achieve a quiet ground reference
at this terminal.
9
AVDD_PLL
P
P
3.3-V analog power supply for PLL This terminal can be connected to the same
power source used to drive power terminal DVSS, but to achieve low PLL jitter, this
terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor.
10 VBGAP
Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.
Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
11
RESET
DI
5 V
Pull up
System reset input, active low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that restores the
TAS5504 to its default conditions, sets the valid output low, and places the PWM
in the hard mute (M) state. Master volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 4−5 ms. device
initialization and set the volume at mute.
12 HP_SEL
13 PDN
DI
DI
5 V
5 V
Pull up
Pull up
Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected –
headphone is off.
Power down, active low. PDN powers down all logic and stops all clocks whenever
a logic low is applied. The internal parameters are preserved through a power down
cycle, as long as a RESET is not active. The duration for system recovery from
power down is 100 ms.
14 MUTE
DI
5 V
Pull up
Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a
logic high) The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
15 DVDD
16 DVSS
P
P
P
Digital power 3.3-V supply for digital core and most of I/O buffers
Digital ground for digital core and most of I/O buffers
17 VR_DPLL
Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital PLL logic. A 0.1−µF low ESR capacitor should be
connected between this terminal and DVSS_CORE. This terminal must not be
used to power external devices.
18 OSC_CAP
19 XTL_OUT
AO
AO
Oscillator capacitor
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5504 via use of an external fundamental mode
crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the
recommended crystal type.
20 XTL_IN
AI
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5504 via use of an external fundamental mode
crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4 for the
recommended crystal type.
21 RESERVED
22 RESERVED
23 RESERVED
24 SDA
Connect to digital ground
Connect to digital ground
Connect to digital ground
2
DIO
DI
5 V
5 V
5 V
5 V
I C serial control data interface input / output
2
25 SCL
I C serial control clock input output
26 LRCLK
27 SCLK
DI
Serial audio data left / right clock (sampling rate clock)
DI
Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data
bit clock that is supplied to the serial bit clock to other I S bus.
2
5
SLES123 − October 2004
TAS5504
Introduction
TERMINAL
NAME
5-V
TOLERANT
TERMIN-
ATION
I/O
DESCRIPTION
NO.
28 SDIN4
29 SDIN3
30 SDIN2
31 SDIN1
DI
5 V
5 V
5 V
5 V
Pulldown Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
DI
DI
DI
Pulldown Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Pulldown Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Pulldown Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
32 PSVC
O
P
Power supply volume control PWM output
33 VR_DIG
Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be
connected between this terminal and DVSS. This terminal must not be used to
power external devices
34 DVSS
P
P
Digital ground
35 DVSS
Digital ground
36 DVDD
P
3.3-V digital power supply
37 BKND_ERR
DI
Pull up
Active low. A backend error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in all system parameters unaffected, while all
H-bridge drive signals going to a hard mute (M) state.
38 DVSS
39 VALID
40 PWM_M_1
41 PWM_P_1
42 PWM_M_2
43 PWM_P_2
44 NC
P
Digital ground
DO
DO
DO
DO
DO
Output indicating validity of PWM outputs active high
PWM 1 output (differential −)
PWM 1 output (differential +)
PWM 2 output (differential −)
PWM 2 output (differential +)
No connection
45 NC
No connection
46 NC
No connection
47 NC
No connection
48 VR_PWM
P
Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor
should be connected between this terminal and DVSS_PWM. This terminal must
not be used to power external devices.
49 PWM_M_3
50 PWM_P_3
51 PWM_M_4
52 PWM_P_4
53 DVSS_PWM
54 DVDD_PWM
55 NC
DO
DO
DO
DO
P
PWM 3 Output (differential −)
PWM 3 Output (differential +)
PWM 4 Output (differential −)
PWM 4 Output (differential +)
Digital ground for PWM
P
3.3-V digital power supply for PWM
No connection
56 NC
No connection
57 NC
No connection
58 NC
No connection
59 PWM_HPML
60 PWM_HPPL
61 PWM_HPMR
62 PWM_HPPR
DO
DO
DO
DO
PWM left channel headphone (differential −)
PWM left channel headphone (differential +)
PWM right channel headphone (differential −)
PWM right channel headphone (differential +)
6
TAS5504
SLES123 − October 2004
Introduction
TERMINAL
NAME
5-V
TOLERANT
TERMIN-
ATION
I/O
DESCRIPTION
NO.
63 MCLK
DI
5 V
Pulldown MCLK is a 3.3-V clock master clock input. The input frequency of this clock can
range from 4 MHz to 50 MHz.
64 RESERVED
Connect to digital ground
NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output
2. All pullups are 200-µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pull ups must be able to sink 200 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must
be able to source 200 µA, while maintaining a logic ‘1’ drive level.
3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
4. 13.5-MHz crystal (HCM49)
1.3 TAS5504 Functional Description
Figure 1−2 shows the TAS5504 functional structure. The next sections describe the TAS5504 functional
blocks:
•
•
•
•
•
•
Power Supply
Clock, PLL, and Serial Data Interface
Serial Control Interface
Device Control
Digital Audio Processor (DAP)
Pulse Width Modulation (PWM) Processor
1.3.1 Power Supply
The power supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5504. The analog supply supports the analog PLL, while digital supplies support
the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control
(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.
1.3.2 Clock, PLL, and Serial Data Interface
The TAS5504 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts
MCLK, SCLK, and LRCLK as inputs only.
The TAS5504 uses the external crystal to provide a time base for:
•
•
•
•
Continuous data and clock error detection and management
Automatic data rate detection and configuration
Automatic MCLK rate detection and configuration (automatic bank switching)
2
Supporting I C operation/ communication while MCLK is absent
The TAS5504 automatically handles clock errors, data rate changes, and master clock frequency changes
without requiring intervention from an external system controller. This feature significantly reduces system
complexity and design.
7
SLES123 − October 2004
TAS5504
Introduction
1.3.2.1 Serial Audio Interface
The TAS5504 operates as a slave only / receive only serial data interface in all modes. The TAS5504 has four
PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2,
SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format.
2
The serial data input interface of the TAS5504 can be configured in right justified, I S, or left-justified modes.
2
The serial data interface format is specified using the I C data interface control register. The supported formats
and word lengths are shown in Table 1−1.
Table 1−1. Serial Data Formats
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
Right justified
Right justified
Right justified
I2S
16
20
24
16
20
24
16
20
24
I2S
I2S
Left Justified
Left Justified
Left Justified
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5504 accepts 32-, 38-, 44.1-, 48-, 88.2-,
2
96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I S serial data formats using
a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).
2
The parameters of this clock and serial data interface are I C configurable.
1.3.3 I2C Serial Control Interface
2
The TAS5504 has an I C serial control slave interface (address 0x36) to receive commands from a system
controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz)
operations without wait states. Since the TAS5504 has a crystal time base, this interface operates even when
MCLK is absent.
The serial control interface supports both single byte and multi-byte read / write operations for status registers
and the general control registers associated with the PWM. However, for the DAP data processing registers,
the serial control interface also supports multiple byte (4 byte) write operations.
2
2
The I C supports a special mode which permits I C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations
that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.
2
This permits the system to incrementally write large register values without blocking other I C transactions.
In order to use this feature, the first chunk of data is written to the target I C address and each subsequent
2
chunk of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent.
An incremental read operation is not supported.
1.3.4 Device Control
The TAS5504 control section provides the control and sequencing for the TAS5504. The device control
provides both high and low level control for the serial control interface, clock and serial data interfaces, digital
audio processor, and pulse width modulator sections.
8
TAS5504
SLES123 − October 2004
Introduction
1.3.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio processing functions – soft volume, loudness
compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing.
Figure 1−4 shows the TAS5504 DAP architecture.
The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32-kHz – 96-kHz data and one for 176.4-kHz to 192-kHz data.
1.3.5.1 TAS5504 Audio Processing Configurations
The 32 − 96 kHz configuration supports four channels of data processing.
The 176.4 − 192 kHz configuration supports three channels of signal processing with one channel passed
though (or derived from the three processed channels).
To efficiently support the processing requirements of both multi-channel 32 – 96-kHz data and the two channel
176.4 and 192-kHz data, the TAS5504 supports separate audio processing features for 32 –96-kHz data rates
and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5504 processing feature sets.
1.3.5.2 TAS5504 Audio Signal Processing Functions
The DAP provides 10 primary signal processing functions.
1. The data processing input has an 8x4 input crossbar mixer. This enables each input to be any ratio of the
eight input channels.
2
2. Two I C programmable threshold detectors in each channel support auto mute.
3. Seven biquads per channel
4. Four soft bass and treble tone controls with 18 dB range, programmable corner frequencies, and 2nd
order slopes. In 4-channel mode, bass and treble controls are normally configured as follows:
−
−
Bass and Treble 1: Channel 1 (Left), Channel 2 (Right), and Channel 3 (Center)
Bass and Treble 2: Channel 4 (Subwoofer)
5. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to
–127 dB. This permits a total volume device control range of +36 dB to –127 dB plus mute. The DAP soft
2
volume and mute update interval is I C programmable. The update is performed at a fixed rate regardless
of the sample rate.
6. Programmable loudness compensation that is controlled via the combination of the master and individual
volume settings.
7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values are provided
used as input parameters using the maximum RMS (master volume x individual channel volume).
8. 4x2 output mixer (channels 1 and 2). Each output can be any ratio of any two signal processed channels.
9. 4x3 output mixer (channels 3 and 4). Each output can be any ratio of any three signal processed channels.
10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate
dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be
2
automatically selected for one or more data sample rates or can be manually selected under I C program
control. This feature enables coefficients for different sample rates to be stored in the TAS5504 and then
select when needed.
9
SLES123 − October 2004
TAS5504
Introduction
Table 1−2. TAS5504 Audio Processing Feature Sets
176.4 AND 192 kHz THREE CHANNEL
FEATURE
32 − 96 kHz FOUR CHANNEL FEATURE SET
FEATURE SET
Signal processing channels
Pass through channels
Master volume
4
N/A
3
1
One for four channels
One for three channels
Individual channel volume
controls
4
3
Bass and treble tone controls
Two bass and treble tone controls with 18-dB range,
programmable corner frequencies, and 2nd order slopes
Two bass and treble tone controls with
18-dB range, programmable corner
frequencies, and 2nd order slopes
L, R, and C (Ch 1, Ch 2, and Ch 3)
Sub (Ch 4)
L and R (Ch 1 and Ch 2)
Sub (Ch 4)
Biquads
28
21
Dynamic range compressors
Input output mapping/mixing
One for three satellites and one for sub
One for two satellites and one for sub
Each of the four signal processing channels input can be
any ratio of the eight input channels.
Each of the three signal processing channels
or the one pass though channels inputs can
be any ratio of the eight input channels.
Each of the four outputs can be any ratio of any two
processed channels.
Each of the four outputs can be any ratio of
any of the three processed or one bypass
channels.
DC blocking filters
(implemented in the PWM
Section)
Four channels
Digital de-emphasis
(implemented in the PWM
Section)
Four channels for 32 kHz, 44.1 kHz, and 48 kHz
Four channels
N/A
Loudness
Three channels
Number of coefficient sets
stored
Three additional coefficient sets can be stored in memory
1.4 TAS5504 DAP Architecture
1.4.1 TAS5504 DAP Architecture Diagrams
Figure 1−2 shows the TAS5504 DAP architecture for Fs = 96 kHz. Note the TAS5504 bass management
2
architecture shown in channels 1, 2, 3, and 4. Note that the I C registers are shown to help the designer
configure the TAS5504.
Figure 1−3 shows the TAS5504 architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels 1,
2, and 4 contain all the features. Channel 3 is pass-through except for master volume control.
Figure 1−4 shows TAS5504 detailed channel processing. The output mixer is 4X2 for channels 1−2 and 4X3
for channels 3 and 4.
10
TAS5504
SLES123 − October 2004
Introduction
Default Input is BOLD
Master Vol
(0xD9)
Max Vol
A
SDIN1−L(L)
B
SDIN1−R (R)
Loud−
ness
(0x91−
0x95)
7 DAP1 Bass &
BQ Treble 1
(0x51− (0xDA−
0x57) 0xDD)
OP Mixer 1
(I2C 0xAA)
4X2 Output
Mixer
C
IP Mixer 1
(I2C 0x41)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
DAP1
Volume
(0xD1)
DRC1
(0x96−
0x9C)
D
L to
PWM1
E
F
G
H
Master Vol
(0xD9)
Max Vol
SDIN1−L(L)
A
B
SDIN1−R(R)
Loud−
ness
(0x91−
0x95)
7 DAP2 Bass &
BQ Treble 1
(0x58− (0xDA−
0x5E) 0xDD)
OP Mixer 2
(I2C 0xAB)
4X2 Output
Mixer
C
IP Mixer 2
(I2C 0x42)
SDIN2−L (LS)
DAP2
Volume
(0xD2)
DRC1
(0x96−
0x9C)
D
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
R to
PWM2
E
F
G
H
SDIN4−R (LFE)
Coeff = 0 (lin)
(I2C 0x4E)
Coeff = 0 (lin)
(I2C 0x4B)
Master Vol
(0xD9)
Max Vol
Coeff = 1 (lin)
(I2C 0x4D)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
A
B
Loud−
ness
(0x91−
0x95)
2 DAP3
BQ
(0x7B−
0x7C)
5 DAP3 Bass &
BQ Treble 1
(0x7D− (0xDA−
OP Mixer 3
(I2C 0xB0)
4X2 Output
Mixer
C
DAP3
Volume
(0xD7)
DRC1
(0x96−
0x9C)
IP Mixer 3
(I2C 0x47)
C to
PWM3
D
E
F
0x81)
0xDD)
G
H
SDIN4−L(C)
SDIN4−R (LFE)
Coeff = 0 (lin)
(I2C 0x4C)
Coeff = 0 (lin)
(I2C 0x49)
Coeff = 0 (lin)
(I2C 0x4A)
Master Vol
(0xD9)
Max Vol
(I2C 0x50)
Coeff = 1 (lin)
SDIN1−L(L)
A
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
B
2 DAP4
BQ
(0x82−
0x83)
Loud−
ness
(0x91−
0x95)
5 DAP4 Bass &
BQ Treble 4
(0x84− (0xDA−
OP Mixer 4
(I2C 0xB1)
4X2 Output
Mixer
C
IP Mixer 4
(I2C 0x48)
DAP4
Volume
(0xD8)
DRC2
(0x9D−
0xA1)
D
Sub to
PWM4
E
F
0x88)
0xDD)
G
H
SDIN4−R(LFE)
Coeff = 0 (lin)
(I2C 0x4F)
2
Figure 1−2. TAS5504 DAP Architecture With I C Registers (Fs ≤ 96 kHz)
Master Vol
Max Vol
(0xD9)
A
SDIN1−Lt (L)
B
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
Loud−
ness
(0x91−
0x95)
7 DAP1
BQ
(0x51−
0x57)
Bass &
Treble 1
(0xDA−
0xDD)
OP Mixer 1
(I2C 0xAA)
4X2 Output
Mixer
C
IP Mixer 1
(I2C 0x41)
DAP1
Volume
(0xD1)
DRC1
(0x96−
0x9C)
D
L to
PWM1
E
F
G
H
SDIN4−Rt (LFE)
Master Vol
(0xD9)
Max Vol
SDIN1−Lt (L)
A
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
B
Loud−
ness
(0x91−
7 DAP2
BQ
(0x58−
0x5E)
Bass &
Treble 1
(0xDA−
0xDD)
OP Mixer 2
(I2C 0xAB)
4X2 Output
Mixer
C
IP Mixer 2
(I2C 0x42)
DAP2
Volume
(0xD2)
DRC1
(0x96−
0x9C)
D
R to
PWM2
E
F
0x95)
G
H
SDIN4−Rt (LFE)
Master Vol
(0xD9)
SDIN1−Lt (L)
A
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
SDIN4−Rt (LFE)
B
OP Mixer 3
(I2C 0xB0)
4X3 Output
Mixer
IP Mixer 3
(I2C 0x47)
C
C to
PWM3
D
E
F
G
H
Master Vol
(0xD9)
Max Vol
A
SDIN1−Lt (L)
B
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
Loud−
ness
(0x91−
0x95)
7 DAP4 Bass &
BQ Treble 4
(0x82− (0xDA−
0x88) 0xDD)
OP Mixer 4
(I2C 0xB1)
4X3 Output
Mixer
C
IP Mixer 4
(I2C 0x48)
DAP4
Volume
(0xD8)
DRC2
(0x9D−
0xA1)
D
Sub to
PWM4
E
F
G
H
SDIN4−Rt (LFE)
2
Figure 1−3. TAS5504 Architecture With I C Registers (Fs = 176.4 kHz or Fs = 192 kHz)
11
SLES123 − October 2004
TAS5504
Introduction
Master
Volume
A_to_ipmix
Left
Channel
Volume
A
B
SDIN1
Max
Volume
Right
DRC
Bypass
Bass and Treble
Bypass
B_to_ipmix
C_to_ipmix
Left
Loudness
C
D
Output
Gain
SDIN2
Input Mixer
Right
Output Mixer Sums
Any Two Channels
D_to_ipmix
E_to_ipmix
Bass and
Treble
7 Biquads
in Series
32-Bit
Trunc
PWM
Proc Output
PWM
Left
E
F
DRC
In-Line
Bass and Treble
In-Line
SDIN3
Post-
Volume
Pre-
Volume
Right
Volume
F_to_ipmix
G_to_ipmix
1 Other
Channel Output
From 7 Available
DRC
Left
G
H
SDIN4
Right
H_to_ipmix
Figure 1−4. TAS5504 Detailed Channel Processing
1.4.2 I2C Coefficient Number Formats
The architecture of the TAS5504 is contained in ROM resources within the TAS5504 and cannot be altered.
2
However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I C bus interface,
provide a user with the flexibility to set the TAS5504 to a configuration that achieves the system level goals.
The firmware is executed in a 48-bit signed fixed-point arithmetic machine. The most significant bit of the 48-bit
data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying
a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output product is then truncated
to a signed 48-bit number. Level offset operations are implemented by adding a 48-bit signed offset coefficient
to a 48-bit signed data value. In most cases, if the addition results in overflowing the 48-bit signed number
format, saturation logic is used. This means that if the summation results in a positive number that is greater
than 0x7FFF_FFFF_FFFF (the spaces are used to ease the reading of the hexadecimal number), the number
is set to 0x7FFF_FFFF_FFFF. If the summation results in a negative number that is less than
0x8000_0000_0000 0000, the number is set to 0x8000_0000_0000 0000.
1.4.2.1 28-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in the Figure 1−5.
−23
2
Bit
−4
2
Bit
Bit
−1
2
0
2 Bit
3
2 Bit
Sign Bit
S_xxxx.xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−5. 5.23 Format
12
TAS5504
SLES123 − October 2004
Introduction
The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 1−6. If
the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 1−6 applied to obtain the
magnitude of the negative number.
3
2
0
−1
−4
−23
2 Bit
2 Bit
2 Bit
2
Bit
2
Bit
2
Bit
3
2
0
−1
−4
−23
(1 or 0) x 2 + (1 or 0) x 2 + … + (1 or 0) x 2 + (1 or 0) x 2 + … + (1 or 0) x 2 + … + (1 or 0) x 2
Figure 1−6. Conversion Weighting Factors—5.23 Format to Floating Point
2
Gain coefficients, entered via the I C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 1−7.
Fraction
Digit 6
Sign
Bit
Integer
Digit 1
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
0
u
u
u
u
S
x
x
x
x.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
2
Figure 1−7. Alignment of 5.23 Coefficient in 32-Bit I C Word
As Figure 1−7 shows, the hex value of the integer part of the gain coefficient cannot be concatenated with the
2
hex value of the fractional part of the gain coefficient to form the 32-bit I C coefficient. The reason is that the
28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex
digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower
3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the
zero-valued most significant hex digit).
1.4.2.2 48-Bit 25.23 Number Format
All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers
formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23 bits to the right
of the decimal point. This is shown in Figure 1−8.
13
SLES123 − October 2004
TAS5504
Introduction
−23
2
Bit
Bit
Bit
−10
2
−1
2
0
2 Bit
16
2
Bit
22
23
2
2
Bit
Bit
Sign Bit
S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−8. 25.23 Format
Figure 1−9 shows the derivation of the decimal value of a 48-bit 25.23 format number.
23
22
0
−1
−23
2
Bit
2
Bit
2 Bit
2
Bit
2
Bit
23
22
0
−1
−23
(1 or 0) x 2 + (1 or 0) x 2 + … + (1 or 0) x 2 + (1 or 0) x 2 + … + (1 or 0) x 2
2
Figure 1−9. Alignment of 5.23 Coefficient in 32-Bit I C Word
2
Two 32-bit words must be sent over the I C bus to download a level or threshold coefficient into the TAS5504.
2
The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I C word is shown in
Figure 1−10.
14
TAS5504
SLES123 − October 2004
Introduction
Integer
Sign
Bit
Digit 4
(Bits 2 − 2 )
3
1
Integer
Digit 1
Integer
Digit 2
Integer
Digit 3
Word 1
(Most
Significant
Word)
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
S
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 16
Coefficient
Digit 15
Coefficient
Digit 14
Coefficient
Digit 13
Coefficient
Digit 12
Coefficient
Digit 11
Coefficient
Digit 10
Coefficient
Digit 9
Integer
Fraction
Digit 6
Digit 4
0
(Bit 2 )
Integer
Digit 5
Integer
Digit 6
Fraction
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
0
Word 2
(Least
Significant
Word)
x
x
x
x
x
x
x
x
x.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
2
Figure 1−10. Alignment of 25.23 Coefficient in Two 32-Bit I C Words
1.4.2.3 TAS5504 Audio Processing
The TAS5504 digital audio processing is designed such that noise produced by filter operations is maintained
below the smallest signal amplitude of interest, as shown in Figure 1−11. The TAS5504 achieves this by
increasing the precision of the signal representation substantially above the number of bits that are absolutely
necessary to represent the input signal.
Ideal Input
Possible Outputs
Desired Output
Values retained by
overflow bits
Maximum Signal
Amplitude
Overflow
Filter
Operation
Reduced
SNR signal
output
Signal bits
output
Signal bits
input
Noise Floor with no
additional precision
Noise Floor as a
result of additional
precision
Figure 1−11. TAS5504 Digital Audio Processing
15
SLES123 − October 2004
TAS5504
Introduction
Similarly, the TAS5504 carries additional precision in the form of overflow bits to permit the value of
intermediate calculations to exceed the input precision without clipping. The TAS5504 advanced digital audio
processor achieves both of these important performance capabilities by using a high performance digital audio
processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator.
1.5 Input Crossbar Mixer
The TAS5504 has a full 8x4 input crossbar mixer. This mixer permits each signal processing channel input
to be any ratio of any of the eight input channels. The control parameters for the input crossbar mixer are
2
programmable via the I C interface. See the Input Mixer Register (0x41−0x48, channels 1−8) section.
Gain Coefficient
28
Input 1
48
Gain Coefficient
48
48
28
Input 2
SUM
48
Gain Coefficient
28
48
Input 8
48
Figure 1−12. Input Crossbar Mixer
1.6 Biquad Filters
For 32-kHz to 96-kHz data, the TAS5504 provides 28 biquads across the four channels (seven per channel)
For 176.4-kHz and 192-kHz data, the TAS5504 has 21 biquads across the three channels (seven per
channel). All of the biquad filters are second order direct form I structure.
The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the
biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number)
and a signed 28-bit coefficient (5.23 format number). The 76-bit ALU in the TAS5504 allows the 76-bit
resolution to be retained when summing the mixer outputs (filter products).
2
The five 28-bit coefficients for the each of the 28 biquads are programmable via the I C interface. See
Table 1−3.
16
TAS5504
SLES123 − October 2004
Introduction
b
0
28
28
28
48
48
48
76
48
76
76
76
Magnitude
Truncation
∑
X
a
b
Z−1
Z−1
1
1
28
28
76
48
48
X
X
b
a
Z−1
Z−1
2
2
76
X
X
Figure 1−13. Biquad Filter Structure
2
All five coefficients for one biquad filter structure are written to one I C register containing 20 bytes (or five
32-bit words). The structure is the same for all biquads in the TAS5504. Registers 0x51 – 0x88 show all the
biquads in the TAS5504. Note that u(31:28) bits are unused and default to 0x0.
Table 1−3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
INITIALIZATION GAIN COEFFICIENT VALUE
DESCRIPTION
b Coefficient
REGISTER FIELD CONTENTS
DECIMAL
1.0
HEX
u(31:28), b0(27:24), b0(23:16), b0(15:8), b0(7:0)
u(31:28), b1(27:24), b1(23:16), b1(15:8), b1(7:0)
u(31:28), b2(27:24), b2(23:16), b2(15:8), b2(7:0)
u(31:28), a1(27:24), a1(23:16), a1(15:8), a1(7:0)
u(31:28), a2(27:24), a2(23:16), a2(15:8), a2(7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
o
b Coefficient
1
0.0
b Coefficient
2
0.0
a Coefficient
1
0.0
a Coefficient
2
0.0
1.7 Bass and Treble Controls
From 32-kHz to 96-kHz data, the TAS5504 has four Bass and Treble tone controls. Each control has a 18-dB
control range with selectable corner frequencies and 2nd order slopes. These controls operate four channel
groups:
•
•
L, R & C (Channels 1, 2, and 3)
Sub (Channel 4)
For 176.4 kHz and 192 kHz data, the TAS5504 has two Bass and Treble tone controls. Each control has a
2
18-dB I C control range with selectable corner frequencies and 2nd order slopes. These controls operate
two channel groups:
•
•
L & R
Sub
The bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment.
17
SLES123 − October 2004
TAS5504
Introduction
Table 1−4. Bass and Treble Filter Selections
3-dB CORNER FREQUENCIES
FILTER
SET 1
FILTER
SET 1
FILTER
SET 2
FILTER
SET 2
FILTER
SET 3
FILTER
SET 3
FILTER
SET 4
FILTER
SET 4
FILTER
SET 5
FILTER
SET 5
FS
(kHz)
BASS
42
TREBLE
917
BASS
83
TREBLE
1833
BASS
125
148
172
188
345
375
689
750
TREBLE
3000
BASS
146
173
201
219
402
438
804
875
TREBLE
3667
BASS
167
TREBLE
4333
32
38
49
1088
1263
1375
2527
2750
5053
5500
99
2177
3562
4354
198
5146
44.1
48
57
115
125
230
250
459
500
2527
4134
5053
230
5972
63
2750
4500
5500
250
6500
88.2
96
115
125
230
250
5053
8269
10106
11000
20213
22000
459
11944
13000
23888
26000
5500
9000
500
176.4
192
10106
11000
16538
18000
919
1000
2
The I C registers that control Bass and Treble are:
•
•
•
•
•
•
Bass and Treble By-Pass Register (0x89 – 0x90, channels 1−8)
Bass and Treble Slew Rates (0xD0)
Bass Filter Sets 1−5 (0xDA)
Bass Filter Index (0xDB)
Treble Filter Sets 1−5 (0xDC)
Treble Filter Index (0xDD)
1.8 Volume, Auto Mute, and Mute
The TAS5504 provides individual channel and master volume controls. Each control provides an adjustment
range of +18.0618 dB to –100 dB in 0.25 dB increments. This permits a total volume device control range of
+36 dB to –100 dB plus mute.
2
The TAS5504 has a master soft mute control that can be enabled by a terminal or I C command. The device
2
also has individual channel soft mute controls that can are enabled via I C.
The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft
2
gain linear update with an I C programmable linear step size at a fixed temporal rate. The linear soft gain step
size can be varied from 0.5 to 0.003906.
Table 1−5. Linear Gain Step Size
STEP SIZE (GAIN)
0.5
10.67
1.33
0.17
0.25
21.33
2.67
0.125
42.67
5.33
0.0625
85.34
10.67
1.33
0.03125
170.67
21.33
0.015625 0.007813 0.003906
Time to go from 36.124 db to −127 dB in ms
Time to go from 18.062 db to −127 dB in ms
Time to go from 0 db to −127 dB in ms
341.35
42.67
5.33
682.70
85.33
10.67
1365.4
170.67
21.33
0.33
0.67
2.67
18
TAS5504
SLES123 − October 2004
Introduction
1.8.1 Auto Mute and Mute
2
The TAS5504 has individual channel automute controls that are enabled via the I C interface. There are two
separate detectors used to trigger the automute:
•
Input Auto Mute: All channels are muted when all 8 inputs to the TAS5504 are less in magnitude than the
input threshold value for a programmable amount of time.
•
Output Auto Mute: A single channel is muted when the output of the DAP section is less in magnitude than
the input threshold value for a programmable amount of time.
The detection period and thresholds for these two detectors are the same.
2
This time interval is selectable via I C to be from 1 ms. to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10,
20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default
value is mask programmable.
The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable
2
via I C. The range of the input threshold adjustment is from below the LSB (bit position 0) to below bit position
12 in a 24 bit input data word (bit positions 8 to 20 in the DSPE). This provides an input threshold that can be
adjusted for 12 to 24 bits of data. The default value is mask programmable.
DVD Data Range
CD Data Range
24-Bit Input
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
9
0
8
32-Bit in DSPE
Representation
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
7
6
5
4
3
2
1
0
Threshold Range
Figure 1−14. Auto Mute Threshold
The auto mute state is exited when the TAS5504 receives one sample that is greater that the output threshold.
The output threshold can be one of two values:
•
•
Equal to the input threshold
6 dB (one bit position) greater than the input threshold
2
The value for the output threshold is selectable via I C. The default value is mask programmable.
The system latency enables the data value that is above the threshold to be preserved and output.
2
A mute command initiated by automute, master mute, individual I C mute, the AM interference mute
sequence, or the bank switch mute sequence overrides an unmute command or a volume command. While
a mute command is activated, the commanded channels transition to the mute state. When a channel is
unmuted, it goes to the last commanded volume setting that has been received for that channel.
1.9 Loudness Compensation
The loudness compensation function compensates for the Fletcher-Munson loudness curves. The TAS5504
loudness implementation tracks the volume control setting to provide spectral compensation for weak low or
high frequency response at low volume levels. For the volume tracking function both linear and log control laws
can be implemented. Any biquad filter response can be used to provide the desired loudness curve. The
2
control parameters for the loudness control are programmable via the I C interface.
19
SLES123 − October 2004
TAS5504
Introduction
The TAS5504 has a single set of loudness controls for the four channels. The loudness control input uses the
Maximum individual master volume (V) to control the loudness that is applied to all channels. In 192-kHz and
176.4-kHz modes, the loudness function is active only for channels 1, 2, and 4.
V
Audio In
Audio Out
x
+
Loudness
Biquad
H(Z)
x
x
Loudness Function = f (V)
V
Figure 1−15. Loudness Compensation Functional Block Diagram
[(Log V) x LG + LO]
Loudness Function = f (V) = G x [2
Loudness Function = f (V) = G x [V
] + O
or alternatively,
LG
LO
x 2 ] + O
For example, for the default values LG = −0.5, LO = 0.0, G = 1.0, and O = 0.0 then:
Loudness Function = 1 / SQRT (V) which is the recommended transfer function for loudness. So,
Audio Out = (Audio In) x V + H (Z) x SQRT (V). Other transfer functions are possible.
Table 1−6. Default Loudness Compensation Parameters
2
I C
DEFAULT
LOUDNESS
TERM
DATA
FORMAT
SUB-ADD
RESS
DESCRIPTION
USAGE
HEX
FLOAT
V
Max volume
Gains audio
5.23
5.23
5.23
NA
NA
NA
NA
0.0
Log V
H (Z)
Log (max volume)
Loudness function
00000000
2
Loudness biquad
Controls shape of
Loudness curves
0x95
b0 = 0000D513
b1 = 00000000
b2 = 0FFF2AED
a1 = 00FE5045
a2 = 0F81AA27
b0 = 0.006503
b1 = 0
b2 = −0.006503
a1 = 1.986825
a2 = −0.986995
LG
LO
G
Gain (log space)
Offset (log space)
Gain
Loudness function
Loudness function
5.23
25.23
5.23
0x91
0x92
0x93
FFC00000
00000000
00000000
−0.5
0
Switch to enable
Loudness (ON = 1,
OFF = 0)
0
O
Offset
Provides offset
25.23
0x94
00000000
0
20
TAS5504
SLES123 − October 2004
Introduction
1.9.1 Loudness Example
Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low frequency attenuation near
60 Hz. The TAS5504 provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz,
and EQ bandwidth = 60 Hz.
Solution: Using Texas Instruments ALE TAS5504 DSP tool, Matlab, or other signal-processing tool, develop
a loudness function with following parameters:
Table 1−7. Loudness Function Parameters
2
EXAMPLE VALUES
LOUDNESS
TERM
DATA
FORMAT
I C
DESCRIPTION
USAGE
SUBADDRESS
HEX
FLOAT
H (Z)
Loudness Biquad
Controls shape of
loudness curves
5.23
0x95
b0 = 00008ACE
b1 = 00000000
b2 = FFFF7532
a1 = FF011951
a2 = 007EE914
b0 = 0.004236
b1 = 0
b2 = −0.004236
a1 = −1.991415
a2 = 0.991488
LG
LO
G
Loudness Gain
Loudness Offset
Gain
Loudness function
Loudness function
5.23
25.23
5.23
0x91
0x92
0x93
FFC00000
00000000
00800000
−0.5
0
Switch to Enable
Loudness (ON = 1,
OFF = 0)
1
O
Offset
Offset
25.23
0x94
00000000
0
See Figure 1−16 for the resulting loudness function at different gains.
Figure 1−16. Loudness Example Plots
21
SLES123 − October 2004
TAS5504
Introduction
1.10 Dynamic Range Control (DRC)
The DRC provides both compression and expansion capabilities over three separate and definable regions
of audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each
of the three regions a distinct compression or expansion transfer function can be established and the slope
of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two
boundaries defining the three regions can also be set by programmable offset coefficients. The DRC
implements the composite transfer function by computing a 5.23 format gain coefficient from each sample
output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input is
the audio data stream. The mixer output is the DRC-adjusted audio data.
There are two distinct DRC blocks in the TAS5504. DRC1 services channels 1−3. This DRC computes rms
estimates of the audio data streams on all channels that it controls. The estimates are then compared on a
sample-by-sample basis and the larger of the estimates is used to compute the compression/expansion gain
coefficient. The gain coefficient is then applied to appropriate channels audio stream. DRC2 services only
channel 4. This DRC also computes an rms estimate of the signal level on channel 4 and this estimate is used
to compute the compression/expansion gain coefficient applied to the channel 4 audio stream.
All of the TAS5504 default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 1−8
shows the recommended time constants and their HEX values. If the user wants to implement other DRC
functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available
from Texas Instruments. The ALE tool allows the user to select the DRC transfer function graphically. It will
then output the TAS5504 hex coefficients for download to the TAS5504.
Table 1−8. DRC Recommended Changes From TAS5504 Defaults
2
I C
RECOMMENDED TIME
CONSTANT (MS)
RECOMMENDED
HEX VALUE
REGISTER FIELDS
DEFAULT HEX
SUBADDRESS
0x98
0x9C
DRC1 energy
DRC1 (1 – energy)
DRC1 attack
5
5
2
5
5
2
0000883F
007F77C0
0000883F
007F77C0
0001538F
007EAC70
0000883F
007F77C0
0000883F
007F77C0
0001538F
007EAC70
0000883F
007F77C0
0000883F
007F77C0
000000AE
007FFF51
0000883F
007F77C0
0000883F
007F77C0
000000AE
007FFF51
DRC1 (1 – attack)
DRC1 decay
DRC1 (1 – decay)
DRC2 energy
0x9D
0xA1
DRC2 (1 – energy)
DRC2 attack
DRC2 (1 – attack)
DRC2 decay
DRC2 (1 – decay)
Recommended DRC set-up flow if the defaults are used:
•
After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See
Table 1−8.
•
Enable either the pre-volume or post-volume DRC
Recommended DRC set-up flow if the DRC design uses values different from the defaults:
•
•
After power up, load all DRC coefficients per the DRC design.
Enable either the pre-volume or post-volume DRC
Figure 1−17 shows the positioning of the DRC block in the TAS5504 processing flow. As seen, the DRC input
can come from either before or after soft volume control and loudness processing.
22
TAS5504
SLES123 − October 2004
Introduction
Master
Volume
Channel
Volume
Max
Volume
DRC
By-Pass
Bass & Treble
By-Pass
Loudness
To Output
Mixer
From Input Mixer
7 Biquads
in Series
Bass and
Treble
DRC
In-Line
Bass & Treble
In-Line
Pre-
Volume
Post-
Volume
DRC
Figure 1−17. DRC Positioning in TAS5504 Processing Flow
Figure 1−18 illustrates a typical DRC transfer function.
Region
0
Region
1
Region
2
k2
k1
1:1 Transfer Function
Implemented Transfer Fucntion
k0
O2
O1
T1
T2
DRC Input Level
Figure 1−18. Dynamic Range Compression (DRC) Transfer Function Structure
The three regions shown in Figure 1−18 are defined by three sets of programmable coefficients:
•
•
•
Thresholds T1 and T2—define region boundaries.
Offsets O1 and O2—define the DRC gain coefficient settings at thresholds T1 and T2 respectively.
Slopes k0, k1, and k2—define whether compression or expansion is to be performed within a given region.
The magnitudes of the slopes define the degree of compression or expansion to be performed.
The three sets of parameters are all defined in logarithmic space and adhere to the following rules:
•
The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value then
have negative values in logarithmic (dB) space.
•
The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word format
used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial data
received at the serial audio receive port by adding 8 bits of headroom above the 32-bit word and 8 bits
of computational precision below the 32-bit word. If the audio processing steps between the SAP input
and the DRC input result in no accumulative boost or cut, the DRC would operate on the 8 bits of headroom
and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value) audio sample
(0x7FFFFFFF) is seen at the DRC input as a –48-dB sample (8 bits x −6.02 dB/bit = −48 dB).
23
SLES123 − October 2004
TAS5504
Introduction
•
Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to the
rms value of the data into the DRC. Zero valued threshold settings reference the maximum valued rms
input into the DRC and negative valued thresholds reference all other rms input levels. Positive valued
thresholds have no physical meaning and are not allowed. In addition, zero valued threshold settings are
not allowed.
Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of the
DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space. This
means that the threshold settings must be programmed as 48-bit (25.23 format) numbers.
CAUTION: Zero valued and positive valued threshold settings are not allowed and
cause unpredictable behavior if used.
•
•
Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain
coefficient at the threshold points T1 and T2 respectively. Positive offsets are defined as cuts, and thus
boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23 format)
numbers.
Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given region,
and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit (5.23 format)
numbers.
1.10.1 DRC Implementation
The three elements comprising the DRC: (1) an rms estimator, (2) a compression/expansion coefficient
computation engine, and (3) an attack/decay controller. DRC1 applies to channels 1 −3 and DRC2 applies
2
2
only to channel 4. DRC1 uses I C register 0x98 − 0x9C and DRC2 uses I C registers 0x9D − 0xA1.
•
RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into
the DRC. For DRC1 (Ch 1−3), the individual channel estimates are computed. The outputs of the
estimators are then compared, sample-by-sample, and the larger valued sample is forwarded to the
compression/expansion coefficient computation engine.
2
Two programmable parameters (I C 0x98), E and (1 – E), set the effective time window over which the rms
estimate is made. For the DRC1 block, the programmable parameters apply to all rms estimators. The
time window over which the rms estimation is computed can be determined by:
* 1
ȏn(1 * E)
t
+
window
F
S
•
•
Compression/expansion coefficient computation—This DRC element converts the output of the rms
estimator to a logarithmic number, determines the region that the input resides, and then computes and
outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters—T1,
T2, O1, O2, k0, k1, and k2—define the three compression/expansion regions implemented by this
element.
Attack/decay control—This DRC element controls the transition time of changes in the coefficient
computed in the compression/expansion coefficient computation element. Four programmable
parameters define the operation of this element. Parameters D and 1 − D set the decay or release time
constant to be used for volume boost (expansion). Parameters A and 1 − A set the attack time constant
to be used for volume cuts. The transition time constants can be determined by:
* 1
ȏn(1 * A)
* 1
ȏn(1 * D)
t +
t +
a
d
F
F
S
S
Figure 1−19 shows how the TAS5504 attack and decay are defined. Note that this is opposite of some
definitions of attack and decay.
24
TAS5504
SLES123 − October 2004
Introduction
t
+ * 1ńFs ȏ (1 * D)
t
+ * 1ńFs ȏ (1 * A)
d
N
a
N
Decay
Attack
Time
Figure 1−19. TAS5504 Attack and Decay Definition
1.10.2 Compression/Expansion Coefficient Computation Engine Parameters
There are seven programmable parameters assigned to each DRC block: two threshold parameters - T1 and
T2, two offset parameters - O1 and O2, and three slope parameters - k0, k1, and k2. The threshold parameters
establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by establishing
known gain settings at the threshold levels, and the slope parameters define whether a given region is a
compression or an expansion region.
The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers. These
mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the audio data in
the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input and the DRC. The
selection of threshold values must take the gain (attenuation) of these mixers into account. The DRC
implementation examples that follow illustrate the effect these mixers have on establishing the threshold
settings.
T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes the
boundary between the mid-volume region and the low-volume region. Both thresholds are set in logarithmic
space, and which region is active for any given rms estimator output sample is determined by the logarithmic
value of the sample.
Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost (> 0 dB)
or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If O2 = 0 dB, the
value of the derived gain coefficient is 1.0 (0x00, 80, 00, 00 in 5.23 format). k2 is the slope of the DRC transfer
function for rms input levels above T2 and k1 is the slope of the DRC transfer function for rms input levels below
T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that there cannot be a discontinuity
in the transfer function at T2. The user can, however, set the DRC parameters to realize a discontinuity in the
transfer function at the boundary defined by T1. If no discontinuity is desired at T1, the value for the offset term
O1 must obey the following equation.
25
SLES123 − October 2004
TAS5504
Introduction
| | | | | |
+ T1 * T2 k1 ) O2 For ( T1 w T2 )
O1
No Discontinuity
T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the
user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is realized.
Going down in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this input
level, the offset of the transfer function curve from the 1:1 transfer curve does not equal O1, there is a
discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no
discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at the input level
T1 is offset from the 1:1 transfer curve by the value O1. The examples that follow illustrate both continuous
and discontinuous transfer curves at T1.
Going down in volume from T1, starting at the offset level O1, the slope k0 defines the compression/expansion
activity in the lower region of the DRC transfer curve.
1.10.2.1 Threshold Parameter Computation
For thresholds,
T
= −6.0206T = −6.0206T
INPUT SUB_ADDRESS_ENTRY
dB
If, for example, it is desired to set T1 = -64 dB, then the subaddressaddress entry required to set T1 to -64 dB
is:
*64
*6.0206
T1
+
+ 10.63
SUB_ADDRESS_ENTRY
T1 is entered as a 48-bit number in 25.23 format. Therefore:
T1 = 10.63 = 0_1010.1010_0001_0100_0111_1010_111
= 0x00000550A3D7 in 25.23 format
1.10.2.2 Offset Parameter Computation
The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An
equivalent statement is that offsets represent the departure of the actual transfer function from a 1:1 transfer
at the threshold point. Offsets are 25.23 formatted 48-bit logarithmic numbers. They are computed by the
following equation.
O
) 24.0824 dB
DESIRED
6.0206
O
+
INPUT
Gains or boosts are represented as negative numbers; cuts or attenuation are represented as positive
2
numbers. For example, to achieve a boost of 21 dB at threshold T1, the I C coefficient value entered for O1
must be:
–21 dB ) 24.0824 dB
O1
+
+ 0.51197555
INPUT
6.0206
+ 0.1000_0011_0001_1101_0100
+ 0x00000041886A in 25.23 format
More examples of offset computations are included in the following examples.
26
TAS5504
SLES123 − October 2004
Introduction
1.10.2.3 Slope Parameter Computation
In developing the equations used to determine the subaddress of the input value required to realize a given
compression or expansion within a given region of the DRC, the following convention is adopted.
DRC Transfer = Input Increase : Output Increase
If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the DRC,
a 1:n expansion is being performed. If the DRC realizes a 1 dB increase in output level for every n dB increase
in the rms value of the audio into the DRC, a n:1 compression is being performed.
For 1:n expansion, the slope k can be found by:
k = n − 1
1
For n:1 compression, the slope k can be found by: k + –1
n
In both expansion (1:n) and compression (n:1), n is implied to be greater than 1. Thus, for expansion:
1
k = n −1 means k > 0 for n > 1. Likewise, for compression, k + –1 means −1 < k < 0 for n > 1. Thus, it appears
n
that k must always lie in the range k > −1.
The DRC imposes no such restriction and k can be programmed to values as negative as −15.999. To
determine what results when such values of k are entered, it is first helpful to note that the compression and
expansion equations for k are actually the same equation. For example, a 1:2 expansion is also a 0.5:1
compression.
1
0.5
0.5 Compression å k +
–1 + 1
1 : 2 Expansion å k + 2–1 + 1
As can be seen, the same value for k is obtained either way. The ability to choose values of k less than −1 allows
the DRC to implement negative slope transfer curves within a given region. Negative slope transfer curves
are usually not associated with compression and expansion operations, but the definition of these operations
can be expanded to include negative slope transfer functions. For example, if k = −4
1
1
3
Compression Equation : k + *4 + *1 å n + – å *0.3333 : 1 compression
n
Expansion Equation : k + *4 + n–1 å n + –3 å 1 : *3 expansion
With k = −4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the DRC.
As the input increases in volume, the output decreases in volume.
1.11 Output Mixer
The TAS5504 provides an 4x2 output mixer for channels 1 and 2. For channels 3 and 4, the TAS5504 provides
an 4x3 output mixer. These mixers allow each output to be any ratio of any two (three) signal processed
2
channels. The control parameters for the output crossbar mixer are programmable via the I C interface.
27
SLES123 − October 2004
TAS5504
Introduction
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
48
48
28
Select
Output
N
1 or 2
Output
48
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
48
48
48
28
Select
Output
N
Output 3 or 4
48
Gain Coefficient
28
Select
Output
N
48
Figure 1−20. Output Mixers
1.12 PWM
The TAS5504 has four channels of high performance digital PWM modulators that are designed to drive
switching output stages (backends) in both single-ended (SE) and H-bridge (bridge tied load) configuration.
The TAS5504 device uses noise-shaping and sophisticated error correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5504 uses an AD1 PWM modulation
th
combined with a 5 order noise shaper to provide a 102-dB SNR from 20 to 20 kHz.
The PWM section accepts 32-bit PCM data from the DAP and outputs four PWM audio output channels.
The TAS5504 PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the
TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone will not
operate while the backend drive channels are operating. The headphone will be enabled via a headphone
2
select terminal or I C command.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled and
disabled.
The PWM section also contains the power supply volume control (PSVC) PWM.
The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
•
Up to 8x over sampling.
−
−
−
8x at F = 44.1 kHz, 48 kHz, 32 kHz, 38 kHz
S
4x at F = 88.2 kHz, 96 kHz
S
2x at F = 176.4 kHz, 192 kHz
S
•
•
5th order noise shaping
102-dB dynamic range 0 – 20 kHz (TAS5504 + TAS5111 system measured at speaker terminals)
28
TAS5504
SLES123 − October 2004
Introduction
•
•
•
THD < 0.01%
Adjustable maximum modulation limit of 93.8% to 99.2%
3.3-V digital signal
1.12.1 DC Blocking (High Pass Enable/ Disable)
Each input channel incorporates a first order digital high-pass filter to block potential dc components. The filter
–3 dB point is approximately 0.89-Hz at 44.1-kHz sampling rate. The high-pass filter can be enabled and
2
disabled via the I C interface.
1.12.2 De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to
support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 1−21 shows a graph of the de-emphasis
filtering characteristics. De-emphasis is set using two bits in the system control register.
0
−10
10.6 (15 µs)
3.18 (50 µs)
Frequency − kHz
Figure 1−21. De-emphasis Filter Characteristics
1.12.3 Power Supply Volume Control (PSVC)
The TAS5504 supports volume control by both conventional digital gain / attenuation and by a combination
of digital and analog gain / attenuation. Varying the H-bridge power supply voltage performs the analog volume
control function. The benefits of using powers supply volume control (PSVC) are reduced idle channel noise,
improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions
2
at reduced power levels. The power supply volume control (PSVC) is enabled via I C. When enabled the
PSCV provides a PWM output that is filtered to provide a reference voltage for the power supply. The power
supply adjustment range can be set for −12.04, −18.06, or −24.08 dB, to accommodate a range of variable
power supply designs.
Figure 1−22 and Figure 1−23 show how power supply and digital gains can be used together.
The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to match
the PSVC volume transfer function.
29
SLES123 − October 2004
TAS5504
Introduction
Power Supply Volume Control
30
20
10
0
−10
−20
−30
Digital Gain
Power Supply Gain
−40
−50
−60
Desired Gain − dB
Figure 1−22. Power Supply and Digital Gains (Log Space)
Power Supply Volume Control
100
10
1
0.1
Digital Gain
Power Supply Gain
0.01
0.001
0.0001
0.00001 0.0001
0.001
0.01
0.1
1
10
100
Desired Gain (Linear)
Figure 1−23. Power Supply and Digital Gains (Linear Space)
1.12.4 AM Interference Avoidance
Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments patented AM
interference avoidance circuit provides a flexible system solution for a wide variety of digital audio
architectures. During AM reception, the TAS5504 adjusts the radiated emissions to provide an emission clear
zone for the tuned AM frequency. The inputs to the TAS5504 for this operation are the tuned AM frequency,
the IF frequency, and the sample rate. The sample rate is automatically detected.
30
TAS5504
SLES123 − October 2004
Introduction
ADC
PCM1802
Analog
Receiver
Audio
DSP
TAS5111
TAS5111
TAS5111
TAS5111
TAS5504
Audio DSP provides the master
and bit clocks
Digital
Receiver
Audio
DSP
TAS5111
TAS5111
TAS5111
TAS5111
TAS5504
The Digital Receiver or the Audio
DSP provides the Master and Bit
clocks
Figure 1−24. Block Diagrams of Typical Systems Requiring TAS5504 Automatic AM Interference
Avoidance Circuit
31
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
2
TAS5504 Controls and Status
2
The TAS5504 provides control and status information from both the I C registers and device pins.
2
This section describes some of these controls and status functions. The I C summary and detailed register
descriptions are contained in sections at the end of this document.
2.1 I2C Status Registers
The TAS5504 has two status registers that provide general device information. These are the General Status
Register 0 (0x01) and the Error Status Register (0x02).
2.1.1 General Status Register (0x01)
•
•
•
Device identification code
Clip indicator – The TAS5504 has a clipping indicator. Writing to the register clears the indicator.
Bank switching is busy
2.1.2 Error Status Register (0x02)
•
No internal errors (the valid signal is high)
•
A clock error has occurred – These are sticky bits that are cleared by writing to the register.
−
−
−
−
LRCLK error – When the number of MCLKs per LRCLK is incorrect
SCLK error – When the number of SCLKS per LRCLK is incorrect
Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
PLL phase-lock error
•
This error status register is normally used for system development only.
2.2 TAS5504 Pin Controls
The TAS5504 provide a number of terminal controls to manage the device operation. These controls are:
•
•
•
•
•
RESET
PDN
BKND_ERR
HP_SEL
MUTE
2.2.1 Reset (RESET)
The TAS5504 is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry
when power is applied.
RESET is an asynchronous control signal that restores the TAS5504 to the hard mute state (M). Master
volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without
an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all
2
I C and serial data bus operations are ignored.
Table 2−1 shows the device output signals while RESET is active.
Table 2−1. Device Outputs During Reset
SIGNAL
Valid
SIGNAL STATE
Low
PWM P-outputs
PWM M-outputs
SDA
Low (M-State)
Low (M-State)
Signal Input (not driven)
33
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading
edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational
state is performed using a quiet start up sequence to minimize noise. This control uses the PWM reset and
unmute sequence to shut down and start up the PWM. A detailed description of these sequences is contained
in the PWM section. If a completely quiet reset or power down sequence is desired, MUTE should be applied
before applying RESET.
The rising edge of the reset pulse begins device initialization before the transition to the operational mode.
During device initialization, all controls are reset to their initial states. Table 2−2 shows the default control
settings following a reset.
Table 2−2. Values Set During Reset
CONTROL
SETTING
Clock register
High pass
Not valid
Disabled
Unmute from clock error
PSVC high Z
Hard unmute
Disabled
Post DAP detection automute
Four Ch PreDAP detection automute
De-emphasis
Enabled
Enabled
De-emphasis disabled
Channel configuration control
Headphone configuration control
Serial data interface format
Individual channel mute
Automute delay
Configured for the default setting
Configured for the default setting
2
I S 24 bit
No channels are muted
5 ms
Automute threshold 1
Automute threshold 2
Modulation limit
< 8 bits
Same as automute threshold 1
Maximum modulation limit of 97.7%
Disengaged for all channels
−32, 0, –16, 16, –24, 8, –8, −24
Enabled
Slew rate limit
Interchannel delay
Shutdown PWM on error
Volume and mute update rate
Treble and bass slew rate
Bank switching
Volume ramp 85 ms
Update every 1.31 ms
Manual bank selection is enabled
All channels use Bank 1
Set to All pass
Auto bank switching map
Biquad coefficients (TAS5504)
Input mixer coefficients
Output mixer coefficients
Input N −> Channel N, no attenuation
Channel N −> Output N, no attenuation
Gain of 0
Subwoofer sum into Ch1 and Ch2
(TAS5504)
Ch1 and Ch2 sum in subwoofer (TAS5504)
Bass and treble bypass
Bass and treble Inline
DRC bypass (TAS5504)
DRC inline (TAS5504)
DRC (TAS5504)
Gain of 0
Gain of 1
Gain of 0
Gain of 1
Gain of 0
DRC disabled, default values
Mute
Master volume
Individual channel volumes
All bass and treble Indexes
Treble filter sets
0 dB
0x12 neutral
Filter Set 3
Filter Set 3
Bass filter sets
34
TAS5504
SLES123 − October 2004
TAS5504 Controls and Status
CONTROL
Loudness (TAS5504)
SETTING
Loudness disabled, default values
AM interference enable
AM interference IF
Disabled
455
AM interference select sequence
Tuned freq and mode
1
0000 , BCD
Enabled
Disabled / 0 dB
Subwoofer PSVC control
PSVC and PSVC range
After the initialization time, the TAS5504 starts the transition to the operational state with the Master volume
set at mute.
Since the TAS5504 has an external crystal time base, following the release of RESET, the TAS5504 sets the
MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state until
2
the master volume is set to a value other than mute via I C.
2.2.2 Power Down (PDN)
The TAS5504 can be placed into the power down mode by holding the PDN terminal low. When power down
mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition
to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power down state. To
initiate the power-up sequence requires MCLK to be operational and the TAS5504 to receive 5 MCLKs prior
to the release of PDN.
As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard
2
mute (M) state. During power down, all I C and serial data bus operations are ignored. Table 2−3 shows the
device output signals while PDN is active.
Table 2−3. Device Outputs During Power Down
SIGNAL
Valid
SIGNAL STATE
Low
PWM P-outputs
PWM M-outputs
SDA
M-state = low
M-state = low
Signal input
M-state = low
PSVC
Following the application of PDN, the TAS5504 does not perform a quiet shutdown to prevent clicks and pops
produced during the application (the leading edge) of this command. The application of PDN immediately
performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the
2
I C register settings.
The crystal time base allows the TAS5504 to determine the CLK rates. Once these rates are determined, the
TAS5504 unmutes the audio.
2.2.3 Backend Error (BKND_ERR)
Backend error is used to provide error management for backend error conditions. Backend error is a level
sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5
MCLK cycles. When BKND_ERR is brought low, the PWM sets all channels into the PWM backend error state.
This state is described in the PWM section. Once the backend error sequence is initiated, a delay of 5 ms is
performed before the system starts the output re−initialization sequence. After the initialization time, the
TAS5504 begins normal operation. Backend error does not affect other PWM modulator operations
35
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
When BKND_ERR is low, the TAS5504 brings the PWM outputs 1−6 to a backend error state, while not
affecting any other internal settings or operations. Table 2−4 shows the device output signal states during
backend error.
Table 2−4. Device Outputs During Backend Error
SIGNAL
Valid
SIGNAL STATE
Low
PWM P-outputs
PWM M-outputs
HPPWM P-outputs
HPPWM M-outputs
SDA
M-State − low
M-State − low
M-State − low
M-State − low
Signal Input (not driven)
2.2.4 Speaker / Headphone Selector (HP_SEL)
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives
the processed data output from DAP and PWM channels 1 and 2.
When low, the headphone output is enabled. In this mode the speaker outputs are disabled. When high, the
speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level results in a state change sequence using soft mute to the hard mute (M) state
for both speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 are defined by the headphone configuration
register. When HP_SEL is high, the channel 1 and 2 configuration registers define the configuration of
channels 1 and 2.
2.2.5 Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS5504 has both a master and individual channel mute commands. A terminal is
2
also provided for the master MUTE. The low active master Mute I C register and the MUTE terminal are
logically Or’ed together. If either is set to low, a mute on all channels is performed. The master mute command
operates on all channels.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master Mute terminal is used to support a variety of other operations in the TAS5504, such as setting the
inter-channel delay, the biquad coefficients, the serial interface format, and the clock rates. A mute command
2
by the master mute terminal, individual I C mute, the AM interference mute sequence, the bank switch mute
sequence, or automute overrides an unmute command or a volume command. While a mute is active, the
commanded channels will be placed in a mute state. When a channel is unmuted, it goes to the last
commanded volume setting that has been received for that channel.
2.3 Device Configuration Controls
The TAS5504 provides a number of system configuration controls that are set at initialization and following
a reset.
•
•
•
•
•
•
Channel Configuration
Headphone Configuration
Audio System Configurations
Recovery from Clock Error
Power Supply Volume Control Enable
Volume and Mute Update Rate
36
TAS5504
SLES123 − October 2004
TAS5504 Controls and Status
•
•
•
•
Modulation Index Limit
Inter-channel Delay
Master Clock and Data Rate Controls
Bank Controls
2.3.1 Channel Configuration Registers
In order for the TAS5504 to have full control of the power stages, registers 0x05, 0x06, 0x0B, and 0x0C must
be programmed to reflect the proper power stage and how each one should be controlled. Channel
configuration registers consist of four registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling during
start up, mute/unmute, shutdown, and error recovery. The TAS5504 must select the sequence that gives the
best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.
This sequence depends on which power stage is present at the TAS5504 output.
Table 2−5. Description of the Channel Configuration Registers (0x05, 0x06, 0x0B, 0x0C)
BIT
DESCRIPTION
D7
Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is
to follow the error recovery sequence or to continue with no interruption.
D6
D5
Determines if the power stage needs the TAS5504 VALID pin to go low to reset the power stage. Some power stages can be reset
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
Determines if the power stage needs the TAS5504 VALID pin to go low to mute the power stage. Some power stages can be muted
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
D4
D3
Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5504 PWM
pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.
The power stage TAS5182 has a special PWM input. To ensure that the TAS5504 has full control in all occasions, the PWM output
must be remapped.
D2
D1
Can be used to handle click and pop for some applications.
This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of
both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0
Not used
Table 2−6 lists the optimal setting for each output stage configuration. Note that the default value is applicable
in all configurations except the TAS5182 SE/BTL configuration.
Table 2−6. Recommended TAS5504 Configurations for Texas Instruments Power Stages
DEVICE
Default
ERROR RECOVERY
RES
CONFIGURATION
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
BTL
BTL
SE
1
1
1
0
0
0
0
0
RES
AUT
RES
AUT
RES
1
1
1
0
0
0
0
0
TAS5111
BTL
SE
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
BTL
SE
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
TAS5112
TAS5182
BTL
SE
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
BTL
SE
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
RES: The output stage requires VALID to go low to recover from a shutdown.
AUT: The power stage can auto recover from a shutdown.
BTL: Bridge tied load configuration
37
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
SE: Single-ended configuration
2.3.2 Headphone Configuration Registers
The headphone configuration controls are identical to the speaker configuration controls. The headphone
configuration control settings are used in place of the speaker configuration control settings for channels 1
and 2 when the headphones are selected. In reality however, there is only one used configuration setting for
headphones and that is the default setting.
2.3.3 Audio System Configurations
The TAS5504 can be configured to comply with various audio systems.
The audio system configuration is set in the General Control Register (0xE0). Bits D31 – D4 must be zero and
D0 is don’t care.
D3
D2
Determines if SUB is to be controlled by PSVC
Enable/Disable power supply volume control
D3−D1 must be configured as the following according to the audio system in the application:
Table 2−7. Audio System Configuration (General Control Register 0xE0)
AUDIO SYSTEM
DEFAULT
D31−D4
D3
0
D2
0
D1
0
D0
X
0
0
0
0
3.1 channels NOT using PSVC
4 channels using PSVC
3.1 channels using PSVC
0
0
1
X
0
1
1
X
1
1
1
X
2.3.4 Recovery from Clock Error
The TAS5504 can be set to either perform a volume ramp up during the recovery sequence of a clock error
or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature
2
is enabled via I C system control register 0x03.
2.3.5 Power Supply Volume Control Enable
2
The power supply volume control (PSVC) can be enabled and disabled via I C register 0xE0. The subwoofer
PWM output can configured to be controlled by the PSVC or digitally attenuated when PSVC is enabled (for
powered subwoofer configurations). Note that PSVC cannot be simultaneously enabled along with unmute
outputs after clock error feature.
2.3.6 Volume and Mute Update Rate
The TAS5504 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute
2
ramp rates are adjustable by programming the I C register 0xD0 for the appropriate number of steps to be
512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
•
•
•
In normal speed, the update rate is 1 step every 4 / Fs seconds.
In double speed, the update is 1 step every 8 / Fs seconds.
In quad speed, the update is 1 step every 16 / Fs seconds.
Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However,
the variance of the total time to go from +18 dB to mute is less than 25%.
38
TAS5504
SLES123 − October 2004
TAS5504 Controls and Status
Table 2−8. Volume Ramp Rates in ms
SAMPLE RATE (kHz)
NUMBER OF STEPS
44.1, 88.2, 176.4
46.44 ms
32, 48, 96, 192
42.67 ms
512
1024
2048
92.88 ms
85.33 ms
185.76 ms
170.67 ms
2.3.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is
50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For
negative signals, the PWM modulations fall below 50% towards 0%.
However, there is a limit to the maximum modulation possible. During the off-time period, the power stage
connected to the TAS5504 output needs to get ready for he next on-time period. The maximum possible
modulation is then set by the power stage requirements. A modulation index of 97.7% is the default setting
of the TAS5504. Default settings can be changed in the Modulation Index Register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
2.3.8 Inter-channel Delay
An 8-bit value can be programmed to each of the four PWM inter-channel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
The default values are shown in Table 2−9.
Table 2−9. Inter-Channel Delay Default Values
2
I C SUB-ADDRESS
CHANNEL
INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)
0x1B
0x1C
0x21
0x22
1
2
3
4
−24
0
−8
+24
2
This delay is generated in the PWM and can be changed at any time through the serial control interface I C
2
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I C sub-address 0x23.
NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I2C serial
interface. Unless otherwise noted, use the default values given in Table 2−9.
2.4 Master Clock and Serial Data Rate Controls
The TAS5504 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right
clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal
allows the TAS5504 to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5504 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5504 accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than 10 MCLK cycles since the last RESET, the TAS5504 performs
a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
39
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
2
•
•
•
MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) − I C parameter
2
Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz − I C parameter
2
AM Mode Enable / Disable − I C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
2
•
•
•
Tuned AM Frequency (for AM interference avoidance) (550 − 1750 kHz) − I C parameter
2
Frequency Set Select (1−4) − I C parameter
2
Sample Rate − I C parameter or auto detected
2.4.1 PLL Operation
The TAS5504 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital
PLL provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal
provides the input reference clock for the digital PLL. The crystal provides a time base to support a number
of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal
time base provides a constant rate for all controls and signal timing.
2
Even if MCLK is not present, the TAS5504 can receive and store I C commands and provide status.
2.5 Bank Controls
The TAS5504 permits the user to specify and assign sample rate dependent parameters for Biquad,
Loudness, DRC, and Tone in one of three banks that can be manually selected or selected automatically
2
based upon the data sample rate. Each bank can be enabled for one or more specific sample rates via I C
bank control register 0x40. Each bank set holds the following values:
•
Coefficients for Seven Biquads (7X5 = 35 coefficients) for Each of the four Channels (Registers 0X51 –
0x88)
•
•
•
•
•
•
•
Coefficients for One Loudness Biquad (Register 0x95)
DRC1 Energy and (1 – Energy) Values (Register 0x98)
DRC1 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0x9C)
DRC2 Energy and (1 – Energy) Values (Register 0x9D)
DRC2 Attack, (1 − Attack), Decay, (1 – Decay) Values (Register 0xA1)
Five Bass Filter-Set Selections (Register 0xDA)
Five Treble Filter-Set Selections (Register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,
Bank 2 and Bank 3 must be programmed on power up since the default values are all zeroes. If bank switching
is used and Bank 2 and Bank 3 are not programmed correctly, then the output of the TAS5504 could be muted
when switching to those banks.
2.5.1 Manual Bank Selection
The three bank selection bits of the bank control register allow the appropriate bank to be manually selected
(000 = Bank 1, 001 = Bank 2, 010 = Bank 3). In the manual mode, when a write occurs to the Biquad, DRC,
or Loudness coefficients, the current selected bank is updated. If audio data is streaming to the TAS5504,
during a manual bank selection, the TAS5504 first performs a mute sequence, then performs the bank switch,
and finally restores the volume using an un-mute sequence.
A mute command initiated by the bank switch mute sequence overrides an un−mute command or a volume
command. While a mute is active, the commanded channels are muted. When a channel is unmated, the
volume level goes to the last commanded volume setting that has been received for that channel.
40
TAS5504
SLES123 − October 2004
TAS5504 Controls and Status
If MCLK or SCLK is stopped, the TAS5504 performs a bank switch operation. If the clocks should start up once
the manual bank switch command has been received, the bank switch operation is performed during the 5-ms
silent start sequence.
2.5.2 Automatic Bank Selection
To enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control
register. Banks are associated with one or more sample rates by writing values into the Bank 1 or Bank 2 data
rate selection registers. The automatic base selection is performed when a frequency change is detected
according to the following scheme:
1. The system scans Bank 1 data rate associations to see if the Bank 1 is assigned for that data rate.
2. If Bank 1 is assigned, then the Bank 1 coefficients will be loaded.
3. If it is not then, the system scans the bank 2 to see if Bank 1 is assigned for that data rate.
4. If Bank 2 is assigned, then the Bank 2 coefficients will be loaded.
5. If it is not then, the system loads the Bank 3 coefficients.
The default is that all frequencies are enabled for Bank 1. This default is expressed as a value of all 1s in the
Bank 1 auto-selection byte and all 0s in the bank 2 auto-section byte.
2.5.2.1 Coefficients Write Operations While Automatic Bank Switch Is Enabled
In automatic mode if a write occurs to the Tone, EQ, DRC, or Loudness coefficients, the bank that is written
to is the current bank.
2.5.3 Bank Set
Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic
switching modes without causing a bank switch to occur. Bank set mode does not alter the current bank
register mapping. It simply enables any bank’s coefficients to be updated while inhibiting any bank switches
from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic
mode this prevents a clock error or data rate change from corrupting a bank coefficient write.
To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank
control register. This enables the Tone, EQ, DRC, and Loudness coefficient values of bank 1, 2, or 3 to be
respectively updated.
Once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired
manual or automatic bank selection mode.
2.5.4 Bank Switch Timeline
2
After a bank switch is initiated (manual or automatic), no I C writes to the TAS5504 should occur before a
minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.
2.5.5 Bank Switching Example 1
Problem: The audio unit containing a TAS5504 needs to handle different audio formats with different sample
rates. Format #1 requires Fs = 32 kHz, Format #2 requires Fs = 44.1 kHz, and Format #3 requires Fs = 48
kHz. The sample-rate dependent parameters in the TAS5504 require different coefficients and data
depending on the sample rate.
Strategy: Use the TAS5504 bank switching feature to allow for managing and switching three banks
associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3).
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
•
Generate bank-related coefficients (see above) for sample rates 32 kHz, 44.1 kHz, and 48 kHz and include
the same in the micro-based TAS5504 I C firmware.
2
41
SLES123 − October 2004
TAS5504
TAS5504 Controls and Status
•
On TAS5504 power up or reset, the micro runs the following TAS5504 Initialization code:
−
−
−
−
−
−
−
Update Bank 1 (Write 0x00048040 to register 0x40).
2
Write bank-related I C registers with appropriate values for Bank 1.
Write Bank 2 (Write 0x00058040 to register 0x40).
2
Load bank-related I C registers with appropriate values for Bank 2.
Write Bank 3 (Write 0x00068040 to register 0x40).
2
Load bank-related I C registers with appropriate values for Bank 3.
Select automatic bank switching (write 0x00038040 to register 0x40)
•
Now when the audio media changes, the TAS5504 automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
In this example any sample rates other then 32 kHz and 44.1 kHz will use Bank 3. If other sample rates are
used, then the banks need to be set−up differently.
2.5.6 Bank Switching Example 2
Problem: The audio system uses all of the sample rates supported by the TAS5504. How can the automatic
bank switching be set up to handle this situation?
Strategy: Use the TAS5504 bank switching feature to allow for managing and switching three banks
associated with sample rates as follows:
•
•
•
Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz
Bank 2: Coefficients for 88.2kHz and 96 kHz
Bank 3: Coefficients for 176.4 kHz and 192 kHz
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
•
Generate bank-related coefficients for sample rates 48 kHz (Bank 1), 96 kHz (Bank 2), and 192 kHz (Bank
3) and include the same in the micro-based TAS5504 I C firmware.
2
•
On TAS5504 power−up or reset, the micro runs the following TAS5504 Initialization code:
−
−
−
−
−
−
−
Update Bank 1 (Write 0x0004F00C to register 0x40).
2
Write bank-related I C registers with appropriate values for Bank 1.
Write Bank 2 (Write 0x0005F00C to register 0x40).
2
Load bank-related I C registers with appropriate values for Bank 2.
Write Bank 3 (Write 0x0006F00C to register 0x40).
2
Load bank-related I C registers with appropriate values for Bank 3.
Select automatic bank switching (Write 0x0003F00C to register 0x40)
•
Now when the audio media changes, the TAS5504 automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
42
TAS5504
SLES123 − October 2004
Electrical Specifications
3
Electrical Specifications
3.1 Absolute Maximum Ratings{
UNITS
Supply voltage, DVDD and DVD_PWM
Supply voltage, AVDD_PLL
−0.3 V to 3.6 V
−0.3 V to 3.6 V
3.3-V digital input
−0.5 V to DVDD + 0.5 V
−0.5 V to 6 V
(2)
5 V tolerant digital input
Input voltage
(3)
(1)
1.8 V LVCMOS
−0.5 V to VREF + 0.5 V
Input clamp current, I (V < 0 or V > 1.8 V
20 mA
20 mA
IK
I
I
Output clamp current, I (V < 0 or V > 1.8 V)
OK
O
O
Operating free air temperature
Storage temperature range, T
0°C to 70°C
−65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. VREF is a 1.8-V supply derived from regulators internal to the TAS5504 chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL,
VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source
power to external devices.
2. 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
3. VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM
DISSIPATION RATING TABLE (High-k Board, 1055C Junction)
T
A
≤ 255C
DERATING FACTOR
T
= 705C
A
PACKAGE
POWER RATING
ABOVE T = 255C
POWER RATING
A
PAG
1869 mW
23.36 mW/°C
818 mW
3.2 Dynamic Performance (At Recommended Operating Conditions at 255C)
PARAMETER
TEST CONDITIONS
MIN
NOM
102
MAX UNITS
Dynamic range 32 kHz to 192 kHz
TAS5504 + TAS5111 A-weighted
dB
TAS5111 A at 1 W
0.1%
0.01%
0.1
Total harmonic distortion
Frequency response
TAS5504 ouput
32-kHz to 96-kHz sample rates
176.4, 192-kHz sample rates
dB
0.2
3.3 Recommended Operating Conditions (over 05C to 705C)
MIN
3
NOM MAX UNITS
Digital supply voltage, DVDD and DVDD_PWM
Analog supply voltage, AVDD_PLL
3.3
3.3
3.6
3.6
V
V
3
3.3 V
2
(4)
5-V tolerant
2
High-level input voltage, V
V
V
IH
1.8-V LVCMOS (XTL_IN)
1.26
3.3 V
0.8
0.8
(4)
5-V tolerant
Low-level input voltage, V
IL
1.8-V (XTL_IN)
0.54
70
Operating ambient air temperature range, T
−20
−20
25
°C
°C
A
Operating junction temperature range, T
105
J
NOTE 4: 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
43
SLES123 − October 2004
TAS5504
Electrical Specifications
3.4 Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
(6)
3.3 V TTL and 5 V tolerant
1.8-V LVCMOS (XTL_OUT)
I
I
I
I
= −4 mA
= − 0.55 mA
= 4 mA
2.4
OH
OH
OL
OL
V
V
High-level output voltage
V
OH
1.44
(6)
3.3-V TTL and 5 V tolerant
0.5
Low-level output voltage
V
OL
1.8-V LVCMOS (XTL_OUT)
3.3-V TTL
= 0.75 mA
0.5
I
High-impedance output current
20
1
µA
µA
OZ
3.3-V TTL
V = V
I
IL
1.8-V LVCMOS (XTL_IN)
V = V
1
I
IL
Low-level input current
High-level input current
I
IL
(5)
5 V tolerant
V = 0 V DVDD = 3 V
I
1
3.3-V TTL
V = V
1
I
IH
IH
1.8-V LVCMOS (XTL_IN)
V = V
I
1
I
IH
µA
(5)
5 V tolerant
V = 5.5 V DVDD = 3 V
I
20
Fs = 48 kHz
Fs = 96 kHz
Fs = 192kHz
Power down
Normal
140
150
155
8
Digital supply voltage, DVDD
mA
mA
I
Input supply current
DD
20
2
Analog supply voltage, AVDD
Power down
NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5 PWM Operation at Recommended Operating Conditions Over 05C to 705C
PARAMETER
TEST CONDITIONS
MODE
VALUE
384
UNITS
kHz
32-kHz data rate 4%
12 x sample rate
44.1-, 88.2-, 176.4-kHz data rate 4%
48, 96, 192 kHz data rate 4%
8, 4, and 2 x sample rate
8, 4, and 2 x sample rate
352.8
384
kHz
Output sample rate 1X – 8 x over sampled
kHz
3.6 Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1 PLL Input Parameters and External Filter Components{
PARAMETER
Frequency, XTAL IN
Frequency, MCLK (1 / t
TEST CONDITIONS
MIN
TYP
MAX UNITS
f
f
Only use 13.5-MHz crystal ≤1000 ppm
13.5
MHz
XTALI
)
cyc2
2
50
MHz
MCLKI
MCLK duty cycle duty cycle
40%
50%
60%
≥2-V MCLK = 49.152 MHz, Within the min
and max duty cycle constraints
MCLK minimum high time
5
5
ns
ns
≤0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
MCLK minimum low time
LRCLK allowable drift before LRCLK reset
External PLL filter cap C1
10 MCLKs
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
SMD, Y5V
100
10
nF
nF
Ω
External PLL filter cap C2
External PLL filter resistor R
External VRA_PLL decoupling
200
100
nF
See the TAS5504 Example Application Schematic section.
44
TAS5504
SLES123 − October 2004
Electrical Specifications
3.6.2 Serial Audio Port
3.6.2.1 Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
2.048
10
TYP
MAX UNITS
f
t
t
t
t
Frequency, SCLK 64 x fs
C = 30 pF
L
12.288
MHz
ns
SCLKIN
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
su1
10
ns
h1
10
ns
su2
10
ns
h2
32
48
50%
50%
192
60%
60%
kHz
SCLK duty cycle
40%
40%
LRCLK duty cycle
SCLK
edges
SCLK rising edges between LRCLK rising edges
64
64
SCLK
period
LRCLK clock edge with respect to the falling edge of SCLK
−1/4
1/4
SCLK
(Input)
t
h1
t
su1
LRCLK
(Input)
t
h2
t
su2
SDIN1
SDIN2
SDIN3
Figure 3−1. Slave Mode Serial Data Interface Timing
45
SLES123 − October 2004
TAS5504
Electrical Specifications
3.6.3 I2C Serial Control Port Operation
3.6.3.1 Timing Characteristics for I2C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNITS
f
t
t
t
t
t
t
t
t
t
t
Frequency, SCL
No wait states
400
kHz
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
pF
SCL
w(H)
w(L)
r
Pulse duration, SCL high
0.6
1.3
Pulse duration, SCL low
Rise time, SCL and SDA
300
300
Fall time, SCL and SDA
f
Setup time, SDA to SCL
100
0
su1
h1
Hold time, SCL to SDA
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Load capacitance for each bus line
1.3
0.6
0.6
0.6
(buf)
su2
h2
su3
C
400
L
t
t
t
t
f
w(L)
w(H)
r
SCL
t
t
h1
su1
SDA
Figure 3−2. SCL and SDA Timing
SCL
t
t
(buf)
h2
t
t
su3
su2
SDA
Start Condition
Stop Condition
Figure 3−3. Start and Stop Conditions Timing
46
TAS5504
SLES123 − October 2004
Electrical Specifications
3.6.4 Reset Timing (RESET)
3.6.4.1 Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
400
10
TYP
MAX UNITS
t
t
t
t
Time to M-STATE low
370
ns
ns
r(DMSTATE)
w(RESET)
r(I2C_ready)
r(run)
Pulse duration, RESET active
None
2
Time to enable I C
3
ms
ms
Device startup time
RESET
Earliest time
that M-State
could be exited
t
w(RESET)
M-State
t
r(I2C_ready)
t
t
= ~ < 300 ns
r(run)
r(DMSTATE)
Start system
Determine SCLK rate
and MCLK ratio Enable I C
2
Figure 3−4. Reset Timing
Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock
ratio is determined, the system outputs audio if a master volume command is issued.
3.6.5 Power-Down (PDN) Timing
3.6.5.1
Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise
Noted)
PARAMETER
MIN
TYP
MAX UNITS
t
t
Time to M-STATE low
300
µs
p(DMSTATE)
Number of MCLKs preceding the release of PDN
Device startup time
5
120
ms
su
PDN
M-State
t
su
t
= ~ < 300 µs
p(DMSTATE)
Figure 3−5. Power-Down Timing
47
SLES123 − October 2004
TAS5504
Electrical Specifications
3.6.6 Backend Error (BKND_ERR)
3.6.6.1 Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
None
<100
UNITS
ns
t
t
t
Pulse duration, BKND_ERR active
350
w(ER)
µs
p(valid_low)
p(valid_high)
2
I C programmable to be between 1 to 10 ms
−25
25 % of interval
t
w(ER)
ERR_RCVRY
M-State
Normal
Normal
Operation
Operation
t
p(valid_high)
t
p(valid_low)
Figure 3−6. Error Recovery Timing
3.6.7 MUTE Timing—MUTE
3.6.7.1 Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX UNITS
(1)
t
Volume ramp time
Defined by rate setting
ms
d(VOL
NOTE 1: See the Volume Treble and Base Slew Rate Register (0xD0) section.
MUTE
VOLUME
Normal
Operation
Normal
Operation
M-State
t
t
d(VOL)
d(VOL)
Figure 3−7. Mute Timing
48
TAS5504
SLES123 − October 2004
Electrical Specifications
3.6.8 Headphone Select (HP_SEL)
3.6.8.1 Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
MAX UNITS
t
t
t
Pulse duration, HP_SEL active
350
None
ns
ms
ms
w(MUTE)
d(VOL)
(SW)
(2)
Soft volume update time
Switch-over time
Defined by rate setting
0.2
1 ms
NOTE 2: See the Volume Treble and Base Slew Rate Register (0xD0) section.
HP_SEL
Spkr Volume
t
d(VOL)
HP Volume
t
d(VOL)
t
(SW)
M-State
(Internal Device State)
HP_SEL
HP Volume
t
d(VOL)
Spkr Volume
t
d(VOL)
t
(SW)
M-State
Figure 3−8. HP_SEL Timing
49
SLES123 − October 2004
TAS5504
Serial Audio Interface Control and Timing
3.6.9 Volume Control
3.6.9.1 Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
−127
UNITS
Individual volume, master volume or a
combination of both
Maximum attenuation before mute
dB
Maximum gain
Individual volume, master volume
0-dB input, any modulation limit
PSVC enabled
18
0
dB
dB
dB
Maximum volume before the onset of clipping
PSVC range
12, 18, or 24
Fs
PSVC rate
PSVC modulation
Single Sided
2048
PSVC quantization
Steps
dB
6% (120 : 95% 1944 :
2048) 2048
PSVC PWM modulation limits
PSVC Rangel = 24 dB
3.7 Serial Audio Interface Control and Timing
3.7.1 I2S Timing
2
I S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of
bit clock. The TAS5504 masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
1
0
23 22
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
0
19 18
15 14
16-Bit Mode
15 14
NOTE: All data presented in 2s complement form with MSB first.
2
Figure 3−9. I S Format 64 Fs Format
50
TAS5504
SLES123 − October 2004
Serial Audio Interface Control and Timing
3.7.2 Left Justified
Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time
the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5504
masks unused trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
LRCLK
Right Channel
Left Channel
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
0
1
0
23 22
19 18
15 14
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−10. Left Justified 64 Fs Format
51
SLES123 − October 2004
TAS5504
Serial Audio Interface Control and Timing
3.7.3 Right Justified
Right justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5504
masks unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
Right Channel
Left Channel
MSB
LSB MSB
0
LSB
0
24-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
20-Bit Mode
16-Bit Mode
0
0
0
0
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−11. Right Justified 64 Fs Format
52
TAS5504
SLES123 − October 2004
I2C Serial Control Interface (Slave Address 0x36)
4
I2C Serial Control Interface (Slave Address 0x36)
The TAS5504 has a bidirectional I C interface that compatible with the I C (Inter IC) bus protocol and supports
both 100 Kbps and 400 Kbps data transfer rates for single and multiple byte write and read operations. This
is a slave only device that does not support a multi-master bus environment or wait state insertion. The control
interface is used to program the registers of the device and to read device status.
2
2
2
2
The TAS5504 supports the standard-mode I C bus operation (100 kHz maximum) and the fast I C bus
2
2
operation (400 kHz maximum). The TAS5504 performs all I C operations without I C wait cycles.
4.1 General I2C Operation
2
The I C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred
in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on
the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and
stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 4−1. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5504 holds SDA low during
acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next
byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All
compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
R/
W
8 Bit Register Data For
Address (N)
8 Bit Register Data For
Address (N)
SDA
SCL
7 Bit Slave Address
A
8 Bit Register Address (N)
A
A
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Start
Stop
2
Figure 4−1. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the
last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
is shown in Figure 4−1.
The 7-bit address for the TAS5504 is 0011011.
4.2 Single and Multiple Byte Transfers
The serial control interface supports both single-byte and multiple-byte read / write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data processing
registers, the serial control interface supports only multiple byte (4 byte) read / write operations.
During multiple byte read operations, the TAS5504 responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular
subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple byte write operations, the TAS5504 compares the number of bytes transmitted to the number
of bytes that are required for each specific sub address. If a write command is received for a biquad
subaddress, the TAS5504 expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
Similarly, if a write command is received for a mixer coefficient, the TAS5504 expects to receive one 32-bit
word.
53
SLES123 − October 2004
TAS5504
I2C Serial Control Interface (Slave Address 0x36)
2
Supplying a subaddress for each subaddress transaction is referred to as random I C addressing. The
2
TAS5504 also supports sequential I C addressing. For write transactions, if a subaddress is issued followed
2
by data for that subaddress and the fifteen subaddresses that follow, a sequential I C write transaction has
2
taken place, and the data for all 16 subaddresses is successfully received by the TAS5504. For I C sequential
write transactions, the subaddress then serves as the start address and the amount of data subsequently
transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true
for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a
partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,
all other data written is accepted; just the incomplete data is discarded.
4.3 Single Byte Write
As shown in Figure 4−2, a single byte data write transfer begins with the master device transmitting a start
2
condition followed by the I C device address and the read/write bit. The read/write bit determines the direction
2
of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I C device
address and the read/write bit, the TAS5504 device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5504 internal memory address being accessed.
After receiving the address byte, the TAS5504 again responds with an acknowledge bit. Next, the master
device transmits the data byte to be written to the memory address being accessed. After receiving the data
byte, the TAS5504 again responds with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single byte data write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Stop
Condition
2
I C Device Address and
Sub-Address
Data Byte
Read/Write Bit
Figure 4−2. Single Byte Write Transfer
4.4 Multiple Byte Write
A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5504 as shown in Figure 4−3. After receiving each data byte, the
TAS5504 responds with an acknowledge bit.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
R/W
A6 A5
A1 A0
ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
Stop
Condition
2
Other Data Bytes
I C Device Address and
Read/Write Bit
Sub-Address
First Data Byte
Last Data Byte
Figure 4−3. Multiple Byte Write Transfer
4.5 Incremental Multiple Byte Write
2
2
The I C supports a special mode which permits I C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte, ... etc., write
operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes
2
of data. This permits the system to incrementally write large register values without blocking other I C
transactions.
This feature is enabled by the append subaddress function in the TAS5504. This function enables the
2
TAS5504 to append 4 bytes of data to a register that was opened by a previous I C register write operation
but has not received its complete number of data bytes. Since the length of the long registers is a multiple of
4 bytes, using 4-byte transfers will have only an integer number of append operations.
54
TAS5504
SLES123 − October 2004
I2C Serial Control Interface (Slave Address 0x36)
When the correct number of bytes has been received, the TAS5504 starts processing the data.
The procedure to perform an incremental multi-byte write operation is as follows:
2
1. Start a normal I C write operation by sending the device address, write bit, register subaddress, and the
first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point,
the register has been opened and accepts the remaining data that is sent by writing 4-byte blocks of data
to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining
number of bytes in sequential order to complete the register write operation. Each of these append
operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes
of data followed by a stop condition.
3. The operation will be terminated due to an error condition and the data will be flushed:
a. If a new subaddress is written to the TAS5504 before the correct number of bytes have been written.
b. If more or less than 4 bytes are data written at the beginning or during any of the append operations.
c. If a read bit is sent.
4.6 Single Byte Read
As shown in Figure 4−4, a single byte data read transfer begins with the master device transmitting a start
2
condition followed by the I C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit will be a 0. After receiving the TAS5504 address
and the read/write bit, the TAS5504 responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5504
address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After
receiving the TAS5504 and the read/write bit the TAS5504 again responds with an acknowledge bit. Next, the
TAS5504 transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not acknowledge followed by a stop condition to complete the single byte data read
transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Sub-Address
I C Device Address and
Read/Write Bit
Data Byte
Figure 4−4. Single Byte Read Transfer
4.7 Multiple Byte Read
A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes
are transmitted by the TAS5504 to the master device as shown in Figure 4−5. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
A6
A0 R/W ACK
A6
A0 R/W ACK D7
D0 ACK
A7 A6 A5
2
2
I C Device Address and
Read/Write Bit
Sub-Address
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 4−5. Multiple Byte Read Transfer
55
SLES123 − October 2004
TAS5504
I2C Serial Control Interface (Slave Address 0x36)
56
TAS5504
SLES123 − October 2004
Serial Control I2C Register Summary
5
Serial Control I2C Register Summary
2
The TAS5504 slave address is 0x36. See the Serial Control I C Register Bit Definitions chapter for complete
bit definitions.
Note that u indicates unused bits.
2
I C
TOTAL
REGISTER FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
1. Fs = 48 kHz
SUBADDRESS BYTES
0x00
0x01
0x02
1
1
1
Clock control register
Set data rate and MCLK frequency
2. MCLK = 256 Fs = 12.288 MHz
General status register
Error status register
Clip indicator and ID code for the
TAS5504
0x01
PLL, SCLK, LRCLK, and frame slip
errors
No errors
1. PWM high pass disabled
2. Auto clock set
3. Hard un-mute on clock error
recovery
PWM high pass, clock set, un-mute
select, PSVC select
0x03
0x04
1
1
System control register 1
System control register 2
4. PSVC HIZ disable
1. Automute timeout disable
2. Post-DAP detection automute
enabled
3. 4-Ch device input detection
automute enabled
Automute and de-emphasis control
4. Un-mute threshold 6 dB over input
5. No de-emphasis
1. Enable backend reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Don’t remap the output for the
TAS5182
0x05 – 0x06
1
Channel configuration registers Configure channels 1 and 2
6. Don’t go low-low in mute
7. Don’t remap Hi-Z state to
low-low state
0x07 – 0x0A
0x0B – 0x0C
Reserved
1. Enable backend reset2. Valid
low for reset3. Valid low for mute4.
Normal BEPolarity5. Don’t remap
the output for the TAS51826. Don’t
go low-low in mute7. Don’t remap
Hi-Z state to low-low state
Channel configuration registers Configure channels 3 and 4
1. Disable backend reset sequence
2 Valid does not have to be low for
reset
3. Valid does not have to be low for
mute
4. Normal BEPolarity
5. Don’t remap output to comply
with 5182
Headphone configuration
Configure headphone output
register
0x0D
0x0E
1
6. Don’t go low-low in mute
7. Don’t remap Hi−Z state to
low-low state
1
1
Serial data interface register
Soft mute register
Set serial data interface to right
justified, I2S, or left justified
24-bit I2S
0x0F
Soft mute for channels 1, 2, 3, and 4
RESERVED
Un-mute all channels
0x10 – 0x13
57
SLES123 − October 2004
TAS5504
Serial Control I2C Register Summary
2
I C
TOTAL
REGISTER FIELDS
Automute control
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
0x14
0x15
1
Set auto-mute delay and threshold
1. Set auto-mute delay = 5 ms
2. Set auto-mute threshold less
than bit 8.
1
Automute PWM threshold and
backend reset period
Set PWM auto-mute threshold, set
backend reset period
1. Set the PWM threshold the same
as the TAS5504 input threshold.
2. Set the backend reset
period = 5 ms.
0x16
1
Modulation limit register
Set modulation index
RESERVED
97.7%
0x17−0x1A
Channel 1 delay = −23 DCLK
periods
Channel 2 delay = 0 DCLK periods
Sets inter-channel delay for channels
1 and 2
0x1B–0x1C
1/Reg. Inter-channel delay registers
0x1D−0x20
RESERVED
Channel 3 delay = −8 DCLK
periods
Channel 4 delay = 24 DCLK
periods
Sets inter-channel delay for channels
3 and 4
0x21–0x22
0x23
1/Reg. Inter-channel delay registers
1
4
Inter-channel offset
Absolute delay offset for channel 1
(0 – 255)
Minimum absolute default = 0
DCLK periods
0x24−0x3F
RESERVED
0x40
Bank switching command
register
Set up DAP coefficients bank
switching for banks 1, 2, and 3
Manual selection – Bank 1
See the Input Mixer Registers
32/Reg (0x41 and 0x42, Channels 1
and 2) section
SDIN1−Left to input mixer 1
SDIN1−Right to input mixer 2
0x41–0x42
0x43–0x46
0x47–0x48
8X4 input crossbar mixer setup
RESERVED
See the Input Mixer Registers
32/Reg (0x47 and 0x48, Channels 3
and 4) section
SDIN4−Left to input mixer 3
SDIN4−Right to input mixer 4
8X4 input crossbar mixer setup
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
4
4
4
4
4
4
ipmix_1_to_ch4
ipmix_2_to_ch4
ipmix_3_to_ch2
Ch3_bp_bq2
Input mixer 1 to Ch 4 mixer coefficient 0.0
Input mixer 2 to Ch 4 mixer coefficient 0.0
Input mixer 3 to Ch 2 mixer coefficient 0.0
Bypass Ch 3 biquad 2 coefficient
Ch 3 biquad 2 coefficient
0.0
1.0
0.0
Ch3_bq2
ipmix_4_to_ch12
Ch 4 biquad 2 output to Ch1 mixer
and Ch2 mixer coefficient
0x4F
0x50
4
4
Ch4_bp_bq2
Ch4_bq2
Bypass Ch 4 biquad 2 coefficient 0
Ch 4 biquad 2 coefficient
0.0
1.0
0x51–0x5E
20/Reg. See the next section
Channels 1, 2, 3, and 4 biquad filter
coefficients
All biquads = All pass
0x89–0x8A
8
8
Bass and Treble Bypass
Ch 1 and 2
Bypass bass and treble for
channels 1 and 2
Bass and treble bypassed for
channels 1 and 2
0x8B−0x8E
0x8F−0x90
RESERVED
Bass and treble bypass Ch 3
and 4
Bypass bass and treble for channels 3 Bass and treble bypassed for
and 4
channels 3 and 4
0x91
0x92
0x93
0x94
4
8
4
8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness Log2 LG
Loudness Log2 LO
Loudness G
0.5
0.0
0.0
0.0
Loudness O
Loudness O
58
TAS5504
SLES123 − October 2004
Serial Control I2C Register Summary
DEFAULT STATE
2
I C
TOTAL
REGISTER FIELDS
DESCRIPTION OF CONTENTS
SUBADDRESS BYTES
0x5F−0x7A
RESERVED
0x7B−0x88
20/Reg See the next section
Channels 3 and 4 biquad filter
coefficient
All biquads = All pass
Loudness biquad coefficient b0
Loudness biquad coefficient b1
Loudness biquad coefficient b2
Loudness biquad coefficient a0
Loudness biquad coefficient a1
DRC1 control channels 1, 2, and 3
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
0x95
20
Loudness biquad
0x96
0x97
4
4
DRC1 control channels 1, 2,
and 3
DRC1 disabled in channels 1, 2,
and 3
DRC2 Ch 4 Control
DRC1 control channel 4
DRC1 energy
DRC2 disabled (channel 4)
0.0041579
Channels 1, 2, and 3,
DRC1 energy
0x98
0x99
8
Channels 1, 2, 3, and 4,
DRC1 (1− energy)
DRC1 (1 energy)
0.9958421
Channels 1, 2, and 3,
DRC1 threshold T1
DRC1 threshold (T1) – upper 4 bytes
DRC1 threshold (T1) – lower 4 bytes
DRC1 threshold (T2) – upper 4 bytes
DRC1 threshold (T2) – lower 4 bytes
DRC1 slope (k0)
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x0F, 0xC0, 0x00, 0x00
16
Channels 1, 2, and 3,
DRC1 thresholdT2
Channels 1, 2, and 3,
DRC1 slope k0
Channels 1, 2, and 3,
DRC1 slope k1
DRC1 slope (k1)
DRC1 slope (k2)
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x9A
0x9B
12
16
Channels 1, 2, and 3,
DRC1 slope k2
Channels 1, 2, and 3,
DRC1 offset 1
DRC1 offset 1 (O1) – upper 4 bytes
DRC1 offset 1 (O1) – lower 4 bytes
DRC1 offset 2 (O2) – upper 4 bytes
DRC1 offset 2 (O2) – lower 4 bytes
DRC1 attack
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
Channels 1, 2, and 3,
DRC1 offset 2
Channels 1, 2, and 3,
DRC1 attack
Channels 1, 2, and 3,
DRC1 (1− Attack)
DRC1 (1 – Attack)
DRC1 delay
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
0x9C
16
Channels 1, 2, and 3,
DRC1 Delay
Channels 1, 2, 3, and 3,
DRC1 (1 – Delay)
DRC1 (1− Delay)
Ch 4 DRC2 energy
DRC2 energy
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x9D
0x9E
8
Ch 4 DRC2 (1− Energy)
DRC2 (1 – Energy)
DRC2 threshold (T1) – upper 4 bytes
DRC2 threshold (T1) – lower 4 bytes
DRC2 threshold (T2) – upper 4 bytes
DRC2 threshold (T2) – lower 4 bytes
DRC2 slope (k0)
CH 4 DRC2 threshold T1
CH 4 DRC2 threshold T2
16
Ch 4 DRC2 slope k0
Ch 4 DRC2 slope k1
Ch 4 DRC2 slope k2
DRC2 slope (k1)
0x9F
12
DRC2 slope (k2)
59
SLES123 − October 2004
TAS5504
Serial Control I2C Register Summary
2
I C
TOTAL
REGISTER FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
DRC2 offset (O1) – upper 4 bytes
DRC2 offset (O1) – lower 4 bytes
DRC2 offset (O2) – upper 4 bytes
DRC2 offset (O2) – lower 4 bytes
DRC 2 attack
0x00, 0x00, 0xFF, 0xFF
Ch 4 DRC2 offset 1
0xFF, 0x82, 0x30, 0x98
0xA0
16
0x00, 0x00, 0x00, 0x00
Ch 4 DRC2 offset 2
0x01, 0x95, 0xB2, 0xC0
Ch 4 DRC2 attack
Ch 4 DRC2 (1− Attack)
Ch 4 DRC2 Delay
Ch 4 DRC2 (1− Delay)
DRC bypass 1
0x00, 0x00, 0x88, 0x3F
DRC2 (1 – Attack)
0x00, 0x7F, 0x77, 0xC0
0xA1
0xA2
16
8
DRC2 delay
0x00, 0x00, 0x00, 0xAE
DRC2 (1 – Delay)
0x00, 0x7F, 0xFF, 0x51
Channel 1 DRC1 bypass coefficient
Channel 1 DRC1 inline coefficient
Channel 2 DRC1 bypass coefficient
Channel 2 DRC1 inline coefficient
Reserved
1.0
DRC inline 1
0.0
DRC bypass 2
1.0
0xA3
8
8
DRC inline 2
0.0
0xA4−0xA7
Reserved
DRC bypass 3
DRC inline 3
Channel 3 DRC1 bypass coefficient
Channel 3 DRC1 inline coefficient
Channel 4 DRC2 bypass coefficient
Channel 4 DRC2 inline coefficient
1.0
0xA8
8
0.0
DRC bypass 4
DRC inline 4
1.0
0xA9
0xAA
8
8
0.0
sel op1−4 and mix to S
Select 0 to 2 of four DAP channels to
output mixer S
Select channel 1 to PWM 1
0xAB
8
sel op1−4 and mix to T
Select 0 to 2 of four DAP channels to
output mixer T
Select channel 2 to PWM 2
0xAC–0xAF
0xB0
RESERVED
12
12
sel op1−4 and mix to Y
sel op1−4 and mix to Z
Select 0 to 3 of four DAPchannels to
output mixer Y
Select channel 3 to PWM 3
Select channel 4 to PWM 4
0xB1
Select 0 to 3 of four DAP channels to
output mixer Z
0xB2–0xCE
0xCF
RESERVED
20
4
Volume biquad
Volume biquad
All pass
0xD0
Vol, T, and B slew rates
U (31:24), U (23:16), U (15:12)
VSR(11:8), TBSR(7:0)
0x00, 0x00, 0x02, 0x3F
0xD1
0xD2
4
4
Ch1 volume
Ch2 volume
Channel 1 volume
0 dB
0 dB
Channel 2 volume
0xD3–0xD6
0xD7
RESERVED
4
4
4
4
4
4
4
4
Ch3 volume
Channel 3 volume
0 dB
0xD8
Ch4 volume
Channel 4 volume
0 dB
0xD9
Master volume
Bass filter set
Bass filter index
Treble filter set
Treble filter index
Master volume
Mute
OXDA
0xDB
Bass filter set (all channels)
Bass filter level (all channels)
Treble filter set (all channels)
Treble filter level (all channels)
Filter set 3
0 dB
0xDC
Filter set 3
0 dB
0xDD
0xDE
AM mode and tuned frequency Set-up AM mode for AM-interference
AM mode disabled
register
reduction
Select sequence 1
IF frequency = 455 kHz
Use BCD-tuned frequency
0xDF
0xE0
4
4
PSVC control range
Set PSVC control range
12-dB control range
General control register
Four channel configuration, PSVC
enable
Four channel configuration, power
supply volume control disabled
0xE1–0xFD
RESERVED
60
TAS5504
SLES123 − October 2004
Serial Control I2C Register Summary
2
I C
TOTAL
REGISTER FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
0xFE
0xFF
4 (min) Multiple byte write append
register
Special register
N/A
RESERVED
61
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6
Serial Control Interface Register Definitions
2
Unless otherwise noted, the I C register default values are in bold font.
Note that u indicates unused bits.
6.1 Clock Control Register (0x00)
Bit D1 is Don’t Care.
Table 6−1. Clock Control Register
D7
0
0
0
0
1
1
1
1
−
−
−
−
−
−
−
−
−
−
D6
0
0
1
1
0
0
1
1
−
−
−
−
−
−
−
−
−
−
D5
0
1
0
1
0
1
0
1
−
−
−
−
−
−
−
−
−
−
D4
−
−
−
−
−
−
−
−
0
0
0
0
1
1
1
1
−
−
D3
−
−
−
−
−
−
−
−
0
0
1
1
0
0
1
1
−
−
D2
−
−
−
−
−
−
−
−
0
1
0
1
0
1
0
1
−
−
D1
D0
FUNCTION
−
32-kHz data rate
−
38-kHz data rate
−
44.1-kHz data rate
48-kHz data rate
−
−
88.2-kHz data rate
96-kHz data rate
−
−
176.4-kHz data rate
192-kHz data rate
−
MCLK frequency = 64
MCLK frequency = 128
MCLK frequency = 192
MCLK frequency = 256
MCLK frequency = 384
MCLK frequency = 512
MCLK frequency = 768
Reserved
1
Clock register is valid (read only)
0
Clock register is not valid (read only)
6.2 General Status Register 0 (0x01)
Table 6−2. General Status Register (0x01)
D7
1
D6
−
D5
−
D4
−
D3
−
D2
D1
D0
FUNCTION
−
−
−
Clip indicator
−
1
−
−
−
−
−
−
Bank switching busy
Identification code for TAS5504
−
−
0
0
0
0
0
1
6.3 Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and than read them to determine if there are any persistent errors.
Table 6−3. Error Status Register (0X02)
D7
1
D6
−
D5
−
D4
−
D3
−
D2
−
D1
D0
FUNCTION
−
−
PLL phase lock error
PLL auto lock error
SCLK error
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
LRCLK error
−
−
−
−
1
−
−
−
Frame slip
0
0
0
0
0
0
0
0
No errors
63
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.4 System Control Register 1 (0x03)
Bit D5, D2, D1, and D0 are Don’t Care.
Table 6−4. System Control Register 1
D7
0
D6
−
D5
D4
−
D3
−
D2
D1
D0
FUNCTION
PWM high pass disabled
1
−
−
−
PWM high pass enabled
−
−
0
Soft unmute on recovery from clock error
Hard unmute on recovery from clock error
PSVC Hi-Z enable
−
−
1
−
−
−
1
−
−
−
0
PSVC Hi-Z disable
6.5 System Control Register 2 (0x04)
Bit D3 and D2 are Don’t Care.
Table 6−5. System Control Register 2
D7
0
D6
−
D5
−
−
−
0
D4
−
−
−
−
−
0
D3
D2
D1
−
−
−
−
−
−
−
0
D0
−
−
−
−
−
−
−
0
FUNCTION
Reserved
−
0
PWM automute detection enabled
PWM automute detection disabled
4 Ch device input detection automute enabled
4 Ch device input detection automute disabled
Unmute threshold 6 dB over input threshold
Unmute threshold equal to input threshold
No de-emphasis
−
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
1
−
−
−
−
0
1
De-emphasis for Fs = 32 kHz
1
0
De-emphasis for Fs = 44.1 kHz
1
1
De-emphasis for Fs = 48 kHz
6.6 Channel Configuration Control Register (0x05−X0C)
Channels 1, 2, 3, and 4 are mapped into x05, x06, x0B, and x0C.
Bit D0 is Don’t Care.
Table 6−6. Channel Configuration Control Registers
D7
0
D6
−
−
0
D5
−
−
−
−
0
D4
−
−
−
−
−
−
0
D3
−
−
−
−
−
−
−
−
0
D2
−
−
−
−
−
−
−
−
−
−
0
D1
−
−
−
−
−
−
−
−
−
−
−
−
0
D0
FUNCTION
Disable backend reset sequence for a channel − BEErrorRecEn
Enable backend reset sequence for a channel
Valid does not have to be low for this channel to be reset BEValidRst
Valid must be low for this channel to be reset
Valid does not have to be low for this channel to be muted BEValidMute
Valid must be low for this channel to be muted
Normal BEPolarity
1
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
Switches PWM+ and PWM− and invert audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
−
−
−
−
−
−
1
−
−
−
−
Do not go to low low in mute − BELowMute
Go to low-low in Mute
1
−
−
Do not remap Hi-Z state to low-low state − BE5111BsMute
Remap Hi-Z state to low-low state
1
64
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
6.7 Headphone Configuration Control Register (0x0D)
Bit D0 is Don’t Care.
Table 6−7. Headphone Configuration Control Register
D7
0
D6
−
−
0
D5
−
−
−
−
0
D4
−
−
−
−
−
−
0
D3
−
−
−
−
−
−
−
−
0
D2
−
−
−
−
−
−
−
−
−
−
0
D1
−
−
−
−
−
−
−
−
−
−
−
−
0
D0
FUNCTION
Disable backend reset sequence for a channel − BEErrorRecEn
Enable backend reset sequence for a channel
Valid does not have to be low for this channel to be reset BEValidRst
Valid must be low for this channel to be reset
Valid does not have to be low for this channel to be muted BEValidMute
Valid must be low for this channel to be muted
Normal BEPolarity
1
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
Switches PWM+ and PWM− and invert audio signal
Do not remap output to comply with 5182 interface
Remap output to comply with 5182 interface
−
−
−
−
−
−
1
−
−
−
−
Do not go to low low in mute − BELowMute
Go to low-low in Mute
1
−
−
Do not remap Hi-Z state to low-low state − BE5111BsMute
Remap Hi-Z state to low-low state
1
6.8 Serial Data Interface Control Register (0x0E)
2
Nine serial modes can be programmed I C.
Table 6−8. Serial Data Interface Control Register Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
D7−D4
D3 D2
D1
D0
Right justified
Right justified
Right justified
16
20
24
16
20
24
16
20
24
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
I S
2
I S
2
I S
Left justified
Left justified
Left justified
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
65
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.9 Soft Mute Register (0x0F)
Table 6−9. Soft Mute Register
D7
−
D6
−
D5
−
D4
−
D3
D2
D1
D0
Function
−
−
−
1
Soft Mute Channel 1
Soft Mute Channel 2
Soft Mute Channel 3
Soft Mute Channel 4
Unmute All Channels
−
−
−
−
−
−
1
−
−
1
−
−
−
−
−
−
1
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
6.10 Automute Control Register(0x14)
Table 6−10. Automute Control Register
D7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Set input automute and PWM automute delay to 1 ms
Set input automute and PWM automute delay to 2 ms
Set input automute and PWM automute delay to 3 ms
Set input automute and PWM automute delay to 4 ms
Set input automute and PWM automute delay to 5 ms
Set input automute and PWM automute delay to 10 ms
Set input automute and PWM automute delay to 20 ms
Set input automute and PWM automute delay to 30 ms
Set input automute and PWM automute delay to 40 ms
Set input automute and PWM automute delay to 50 ms
Set input automute and PWM automute delay to 60 ms
Set input automute and PWM automute delay to 70ms
Set input automute and PWM automute delay to 80 ms
Set input automute and PWM automute delay to 90 ms
Set input automute and PWM automute delay to 100 ms
Set input automute and PWM automute delay to 110 ms
Set input automute threshold less than Bit 1 (zero input signal), lowest automute
threshold.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Set input automute threshold less than Bit 2
Set input automute threshold less than Bit 3
Set input automute threshold less than Bit 4
Set input automute threshold less than Bit 5
Set input automute threshold less than Bit 6
Set input automute threshold less than Bit 7
Set input automute threshold less than Bit 8
Set input automute threshold less than Bit 9
Set input automute threshold less than Bit 10
Set input automute threshold less than Bit 11
Set input automute threshold less than Bit 12
Set input automute threshold less than Bit 13
Set input automute threshold less than Bit 14
Set input automute threshold less than Bit 15
66
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
6.11 Automute PWM Threshold and Backend Reset Period (0x15)
Table 6−11. Automute PWM Threshold and Backend Reset Period
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
−
−
−
−
−
−
−
−
−
−
−
−
−
D3
−
−
−
−
−
−
−
−
−
−
−
−
−
D2
−
−
−
−
−
−
−
−
−
−
−
−
−
D1
−
−
−
−
−
−
−
−
−
−
−
−
−
D0
−
−
−
−
−
−
−
−
−
−
−
−
−
FUNCTION
Set PWM automute threshold equals input automute threshold
Set PWM automute threshold 1 bit more than input automute threshold
Set PWM automute threshold 2 bits more than input automute threshold
Set PWM automute threshold 3 bits more than input automute threshold
Set PWM automute threshold 4 bits more than input automute threshold
Set PWM automute threshold 5 bits more than input automute threshold
Set PWM automute threshold 6 bits more than input automute threshold
Set PWM automute threshold 7 bits more than input automute threshold
Set PWM automute threshold equals input automute threshold
Set PWM automute threshold 1 bit less than input automute threshold
Set PWM automute threshold 2 bits less than input automute threshold
Set PWM automute threshold 3 bits less than input automute threshold
Set PWM automute threshold 4 bits less than input automute threshold
Set PWM automute threshold 5 bits less than input automute threshold
Set PWM automute threshold 6 bits less than input automute threshold
Set PWM automute threshold 7 bits less than input automute threshold
Set backend reset period < 1 ms
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Set backend reset period 1 ms
Set backend reset period 2 ms
Set backend reset period 3 ms
Set backend reset period 4 ms
Set backend reset period 5 ms
Set backend reset period 6 ms
Set backend reset period 7 ms
Set backend reset period 8 ms
Set backend reset period 9 ms
Set backend reset period 10 ms
Set backend reset period 10 ms
Set backend reset period 10 ms
67
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.12 Modulation Index Limit Register (0x16)
Table 6−12. Modulation Index Limit Register
LIMIT
[DCLKS]
MIN WIDTH
[DCLKS]
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION INDEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
2
4
99.2%
98.4%
97.7%
96.9%
96.1%
95.3%
94.5%
93.8%
6
8
10
12
14
16
6.13 Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23)
Channels 1, 2, 3, and 4 are mapped into (0x1B, 0x1C, 0x21, and 0x22).
Bits D1 and D0 are Don’t Care.
Table 6−13. Interchannel Channel Delay Registers
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for channel 1
Maximum positive delay, 31 x 4 DCLK cycles
Maximum negative delay, −32 x 4 DCLK cycles
Default value for Channel 1 −32
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Default value for Channel 2 0
1
1
1
0
0
0
Default value for Channel 3 −8
0
1
1
0
0
0
Default value for Channel 4 24
The offset register is mapped into 0x23.
Table 6−14. Channel Offset Register
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Minimum absolute offset, 0 DCLK cycles default for channel 1
Maximum absolute delay, 255 DCLK cycles
1
1
1
1
1
1
1
1
68
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
6.14 Bank Switching Command (0x40)
Bits D31−D24, D22−D19 are Don’t Care.
Table 6−15. Bank Switching Command
D31
D30
D22
D29
D21
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
−
D20
D19
D18
0
D17
0
D16
0
FUNCTION
Manual selection Bank 1
Manual selection Bank 2
Manual selection Bank 3
Automatic bank selection
Update the values in Bank 1
Update the values in Bank 2
Update the values in Bank 3
Update only the bank map
−
0
0
1
−
0
1
0
−
0
1
1
−
1
0
0
−
1
0
1
−
1
1
0
0
1
1
1
0
x
x
x
Update the bank map using values in
D15−D0
1
x
x
x
Do not update the bank map using
values in D15−D0
D15
1
D14
−
D13
−
D12
−
D11
−
D10
−
D9
−
D8
−
FUNCTION
32-kHz data rate – Use Bank 1
38-kHz data rate – Use Bank 1
44.1-kHz data rate – Use Bank 1
48-kHz data rate – Use Bank 1
88.2-kHz data rate – Use Bank 1
96-kHz data rate – Use Bank 1
176.4-kHz data rate – Use Bank 1
192-kHz data rate – Use Bank 1
Default
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
1
1
1
1
1
1
1
1
D7
1
D6
−
D5
−
D4
−
D3
−
D2
−
D1
−
D0
−
FUNCTION
32-kHz data rate – Use Bank 2
38-kHz data rate – Use Bank 2
44.1-kHz data rate – Use Bank 2
48-kHz data rate – Use Bank 2
88.2-kHz data rate – Use Bank 2
96-kHz data rate – Use Bank 2
176.4-kHz data rate – Use Bank 2
192-kHz data rate – Use Bank 2
Default
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
−
1
1
1
1
1
1
1
1
1
69
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.15 Input Mixer Registers (0x41, 0x42, 0x47, 0x48, Channels 1−4)
Input mixers 1, 2, 3, and 4 are mapped into registers 0x41, 0x42, 0x47, and 0x48.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
Table 6−16. Input Mixer Registers Format (Channels 1−4)
2
I C
TOTAL
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
SDIN1−Left A to Input Mixer 1 coefficient (default = 1)
U (31:28), A_1 (27:24), A_1 (23:16), A_1 (15:8), A_1 (7:0)
0x00, 0x80, 0x00, 0x00
A_to_ipmix[1]
B_to_ipmix[1]
C_to_ipmix[1]
D_to_ipmix[1]
E_to_ipmix[1]
F_to_ipmix[1]
G_to_ipmix[1]
H_to_ipmix[1]
A_to_ipmix[2]
B_to_ipmix[2]
C_to_ipmix[2]
D_to_ipmix[2]
E_to_ipmix[2]
F_to_ipmix[2]
G_to_ipmix[2]
H_to_ipmix[2]
SDIN1−Right B to Input Mixer 1 coefficient (default = 0)
U (31:28), B_1 (27:24), B_1 (23:16), B_1 (15:8), B_1 (7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
SDIN2−Left C to Input Mixer 1 coefficient (default = 0)
U (31:28), C_1 (27:24), C_1 (23:16), C_1 (15:8), C_1 (7:0)
SDIN2−Right D to Input Mixer 1 coefficient (default = 0)
U (31:28), D_1 (27:24), D_1 (23:16), D_1 (15:8), D_1 (7:0)
0x41
32
SDIN3−Left E to Input Mixer 1 coefficient (default = 0)
U (31:28), E_1 (27:24), E_1 (23:16), E_1 (15:8), E_1 (7:0)
SDIN3−Right F to Input Mixer 1 coefficient (default = 0)
U (31:28), F_1 (27:24), F_1 (23:16), F_1 (15:8), F_1 (7:0)
SDIN4−Left G to Input Mixer 1 coefficient (default = 0)
U (31:28), G_1 (27:24), G_1 (23:16), G_1 (15:8), G_1 (7:0)
SDIN4−Right H to Input Mixer 1 coefficient (default = 0)
U (31:28), H_1 (27:24), H_1 (23:16), H_1 (15:8), H_1 (7:0)
SDIN1−Left A to Input Mixer 2 coefficient (default = 0)
U (31:28), A_2 (27:24), A_2 (23:16), A_2 (15:8), A_2 (7:0)
SDIN1−Right B to Input Mixer 2 coefficient (default = 1)
U (31:28), B_2 (27:24), B_2 (23:16), B_2 (15:8), B_2 (7:0)
SDIN2−Left C to Input Mixer 2 coefficient (default = 0)
U (31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)
SDIN2−Right D to Input Mixer 2 coefficient (default = 0)
U (31:28), D_2 (27:24), D_2 (23:16), D_2 (15:8), D_2 (7:0)
0x42
32
SDIN3−Left E to Input Mixer 2 coefficient (default = 0)
U (31:28), E_2 (27:24), E_2 (23:16), E_2 (15:8), E_2 (7:0)
SDIN3−Right F to Input Mixer 2 coefficient (default = 0)
U (31:28), F_2 (27:24), F_2 (23:16), F_2 (15:8), F_2 (7:0)
SDIN4−Left G to Input Mixer 2 coefficient (default = 0)
U (31:28), G_2 (27:24), G_2 (23:16), G_2 (15:8), G_2 (7:0)
SDIN4−Right H to Input Mixer 2 coefficient (default = 0)
U (31:28), H_2 (27:24), H_2 (23:16), H_2 (15:8), H_2 (7:0)
70
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
2
I C
TOTAL
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
SDIN1−Left A to Input Mixer 3 coefficient (default = 0)
U (31:28), A_3 (27:24), A_3 (23:16), A_3 (15:8), A_3 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[3]
B_to_ipmix[3]
C_to_ipmix[3]
D_to_ipmix[3]
E_to_ipmix[3]
F_to_ipmix[3]
G_to_ipmix[3]
H_to_ipmix[3]
A_to_ipmix[4]
B_to_ipmix[4]
C_to_ipmix[4]
D_to_ipmix[4]
E_to_ipmix[4]
F_to_ipmix[4]
G_to_ipmix[4]
H_to_ipmix[4]
SDIN1−Right B to Input Mixer 3 coefficient (default = 0)
U (31:28), B_3 (27:24), B_3 (23:16), B_3 (15:8), B_3 (7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
SDIN2−Left C to Input Mixer 3 coefficient (default = 0)
U (31:28), C_3 (27:24), C_3 (23:16), C_3 (15:8), C_3 (7:0)
SDIN2−Right D to Input Mixer 3 coefficient (default = 0)
U (31:28), D_3 (27:24), D_3 (23:16), D_3 (15:8), D_3 (7:0)
0x47
32
SDIN3−Left E to Input Mixer 3 coefficient (default = 0)
U (31:28), E_3 (27:24), E_3 (23:16), E_3 (15:8), E_3 (7:0)
SDIN3−Right F to Input Mixer 3 coefficient (default = 0)
U (31:28), F_3 (27:24), F_3 (23:16), F_3 (15:8), F_3 (7:0)
SDIN4−Left G to Input Mixer 3 coefficient (default = 1)
U (31:28), G_3 (27:24), G_3 (23:16), G_3 (15:8), G_3 (7:0)
SDIN4−Right H to Input Mixer 3 coefficient (default = 0)
U (31:28), H_3 (27:24), H_3 (23:16), H_3 (15:8), H_3 (7:0)
SDIN1−Left A to Input Mixer 4 coefficient (default = 0)
U (31:28), A_4 (27:24), A_4 (23:16), A_4 (15:8), A_4 (7:0)
SDIN1−Right B to Input Mixer 4 coefficient (default = 0)
U (31:28), B_4 (27:24), B_4 (23:16), B_4 (15:8), B_4 (7:0)
SDIN2−Left C to Input Mixer 4 coefficient (default = 0)
U (31:28), C_4 (27:24), C_4 (23:16), C_4 (15:8), C_4 (7:0)
SDIN2−Right D to Input Mixer 4 coefficient (default = 0)
U (31:28), D_4 (27:24), D_4 (23:16), D_4 (15:8), D_4 (7:0)
0x48
32
SDIN3−Left E to Input Mixer 4 coefficient (default = 0)
U (31:28), E_4 (27:24), E_4 (23:16), E_4 (15:8), E_4 (7:0)
SDIN3−Right F to Input Mixer 4 coefficient (default = 0)
U (31:28), F_4 (27:24), F_4 (23:16), F_4 (15:8), F_4 (7:0)
SDIN4−Left G to Input Mixer 4 coefficient (default = 0)
U (31:28), G_4 (27:24), G_4 (23:16), G_4 (15:8), G_4 (7:0)
SDIN4−Right H to Input Mixer 4 coefficient (default = 1)
U (31:28), H_4 (27:24), H_4 (23:16), H_4 (15:8), H_4 (7:0)
71
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TAS5504
Serial Control Interface Register Definitions
6.16 Bass Management Registers (0x49–0x50)
Registers 0x49–0x50 provide configuration control for bass mangement.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper four bits not used.
Table 6−17. Bass Management Registers Format (0x49 – 0x50)
TOTAL
BYTES
REGISTER
NAME
SUBADDRESS
DESCRIPTION OF CONTENTS
DEFAULT STATE
0x49
4
4
4
4
4
4
ipmix_1_to_ch4
ipmix_2_to_ch4
Input Mixer 1 to Ch 4 Mixer coefficient (default = 0)
U (31:28), ipmix14 (27:24), ipmix14 (23:16), ipmix14 (15:8),
ipmix14 (7:0)
0x00, 0x00, 0x00, 0x00
0x4A
0x4B
0x4C
0x4D
0x4E
Input Mixer 2 to Ch 4 Mixer coefficient (default = 0)
U (31:28), ipmix24 (27:24), ipmix24 (23:16), ipmix24 (15:8),
ipmix24 (7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
ipmix_3_to_ch12 Input Mixer 3 to Ch 1 and Ch 2 Mixer coefficient (default = 0)
U (31:28), ipmix32 (27:24), ipmix32 (23:16), ipmix32 (15:8),
ipmix32 (7:0)
Ch3_bp_bq2
Ch 3 Biquad-2 By-pass coefficient (default = 0)
U (31:28), ch3_bp_bq2 (27:24), ch3_bp_bq2 (23:16),
ch3_bp_bq2 (15:8), ch3_bp_bq2 (7:0)
Ch3_bq2
Ch 3 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch3_bq2 (27:24), ch3_bq2 (23:16), ch3_bq2 (15:8),
ch3_bq2 (7:0)
ipmix_4_to_ch12 Ch 4 Biquad-2 Output to Ch1 Mixer and Ch2 Mixer coefficient
(default = 0)
U (31:28), ipmix4_12 (27:24), ipmix4_12 (23:16), ipmix4_12
(15:8), ipmix4_12 (7:0)
0x4F
0x50
4
4
Ch4_bp_bq2
Ch4_bq2
Ch 4 Biquad-2 By-pass coefficient (default = 0)
0U (31:28), ch4_bp_bq2 (27:24), ch4_bp_bq2 (23:16),
ch4_bp_bq2 (15:8), ch4_bp_bq2 (7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x80, 0x00, 0x00
Ch 4 Biquad-2 Inline coefficient (default = 1)
U (31:28), ch4_bq2 (27:24), ch4_bq2 (23:16), ch4_bq2 (15:8),
ch4_bq2 (7:0)
6.17 Biquad Filters Register (0x51 – 0x88)
Table 6−18. Biquad Filters Registers Format (0x51 – 0x88)
2
I C
TOTAL
BYTES
DEFAULT
STATE
REGISTER NAME
DESCRIPTION OF CONTENTS
SUBADDRESS
0x51–0x57
0x58–0x5E
0x7B–0x81
0x82–0x88
20/Reg.
20/Reg.
20/Reg.
20/Reg.
Ch1_bq[1] – [7]
Ch2_bq[1] – [7]
Ch3_bq[1] − [7]
Ch4_bq[1] − [7]
Ch 1 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 2 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 3 Biquads 1 – 7. See Table 6−19 for bit definition.
Ch 4 Biquads 1 – 7. See Table 6−19 for bit definition.
See Table 6−19
See Table 6−19
See Table 6−19
See Table 6−19
72
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SLES123 − October 2004
Serial Control Interface Register Definitions
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper four bits not used.
Table 6−19. Contents of One 20-Byte Biquad Filter Register Format (Default = All-pass)
DEFAULT GAIN COEFFICIENT VALUES
DESCRIPTION
b Coefficient
REGISTER FIELD CONTENTS
DECIMAL
1.0
HEX
U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)
U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0
b Coefficient
1
0.0
b Coefficient
2
0.0
a Coefficient
1
0.0
a Coefficient
2
0.0
6.18 Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 4)
Channels 1, 2, 3, and 4 are mapped into registers 0x89, 0x8A, 0x8F, and 0x90. Eight bytes are written for each
channel. Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is
written as a 32-bit word with the upper four bits not used.
Table 6−20. Bass and Treble Bypass Register Format (0x89−0x90)
REGISTER NAME TOTAL BYTES
CONTENTS
INITIALIZATION VALUE
Channel bass and
treble bypass
U 31:28), Bypass (27:24), Bypass (23:16), Bypass (15:8), Bypass (7:0) 0x00, 0x80, 0x00, 0x00
8
Channel bass and
U (31:28), Inline (27:24), Inline (23:16), Inline (15:8), Inline (7:0)
0x00, 0x00, 0x00, 0x00
treble inline
6.19 Loudness Registers (0x91 – 0x95)
Table 6−21. Loudness Registers Format (0x91 – 0x95)
2
I C
TOTAL
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
0x91
4
Loudness Log2 Gain (LG) U (31:28), LG (27:24), LG (23:16), LG (15:8), LG
(7:0)
0xFF, 0xC0, 0x00, 0x00
Loudness Log2 Offset
(LO)
U (31:24), U (23:16), LO (15:8), LO (7:0)
0x00, 0x00, 0x00, 0x00,
0x92
0x93
8
4
Loudness Log2 LO
Loudness Gain (G)
LO (31:24), LO (23:16), LO (15:8), LO (7:0)
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
U (31:28), G (27:24), G (23:16), G (15:8), G (7:0)
Loudness Offset Upper 16 U (31:24), U (23:16), O (15:8), O (7:0)
bits (O)
0x94
8
Loudness O Offset Lower
32 bits (O)
O (31:24), O (23:16), O (15:8), O (7:0)
0x00, 0x00, 0x00, 0x00,
Loudness Biquad (b0)
Loudness Biquad (b1)
Loudness Biquad (b2)
Loudness Biquad (a1)
Loudness Biquad (a2)
U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)
U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)
0x00, 0x00, 0xD5, 0x13,
0x00, 0x00, 0x00, 0x00,
0x0F, 0xFF, 0x2A, 0xED,
0x00, 0xFE, 0x50, 0x45,
0x0F, 0x81, 0xAA, 0x27
0x95
20
73
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TAS5504
Serial Control Interface Register Definitions
6.20 DRC1 Control (0x96, Channels 1−3)
Bits D31 – D14 are Don’t Care.
Table 6−22. DCR1 Control (0x96, Channels 1−3)
D31
D23
D15
D30
D22
D14
D29
D21
D28
D20
D27
D19
D26
D25
D24
FUNCTION
Unused bits
D18
D17
D16
FUNCTION
FUNCTION
Unused bits
D13
0
D12
0
D11
−
D10
−
D9
−
D8
−
Channel 1 (node j): No DRC
0
1
−
−
−
−
Channel 1 (node j): Pre-volume DRC
Channel 1 (node j): Post-volume DRC
Channel 1 (node j): No DRC
1
0
−
−
−
−
1
1
−
−
−
−
−
−
0
0
−
−
Channel 2 (node I): No DRC
−
−
0
1
−
−
Channel 2 (node I): Pre-volume DRC
Channel 2 (node I): Post-volume DRC
Channel 2 (node i): No DRC
−
−
1
0
−
−
−
−
1
1
−
−
D7
D6
D5
−
D4
−
D3
−
D2
−
D1
0
D0
0
FUNCTION
Channel 3 (node q): No DRC
−
−
−
−
0
1
Channel 3 (node q): Pre-volume DRC
Channel 3 (node q): Post-volume DRC
Channel 3 (node q): No DRC
−
−
−
−
1
0
−
−
−
−
1
1
6.21 DRC2 Control (0x97, Channel 4)
Table 6−23. DRC2 Control (0x97, Channel 4)
FUNCTION
D31 – D2
D1
0
D0
0
0
0
0
0
0
Channel 4 (node r): No DRC
0
0
0
0
1
Channel 4 (node r): Pre-volume DRC
Channel 4 (node r): Post-volume DRC
Channel 4 (node r): No DRC
1
0
1
1
74
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Serial Control Interface Register Definitions
6.22 DRC1 Data Registers (0x98 – 0x9C)
DRC1 applies to channels 1, 2, and 3.
Table 6−24. DRC1 Data Registers
2
I C
TOTAL
REGISTER NAME
Channel 1, 2, and 3
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
U (31:28), E (27:24), E (23:16), E (15:8), E (7:0) 0x00, 0x00, 0x88, 0x3F
DRC1 Energy
0x98
8
Channel 1, 2, and 3
U (31:28), 1−E (27:24), 1−E (23:16), 1−E (15:8), 0x00, 0x7F, 0x77, 0xC0
1−E (7:0)
DRC1 (1− Energy)
Channel 1, 2, and 3
DRC1 Threshold Upper 16 bits
(T1)
U (31:24), U (23:16), T1 (15:8), T1 (7:0)
T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)
U (31:24), U (23:16), T2 (15:8), T2 (7:0)
T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
Channel 1, 2, and 3
DRC1 Threshold Lower 32 bits
(T1)
0x99
16
Channel 1, 2, and 3
DRC1 Threshold
Upper 16 bits (T2)
Channel 1, 2, and 3
DRC1 Threshold
Lower 32 bits (T2)
Channel 1, 2, and 3
DRC1 slope (k0)
U (31:28), k0 (27:24), k0 (23:16), k0 (15:8),
k0 (7:0)
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
Channel 1, 2, and 3
DRC1 slope (k1)
U (31:28), k1 (27:24), k1 (23:16), k1 (15:8),
k1 (7:0)
0x9A
12
Channel 1, 2, and 3
DRC1 slope (k2)
U (31:28), k2 (27:24), k2 (23:16), k2 (15:8),
k2 (7:0)
Channel 1, 2, and 3
DRC1 Offset 1 Upper 16 bits
(O1)
U (31:24), U (23:16), O1 (15:8), O1 (7:0)
O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)
U (31:24), U (23:16), O2 (15:8), O2 (7:0)
O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)
Channel 1, 2, and 3
DRC1 Offset 1 Lower 32 bits
(O1)
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x9B
16
Channel 1, 2, and 3
DRC1 Offset 2 Upper 16 bits
(O2)
Channel 1, 2, and 3
DRC1 Offset 2 Lower 32 bits
(O2)
Channel 1, 2, and 3
DRC1 Attack
U (31:28), A (27:24), A (23:16), A (15:8), A (7:0) 0x00, 0x00, 0x88, 0x3F
Channel 1, 2, and 3
DRC1 (1− Attack)
U (31:28), 1−A (27:24), 1−A (23:16), 1−A (15:8), 0x00, 0x7F, 0x77, 0xC0
1−A (7:0)
0x9C
16
Channel 1, 2, and 3
DRC1 Decay
U (31:28), D (27:24), D (23:16), D (15:8), D (7:0) 0x00, 0x00, 0x00, 0x56
Channel 1, 2, and 3
DRC1 (1− Decay)
U (31:28), 1−D (27:24), 1−D (23:16), 1−D (15:8), 0x00, 0x3F, 0xFF, 0xA8
1−D (7:0)
75
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Serial Control Interface Register Definitions
6.23 DRC2 Data Registers (0x9D – 0xA1)
DRC2 applies to channel 4.
Table 6−25. DRC2 Data Registers
2
I C
TOTAL
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS BYTES
Channel 4 DRC2 Energy
U (31:28), E (27:24), E (23:16), E (15:8), E (7:0)
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x9D
0x9E
8
Channel 4 DRC2 (1− Energy)
U (31:28), 1−E (27:24), 1−E (23:16), 1−E (15:8),
1−E (7:0)
Channel 4 DRC2 Threshold
Upper 16 bits (T1)
U (31:24), U (23:16), T1 (15:8), T1 (7:0)
T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)
U (31:24), U (23:16), T2 (15:8), T2 (7:0)
T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF,
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
Channel 4 DRC2 Threshold
Lower 32 bits (T1)
16
Channel 4 DRC2 Threshold
Upper 16 bits (T2)
Channel 4 DRC2 Threshold
Lower 32 bits (T2)
Channel 4 DRC2 slope (k0)
Channel 4 DRC2 slope (k1)
Channel 4 DRC2 slope (k2)
U (31:28), k0 (27:24), k0 (23:16), k0 (15:8),
k0 (7:0)
U (31:28), k1 (27:24), k1 (23:16), k1 (15:8),
k1 (7:0)
0x9F
0xA0
0xA1
12
16
16
U (31:28), k2 (27:24), k2 (23:16), k2 (15:8),
k2 (7:0)
Channel 4 DRC2 Offset 1
Upper 16 bits (O1)
U (31:24), U (23:16), O1 (15:8), O1 (7:0)
O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)
U (31:24), U (23:16), O2 (15:8), O2 (7:0)
O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)
U (31:28), A (27:24), A (23:16), A (15:8), A (7:0)
Channel 4 DRC2 Offset 1
Lower 32 bits (O1)
Channel 4 DRC2 Offset 2
Upper 16 bits (O2)
Channel 4 DRC2 Offset 2
Lower 32 bits (O2)
Channel 4 DRC2 Attack
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
Channel 4 DRC2 (1− Attack)
U (31:28), 1−A (27:24), 1−A (23:16), 1−A (15:8),
1−A (7:0)
Channel 4 DRC2 Decay
U (31:28), D (27:24), D (23:16), D (15:8), D (7:0)
0x00, 0x00, 0x00, 0x56
0x00, 0x3F, 0xFF, 0xA8
Channel 4 DRC2 (1− Decay)
U (31:28), 1−D (27:24), 1−D (23:16), 1−D (15:8),
1−D (7:0)
76
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
6.24 DRC Bypass Registers (0xA2, 0xA3, 0xA8, 0xA9)
DRC bypass/inline for channels 1, 2, 3, and 4 are mapped into registers 0xA2, 0xA3, 0xA8, and 0xA9. 8−bytes
are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x00800000 is a gain of 1. Each
gain coefficient is written as a 32-bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x00000000 and inline = 0x00800000.
To disable DRC for a given channel, bypass = 0x00800000 and inline = 0x00000000.
Table 6−26. DRC Bypass Registers Format (0xA2−0xA9)
REGISTER NAME
TOTAL
BYTES
CONTENTS
INITIALIZATION
VALUE
Channel bass DRC bypass
Channel DRC inline
U (31:28), bypass (27:24), bypass (23:16), bypass (15:8), bypass (7:0) 0x00, 0x80, 0x00, 0x00
U (31:28), inline (27:24), inline (23:16), inline (15:8), inline (7:0) 0x00, 0x00, 0x00, 0x00
8
6.25 4x2 Output Mixer Registers (0xAA and 0xAB)
Output mixers for channels 1 and 2 map to registers 0xAA and 0xAB.
Total data per register is 8 bytes.
Table 6−27. Output Mixer Control Register Format (Upper 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
0
0
1
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
77
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
Table 6−28. Output Mixer Control (Lower 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
0
0
1
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
6.26 4x3 Output Mixer Registers (0xB0 – 0xB1)
Output mixers for channels 3 and 4 map to registers 0xB0 and 0xB1.
Total data per register is 12 bytes.
Table 6−29. Output Mixer Control (Upper 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
0
0
1
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
78
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
Table 6−30. Output Mixer Control (Middle 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
0
0
1
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
Table 6−31. Output Mixer Control (Lower 4 Bytes)
D31
0
D30
0
D29
0
D28
0
D27
D26
D25
D24
FUNCTION
Select channel 1 to output mixer
Select channel 2 to output mixer
Select channel 3 to output mixer
Select channel 4 to output mixer
0
0
0
1
0
1
1
0
0
1
1
1
G27
G26
G25
G24 Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16 Selected channel gain (continued)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
Selected channel gain (continued)
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Selected channel gain (lower 8 bits)
G7
G6
G5
G4
G3
G2
G1
G0
79
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.27 Volume Biquad Register (0xCF)
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper four bits not used.
Table 6−32. Volume Biquad Register Format (Default = All-pass)
DEFAULT GAIN COEFFICIENT VALUES
DESCRIPTION
b Coefficient
REGISTER FIELD CONTENTS
DECIMAL
1.0
HEX
0U (31:28), b0 (27:24), b0 (23:16), b0 (15:8), b0 (7:0)
U (31:28), b1 (27:24), b1 (23:16), b1 (15:8), b1 (7:0)
U (31:28), b2 (27:24), b2 (23:16), b2 (15:8), b2 (7:0)
0U (31:28), a1 (27:24), a1 (23:16), a1 (15:8), a1 (7:0)
U (31:28), a2 (27:24), a2 (23:16), a2 (15:8), a2 (7:0)
0x00, 0x80, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
o
b Coefficient
1
0.0
b Coefficient
2
0.0
a Coefficient
1
0.0
a Coefficient
2
0.0
6.28 Volume Treble and Bass Slew Rates (0xD0)
Table 6−33. Volume Gain Update Rate (Slew Rate)
FUNCTION
D31−D10
D9
0
D8
0
0
0
0
0
512 step update at 4 Fs, 42.6 ms at 48 kHz
1024 step update at 4 Fs, 85.3 ms at 48 kHz
2048 step update at 4 Fs, 170 ms at 48 kHz
2048 step update at 4 Fs, 170 ms at 48 kHz
0
1
1
0
1
1
Table 6−34. Treble and Bass Gain Step Size (Slew Rate)
D7
0
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
FUNCTION
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
No operation
0
0
0
1
1
0
0
1
0
0
Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz)
Update ever 0.67 ms (32 LRCLKs at 48 kHz)
0
0
0
0
0
0
1
1
1
1
Default rate − Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the
maximum constant time that can be set for all sample rates.
1
1
1
1
1
1
1
1
Minimum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)
6.29 Volume Registers (0xD1, 0xD2, 0xD7, and 0xD8)
Channels 1, 2, 3, and 4 are mapped into registers 0xD1, 0xD2, 0xD7, and 0xD8.
Master volume is mapped into register 0xD9.
Bits D31 − D12 are Don’t Care.
Table 6−35. Volume Registers
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
D15
D22
D14
D21
D13
D20
D12
D19
D18
D17
D16
FUNCTION
FUNCTION
FUNCTION
Unused bits
Volume
D11
V11
D10
V10
D9
V9
D8
V8
D7
V7
D6
V6
D5
V5
D4
V4
D3
V3
D2
V2
D1
V1
D0
V0
Volume
80
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
Table 6−36. Master and Individual Volume Controls
VOLUME INDEX (H)
GAIN/INDEX
17.75
17.5
EXPECTED
17.81
17.56
17.31
17.06
16.81
16.56
16.31
16.05
15.8
ACTUAL
17.81
17.56
17.31
17.06
16.81
16.56
16.31
16.05
15.8
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
044
045
046
047
048
049
04A
04B
04C
240
241
242
243
244
245
17.25
17
16.75
16.5
16.25
16
15.75
15.5
15.55
15.3
15.55
15.3
15.25
15
15.05
14.8
15.05
14.8
14.75
14.5
14.55
14.3
14.55
14.3
14.25
14
14.05
1
14.05
1
1
0.75
0.75
0.75
0.5
0.5
0.5
0.25
0.25
0.25
0
0
0
−0.25
−0.5
−0.75
−1
−0.25
−0.5
−0.25
−0.5
−0.75
−1
−0.75
−1
−126
−126.25
−126.5
−126.75
−127
Mute
TO
−126.43
−126.68
−126.93
−127.19
−127.44
Mute
−126.43
−126.99
−126.99
−127.59
−127.59
Mute
3FF
Mute
Mute
Mute
6.30 Bass Filter Set Register (0xDA)
Bits D31−D27, D23−D19, D15−D11, and D7−D3 are Don’t Care.
Table 6−37. Channel 4 Sub Woofer
D31
0
D30
0
D29
0
D28
0
D27
0
D26
0
D25
0
D24
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Illegal
81
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
Table 6−38. Channel 3, 2, 1 (Center, Right Front, and Left Front)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Bass filter set 1
Bass filter set 2
Bass filter set 3
Bass filter set 4
Bass filter set 5
Illegal
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Illegal
6.31 Bass Filter Index Register (0xDB)
Index values above 0x24 are invalid.
Table 6−39. Bass Filter Index Register
2
I C SUBADDRESS TOTAL BYTES
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
0xDB
Bass filter index
(BFI)
4
Ch4_BFI (31:24), NONE (23:16), NONE (15:8),
Ch321_BFI (7:0)
0x12, 0xxx, 0xxx, 0x12,
Table 6−40. Bass Filter Index Table
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
−16
−17
−18
+8
+7
+6
+5
+4
+3
+2
+1
0
82
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
6.32 Treble Filter Set Register (0xDC)
Bits D31−D27 are Don’t Care.
Table 6−41. Channel 4 Sub Woofer
D31
0
D30
0
D29
0
D28
0
D27
0
D26
0
D25
D24
FUNCTION
0
0
No change
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Illegal
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
Illegal
Table 6−42. Channel 3, 2, 1 (Center, Right Front, and Left Front)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No change
0
0
0
0
0
0
0
1
Treble filter set 1
Treble filter set 2
Treble filter set 3
Treble filter set 4
Treble filter set 5
Illegal
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Illegal
83
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
6.33 Treble Filter Index (0xDD)
Index values above 0x24 are invalid.
Table 6−43. Treble Filter Index Register
2
I C
REGISTER
NAME
TOTAL BYTES
DESCRIPTION OF CONTENTS
DEFAULT STATE
SUBADDRESS
0xDD
Treble filter index (TFI)
4
Ch4_TFI (31:24), NONE (23:16), NONE (15:8),
Ch321_TFI (7:0)
0x12,0x12,0x12,0x12
Table 6−44. Treble Filter Index
TREBLE INDEX VALUE
ADJUSTMENT (DB)
TREBLE INDEX VALUE
ADJUSTMENT (DB)
0x00
0x01
0x02
0x03
0x04
0x05
0x\06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
−16
−17
−18
+8
+7
+6
+5
+4
+3
+2
+1
0
6.34 AM Mode Register (0xDE)
Bits D31−D21 are Don’t Care.
Table 6−45. AM Mode Register
D31
D23
D30
D22
D29
D21
D28
D27
D26
D25
D24
FUNCTION
FUNCTION
Unused bits
D20
0
D19
−
D18
−
D17
−
D16
−
AM mode disabled
AM mode enabled
1
−
−
−
−
−
0
0
−
−
Select sequence 1
Select sequence 2
−
0
1
−
−
−
1
0
−
−
Select sequence 3
−
1
1
−
−
Select sequence 4
−
−
−
0
−
IF frequency 455
−
−
−
1
−
IF frequency 262.5
Use BCD tuned frequency
Use binary tuned frequency
−
−
−
−
0
−
−
−
−
1
84
TAS5504
SLES123 − October 2004
Serial Control Interface Register Definitions
Table 6−46. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)
D15
0
D14
0
D13
D12
B0
−
D11
D10
D9
D8
FUNCTION
0
−
−
−
−
BCD frequency (1000s kHz)
BCD frequency (100s kHz)
Default value
−
−
−
B3
0
B2
0
B1
0
B0
0
0
0
0
0
D7
B3
−
D6
B2
−
D5
B1
−
D4
B0
−
D3
−
D2
−
D1
−
D0
−
FUNCTION
BCD frequency (10s kHz)
BCD frequency (1s kHz)
Default value
B3
0
B2
0
B1
0
B0
0
0
0
0
0
Table 6−47. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)
D15
0
D14
0
D13
D12
D11
D10
B10
0
D9
B9
0
D8
B8
0
FUNCTION
0
0
0
Binary frequency (upper 3 bits)
0
0
0
0
0
Default value
D7
B7
0
D6
B6
0
D5
B5
0
D4
B4
0
D3
B3
0
D2
B2
0
D1
B1
0
D0
B0
0
FUNCTION
Binary frequency (lower 8 bits)
Default value
6.35 PSVC Range Register (0xDF)
Bits D31−D2 are zero.
Table 6−48. PSVC Range Register
D31 – D2
D1
0
D0
0
FUNCTION
0
0
0
0
12.04-dB control range for PSVC
0
1
18.06-dB control range for PSVC
24.08-dB control range for PSVC
Ignore − retain last value
1
0
1
1
6.36 General Control Register (0xE0)
Bits D31−D4 are zero. Bit D0 is Don’t Care.
Table 6−49. General Control Register
D31 – D4
D3
D2
0
D1
−
D0
−
FUNCTION
0
0
0
0
Power supply volume control disable
Power supply volume control enable
Subwoofer part of PSVC
1
−
−
0
−
−
−
1
−
−
−
Subwoofer separate from PSVC
6.37 Incremental Multiple Write Append Register (0xFE)
This is a special register used to append data to a previously opened register.
85
SLES123 − October 2004
TAS5504
Serial Control Interface Register Definitions
86
TAS5504
SLES123 − October 2004
TAS5504 Example Application Schematic
7
TAS5504 Example Application Schematic
The following page contains an example application schematic for the TAS5504.
87
SLES123 − October 2004
TAS5504
5
4
3
2
1
D
C
B
A
D
C
B
A
Left + Right Headphone
+5.0V
+5.0V
+3.3V
2
R20
22.0R
1
PWM_HPM_L
PWM_HPP_L
PWM_HPM_R
PWM_HPP_R
J900
C25
220nF
C26
10uF
V-HBRIDGE
4
3
2
1
OUT_R
GVDD
HEADPHONE OUTPUT
/SD2_TAS5121
/OTW_TAS5121
OUT_GND
OUT_L
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
Mini-Jack (3.5mm)
GND
2 Channel Headphone Design (TPA112)
PWM_P
PWM_M
/VALID
1
2
SUBWOOFER
SPEAKER
OUTPUT
OUT_1
OUT_2
/VALID
J800
CH4 TAS5121 H-Bridge Output Stage
V-HBRIDGE
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
MCLK
PWM_P
PWM_M
/VALID
1
2
CENTER
SPEAKER
OUTPUT
OUT_1
OUT_2
/VALID
J700
CH3 TAS5121 H-Bridge Output Stage
C29
100nF
C10
10nF
R10
200R
R11
200R
C13
10nF
C14
100nF
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VRA_PLL
VR_PWM
NC
C11
100nF
C12
100nF
2
PLL_FLT_RET
3
4
PLL_FLTM
PLL_FLTP
AVSS
NC
NC
5
NC
6
AVSS
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VAILD
7
VRD_PLL
AVSS_PLL
AVDD_PLL
VBGAP
RESET
HP_SEL
PDN
U10
+3.3V R12
8
2R
TAS5504
1
2
9
10
11
12
13
14
15
16
/VALID
/RESET_TAS5504
/HP_SEL
DVSS
C15
C16
C17
100nF
C18
100nF
10uF
1nF
/BKND_ERR_TAS5504
BKND_ERR
DVDD
+3.3V
/PDN_TAS5504
/MUTE_TAS5504
MUTE
DVSS
R13
R18
1R
3.30R
DVDD
DVSS
V-HBRIDGE
DVSS
VR_DIG
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GVDD
GND
+3.3V
C22
100nF
C23
10uF
C24
100nF
PWM_P
PWM_M
/VALID
R14
1
2
RIGHT
SPEAKER
OUTPUT
1R
OUT_1
OUT_2
/VALID
GND
J200
C19
C20
C21
CH2 TAS5121 H-Bridge Output Stage
10uF
100nF
100nF
V-HBRIDGE
GVDD
+5.0V +3.3V
V-HBRIDGE
GND
GVDD
/SD1_TAS5121
/OTW_TAS5121
/SHUTDOWN_TAS5121
/TEMP_WARNING
V-HBRIDGE
GND
PSVC_TAS5504
SDIN1
SDIN2
SDIN3
SDIN4
SCLK
GVDD
/RESET
/RESET
PWM_P
PWM_M
/VALID
X10
1
2
LEFT
SPEAKER
OUTPUT
/RESET_TAS5504
/RESET_TAS5504
OUT_1
OUT_2
/VALID
J100
13.5MHz
/BKND_ERR
/BKND_ERR
CH1 TAS5121 H-Bridge Output Stage
2
1
/BKND_ERR_TAS5504
/BKND_ERR_TAS5504
LRCLK
SCL
R21
1M
C27
15pF
C28
15pF
/SD1_TAS5121
/SD1
/SD1_TAS5121
/SD1
PSVC_TAS5504
SDA
PSVC_TAS5504
/SD2_TAS5121
/SD2
/SD2_TAS5121
/SD2
TAS5504 Example Application Schematic
/VALID
/VALID
/OTW_TAS5121
/OTW
/OTW_TAS5121
/OTW
(Circuit is Subject To Change Without Notice)
PSU and Interface Logic
5
4
3
2
1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
TAS5504PAG
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PAG
64
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5504PAGR
TQFP
PAG
64
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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