TAS5424TDKDRQ1 [TI]
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS; 四通道车载数字放大器
| 型号： | TAS5424TDKDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS |
| 文件： | 总41页 (文件大小：881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5414
TAS5424
www.ti.com
SLOS514–FEBRUARY 2007
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS
FEATURES
•
36-Pin PSOP3 (DKD) Power SOP Package
With Heat Slug Up for the TAS5414
•
•
•
•
•
TAS5414 – Single-Ended Input
•
44-Pin PSOP3 (DKD) Power SOP Package
With Heat Slug Up for the TAS5424
TAS5424 – Differential Input
Four-Channel Digital Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
•
•
•
•
Designed for Automotive EMC Requirements
Pb-Free Soldering Supported
Typical Output Power per Channel at 10%
THD+N
ISO9000:2002 TS16949 Certified
–40°C to 105°C Ambient Temperature Range
–
–
–
–
28 W/Ch Into 4 Ω at 14.4 Vdc
45 W/Ch Into 2 Ω at 14.4 Vdc
58 W/Ch Into 4 Ω at 21 Vdc
APPLICATIONS
•
High-power OEM/retail head units and
amplifier modules where feature densities and
system configurations require reduction in
heat from the audio power amplifier
116 W/Ch Into 2 Ω at 21 Vdc PBTL
•
Channels Can Be Paralleled (PBTL) for 1-Ω
Applications
•
•
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
DESCRIPTION
Patented Pop- and Click-Reduction
Technology
The TAS5414 and TAS5424 are four-channel digital
audio amplifiers designed for use in automotive head
units and external amplifier modules. The TAS5414
and TAS5424 provide four channels at 23 W
continuously into 4 Ω at less than 1% THD+N from a
14.4-V supply. Each channel can also deliver 38 W
into 2 Ω at 1% THD+N. The TAS5414 uses
single-ended analog inputs, while the TAS5424
employs differential inputs for increased immunity to
common-mode system noise. The digital PWM
topology of the TAS5414 and TAS5424 provides
dramatic improvements in efficiency over traditional
linear amplifier solutions. This reduces the power
dissipated by the amplifier by a factor of ten under
typical music playback conditions. High efficiency is
accomplished without the need for complicated
power-supply schemes. Multiple TAS5414s or
TAS5424s can be synchronized to meet
high-channel-count applications.
–
–
Soft Muting With Gain Ramp Control
Common-Mode Ramping
•
•
•
•
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
•
•
Configurable Channel Gains: 12-dB, 20-dB,
26-dB, 32-dB
Load Diagnostic Functions:
–
–
–
Output Open and Shorted Load
Output-to-Power and -to-Ground Shorts
Patented Tweeter Detection
•
Protection and Monitoring Functions:
–
–
–
Short-Circuit Protection
The TAS5414 and TAS5424 incorporate all the
functionality needed to perform in the demanding
OEM applications area. They have built-in load
diagnostic functions for detecting and diagnosing
misconnected outputs to help to reduce test time
during the manufacturing process.
Load-Dump Protection to 50 V
Fortuitous Open Ground and Power
Tolerant
–
Patented Output DC Level Detection While
Music Playing
–
–
–
Overtemperature Protection
Over- and Undervoltage Conditions
Clip Detection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS5414
TAS5424
www.ti.com
SLOS514–FEBRUARY 2007
TAS5414 FUNCTIONAL BLOCK DIAGRAM
3.3 V – 5 V
REXT
TAS5414-36 Pins
VREF and IREF
I2C ADDR
“0” – “3”
Supplies
and
References
D_BYP
A_BYP
AVDD (6.5 V)
DVDD (3.3 V)
SDA
SCL
I2C
SGND
GND
System
mP
OverTemp
Warn/SD
Channel
Utilities
FAULT
CLIP_OTW
Fault
and
Timing
Logic
CP
AVDD
Over/Under
Voltage
STANDBY
GND/SGND PGND
CPC_TOP
CPC_BOT
PVDD
Charge
Pump
Load Dump
OSC_SYNC
Osc
and
Clock
Battery
8 VDC – 22 VDC
CP
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Open/Short
Diagnostic
DC Detect
OC Timer
Optional
Radio DSP
PVDD
Signal Path
Clip Detect
Current
Limit
IN1_P
IN_M
OUT1_P
OUT1_M
Gate
Driver
PreAmp
PWM
PGND
Tweeter
Detect
Feedback
Channels 2, 3, 4: Same as Ch 1
B0198-01
2
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TAS5414
TAS5424
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SLOS514–FEBRUARY 2007
TAS5424 FUNCTIONAL BLOCK DIAGRAM
3.3 V – 5 V
REXT
TAS5414-36 Pins
VREF and IREF
I2C ADDR
“0” – “3”
Supplies
and
References
D_BYP
A_BYP
AVDD (6.5 V)
DVDD (3.3 V)
SDA
SCL
I2C
SGND
GND
System
mP
OverTemp
Warn/SD
Channel
Utilities
FAULT
CLIP_OTW
Fault
and
Timing
Logic
CP
AVDD
Over/Under
Voltage
STANDBY
GND/SGND PGND
CPC_TOP
CPC_BOT
PVDD
Charge
Pump
Load Dump
OSC_SYNC
Osc
and
Clock
Battery
8 VDC – 22 VDC
CP
Channel 1 of 4
MUTE
Load Diagnostics and Fault Monitors
Open/Short
Diagnostic
DC Detect
OC Timer
Optional
PVDD
Signal Path
Clip Detect
Current
Limit
IN1_P
IN1_M
OUT1_P
OUT1_M
Audio
Input
Gate
Driver
PreAmp
PWM
PGND
Tweeter
Detect
Feedback
Channels 2, 3, 4: Same as Ch 1
B0198-02
3
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TAS5414
TAS5424
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SLOS514–FEBRUARY 2007
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments for the TAS5414 and TAS5424 are shown as follows.
TAS5414
DKD PACKAGE
(TOP VIEW)
TAS5424
DKD PACKAGE
(TOP VIEW)
OSC_SYNC
PVDD
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OSC_SYNC
PVDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PVDD
2
I2C_ADDR
SDA
SCL
PVDD
2
I2C_ADDR
SDA
SCL
OUT1_M
OUT1_P
PGND
3
PVDD
3
4
OUT1_M
OUT1_P
PGND
4
FAULT
MUTE
5
FAULT
MUTE
GND
5
OUT2_M
OUT2_P
CPC_TOP
CP
6
6
STANDBY
7
PGND
7
8
D_BYP
CLIP_OTW
GND
OUT2_M
OUT2_P
CPC_TOP
CP
8
STANDBY
D_BYP
CLIP_OTW
GND
9
9
CPC_BOT
PGND
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
19
20
21
22
SGND
OUT3_M
OUT3_P
PGND
REXT
CP_BOT
PGND
SGND
A_BYP
IN1_P
REXT
A_BYP
IN1_P
OUT3_M
OUT3_P
PGND
IN2_P
OUT4_M
OUT4_P
PVDD
IN_M
IN1_M
IN3_P
IN4_P
PGND
IN2_P
IN2_M
IN3_P
IN3_M
PVDD
OUT4_M
OUT4_P
PVDD
P0018-03
PVDD
IN4_P
IN4_M
PVDD
P0055-01
4
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TAS5424
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SLOS514–FEBRUARY 2007
Table 1. TERMINAL FUNCTIONS
TERMINAL
TYPE(1)
PBY
DESCRIPTION
TAS5414
NO.
TAS5424
NO.
NAME
A_BYP
13
14
Bypass capacitor for the AVDD analog regulator
Open-drain CLIP, OTW, or logical OR of the CLIP and OTW outputs. It also
reports tweeter detection during tweeter mode.
CLIP_OTW
9
10
DO
CP
28
27
29
8
34
33
35
9
CP
CP
CP
PBY
DO
DG
AI
Top of main storage capacitor for charge pump (bottom goes to PVDD)
Bottom of flying capacitor for charge pump
Top of flying capacitor for charge pump
CPC_BOT
CPC_TOP
D_BYP
FAULT
GND
Bypass pin for DVDD regulator output
5
5
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
Ground
I2C address bit
10
2
7, 11
2
I2C_ADDR
IN1_M
IN1_P
N/A
14
N/A
15
N/A
17
N/A
18
16
6
16
15
18
17
20
19
22
21
N/A
6
AI
Inverting analog input for channel 1 (TAS5424 only)
Non-inverting analog input for channel 1
Inverting analog input for channel 2 (TAS5424 only)
Non-inverting analog input for channel 2
Inverting analog input for channel 3 (TAS5424 only)
Non-inverting analog input for channel 3
Inverting analog input for channel 4 (TAS5424 only)
Non-inverting analog input for channel 4
Signal return for the 4 analog channel inputs (TAS5414 only)
Gain ramp control: mute (low), play (high)
AI
IN2_M
IN2_P
AI
AI
IN3_M
IN3_P
AI
AI
IN4_M
IN4_P
AI
AI
IN_M
ARTN
AI
MUTE
Oscillator sync input from master or output to slave amplifiers (20 MHz divided by
5, 6, or 7)
OSC_SYNC
1
1
DI/DO
OUT1_M
OUT1_P
OUT2_M
OUT2_P
OUT3_M
OUT3_P
OUT4_M
OUT4_P
34
33
31
30
25
24
22
21
41
40
37
36
31
30
27
26
PO
PO
PO
PO
PO
PO
PO
PO
– polarity output for bridge 1
+ polarity output for bridge 1
– polarity output for bridge 2
+ polarity output for bridge 2
– polarity output for bridge 3
+ polarity output for bridge 3
– polarity output for bridge 4
+ polarity output for bridge 4
28, 29, 32,
38, 39
PGND
PVDD
23, 26, 32
PGND
PWR
Power GND
19, 20, 35, 23, 24, 25,
PVDD supply
36
12
4
42, 43, 44
REXT
SCL
13
4
AI
DI
Precision resistor pin to set clock frequency
I2C clock input from system I2C master
SDA
3
3
DI/DO
AG/DG
DI
I2C data I/O for communication with system I2C master
Signal ground (analog and digital signal ground)
Active-low STANDBY pin. Standby (low), power up (high)
SGND
STANDBY
11
7
12
8
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PGND = power ground,
PBY = power bypass, PO = power output, AG = analog ground, DG = digital ground, CP = charge pump.
5
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TAS5424
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SLOS514–FEBRUARY 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
PVDD
DC supply voltage range
Relative to PGND
–0.3 to 30
–1 to 50
25
V
V
PVDDMAX
PVDDRAMP
IPVDD
Pulsed supply voltage range
t ≤ 100 ms exposure
Supply voltage ramp rate
Voltage rising up to PVDDMAX
V/ms
A
Externally imposed dc supply current per PVDD or PGND pin
Pulsed supply current per PVDD pin (one shot)
Maximum allowed dc current per output pin
Pulsed output current per output pin (single pulse)
Maximum current, all digital and analog input pins(2)
Maximum current on MUTE pin
±12
IPVDD_MAX
IO
t < 100 ms
17
A
± 13.5
±17
A
(1)
IO_MAX
t < 100 ms
A
IIN_MAX
DC or pulsed
DC or pulsed
±1
mA
mA
mA
IMUTE_MAX
IIN_ODMAX
±20
Maximum sinking current for open-drain pins
7
Input voltage range for logic pin relative to SGND (SCL and
SDA pins)
Supply voltage range:
6.5 V < PVDD < 24 V
VLOGIC
–0.3 to 7
–0.3 to 7
–0.3 to 5.8
–0.3 to 3.6
6.5
V
V
Supply voltage range:
6.5 V < PVDD < 24 V
VI2C_ADDR
VSTANDBY
VOSC_SYNC
VAIN_MAX
Input voltage range for I2C_ADDR pin relative to SGND
Input voltage range for STANDBY pin
Supply voltage range:
6.5 V < PVDD < 24V
V
Supply voltage range:
6.5 V < PVDD < 24 V
Input voltage range for OSC_SYNC pin relative to SGND
V
Maximum instantaneous input voltage (per pin), analog input Supply voltage range:
pins
V
6.5 V < PVDD < 24 V
Maximum ac coupled input voltage for TAS5414(2), analog
input pins
Supply voltage range:
6.5 V < PVDD < 24 V
VAIN_AC_MAX_5414
1.9
Vrms
3.8
(1.9 per
pin)
Maximum ac coupled differential input voltage for TAS5424(2)
analog input pins
,
Supply voltage range:
6.5 V < PVDD < 24 V
VAIN_AC_MAX_5424
Vrms
V
Supply voltage range:
6.5 V < PVDD < 24 V
VAIN_DC
Input voltage range for analog pin relative to AGND (INx pins)
–0.3 to 6.5
TJ
Maximum operating junction temperature range
Storage temperature range
–55 to 150
–55 to 150
°C
°C
Tstg
Lead temperature during soldering 1,6 mm (1/16 inch) from
case for 10 seconds
TSOLDER
260
80
°C
Power dissipation Continuous power dissipation
Tcase = 70°C
W
(1) Pulsed current ratings are maximum survivable currents externally applied to the TAS5414 and TAS5424. High currents may be
encountered during reverse battery, fortuitous open ground, and fortuitous open supply fault conditions.
(2) See Application Information section for information on analog input voltage and ac coupling.
THERMAL CHARACTERISTICS
PARAMETER
VALUE
UNIT
Junction-to-case (heat slug) thermal
resistance
RθJC
RθJA
1
°C/W
This device is not intended to be used without a heatsink. Therefore, RθJA
is not specified. See the Thermal Information section.
Junction-to-ambient thermal resistance
°C/W
6
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TAS5414
TAS5424
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SLOS514–FEBRUARY 2007
RECOMMENDED OPERATING CONDITIONS(1)
MIN
8
TYP
14.4
14.4
MAX
22
UNIT
V
PVDDOP
PVDDI2C
VAIN_5414
DC supply voltage range relative to PGND
DC supply voltage range for I2C reporting
Analog audio input signal level (TAS5414)
Analog audio input signal level (TAS5424)
Audio frequency for tweeter detect
Ambient temperature
6
26.5
V
(2)
(2)
AC-coupled input voltage
AC-coupled input voltage
0
0.25–1(3)
0.5–2(3)
25
Vrms
Vrms
kHz
°C
0
VAIN_5424
fAUDIO_TW
TA
10
–40
20
105
An adequate heat sink is required
to keep TJ within specified range
TJ
Junction temperature
–40
115
°C
RL
Nominal speaker load impedance
2
3
4
Ω
VPU
Pullup voltage supply (for open-drain logic outputs)
3.3 or 5
5.5
100
10
V
Resistor connected between
open-drain logic output and VPU
supply
RPU_EXT
RPU_I2C
External pullup resistor on open-drain logic outputs
I2C pullup resistance on SDA and SCL pins
10
1
50
5
kΩ
kΩ
Total resistance of voltage divider for I2C address
slave 1 or slave 2, connected between D_BYP and
SGND pins
RI2C_ADD
10
100
kΩ
RREXT
External resistance on REXT pin
External capacitance on D_BYP pin
External capacitance on A_BYP pin
1% tolerance required
19.8
10
20
1
20.2
120
120
kΩ
nF
nF
CD_BYP
CA_BYP
10
External capacitance to analog input pin in series
with input signal
CIN
µF
CFLY
Flying capacitor on charge pump
Charge pump capacitor
0.47
0.47
3.3
1
1
1.5
1.5
µF
µF
nF
pF
CP
CMUTE
Capacitance on MUTE pin
330
5
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
(1) The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical
Characteristics table for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.
7
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TAS5424
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SLOS514–FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPERATING CURRENT
IPVDD_IDLE
All four channels running in MUTE mode
All four channels in Hi-Z mode
STANDBY mode, TJ ≤ 85°C
240
80
2
300
mA
PVDD idle current
IPVDD_Hi-Z
IPVDD_STBY
PVDD standby current
20
µA
OUTPUT POWER
4 Ω, PVDD = 14.4V, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4V, square wave, 1 kHz, Tc = 75°C
4 Ω, PVDD = 21 V, THD+N = 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 21 V, THD+N = 10%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4V, THD+N = 1%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4V, THD+N = 10%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, square wave 1 kHz, Tc = 75°C
23
28
43
47
58
38
45
70
25
50
40
POUT
Output power per channel
W
PBTL 2-Ω operation, PVDD = 21 V, THD+N = 10%,
1 kHz, Tc = 75°C
116
90
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, Tc = 75°C
4 channels operating, 23W output power/ch, L = 10 µH,
TJ ≤ 85°C
EFFP
Power efficiency
90%
AUDIO PERFORMANCE
VNOISE
Noise voltage at output
G = 26 dB, zero input, AES17 filter, and A-weighting
1W, G = 26 dB, 1 kHz
60
75
100
µV
dB
dB
dB
Crosstalk
CMRR5424
PSRR
Channel crosstalk
60
60
60
Common-mode rejection ratio (TAS5424)
Power supply rejection ratio
Total harmonic distortion + noise
1 kHz, 1 Vrms referenced to SGND, G = 26 dB
G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P = 1 W, G = 26 dB, f = 1 kHz, 0°C ≤ TJ ≤ 75°C
75
75
THD+N
0.02%
357
417
500
80
0.1%
378
442
530
100
336
392
470
60
Switching frequency selectable for AM interference
avoidance
fS
Switching frequency
kHz
RAIN
Analog input resistance
Internal shunt resistance on each input pin
kΩ
AC-coupled common-mode input voltage (zero
differential input)
VIN_CM
VCM_INT
Common-mode input voltage (non-clipping)
Internal common-mode input bias voltage
1.3 Vrms
Internal bias applied to IN_M pin
3.25
12
20
26
32
0
V
11
19
25
31
–1
13
21
dB
27
G
Voltage gain (VO/VIN
)
Source impedance = 0 Ω
33
GCH
tCM
Channel-to-channel variation
Output-voltage common-mode ramping time
Gain ramping time
Any gain commanded
1
dB
ms
ms
35
30
tGAIN
External CMUTE = 330 nF
PWM OUTPUT STAGE
RDSon
FET Drain-to-source resistance
Output offset voltage
Not including bond wire resistance, TJ = 25°C
75
95
mΩ
VO_OFFSET
Zero input signal and G = 26 dB
±10
±25
mV
PVDD OVER VOLTAGE (OV) PROTECTION
VOV PVDD over voltage shutdown
LOAD DUMP (LD) PROTECTION
22.1
23.7
26.3
V
VLD_SD_SET
Load-dump shutdown voltage
Recovery voltage for load-dump shutdown
26.6
23.5
29
32
V
V
VLD_SD_CLEAR
26.4
28.4
PVDD UNDER VOLTAGE (UV) PROTECTION
VUV_SET
PVDD under voltage shutdown
Recovery voltage for PVDD UV
6.5
7
7
7.5
8
V
V
VUV_CLEAR
7.5
8
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TAS5424
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SLOS514–FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AVDD
VA_BYP
A_BYP pin voltage
A_BYP UV voltage
6.5
4.8
5.3
V
V
V
VA_BYP_UV_SET
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV
DVDD
VD_BYP
D_BYP pin voltage
3.3
V
POWER-ON RESET (POR)
Maximum PVDD voltage for POR; I2C
active above this voltage
VPOR
6
V
V
VPOR_HY
REXT
PVDD recovery hysteresis voltage for POR
0.1
VREXT
Rext pin voltage
1.24
V
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
Recovery voltage for CP UV
4.8
5.2
V
V
VCPUV_CLEAR
OVERTEMPERATURE (OV) PROTECTION
TOTW1_CLEAR
102
112
115
125
128
138
TOTW1_SET
/
TOTW2_CLEAR
Junction temperature for overtemperature
warning
TOTW2_SET
/
122
132
142
135
145
155
148
158
168
TOTW3_CLEAR
°C
TOTW3_SET
/
TOTWD_CLEAR
Junction temperature for overtemperature
shutdown
TOTSD
CURRENT LIMITING PROTECTION
ILIM1 Current limit 1 (load current)
Load < 4 Ω
Load < 2 Ω
5.5
8.5
7.3
11
9
A
A
Current limit 2 (load current), I2C setting
current limit level 2
ILIM2
13.5
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX1
IMAX2
TWEETER DETECT
Maximum current 1 (peak output current)
9.5
11.3
14.3
13
17
A
A
Any short to supply, ground, or other channels
Maximum current 2 (peak output current)
11.5
ITH_TW
Load current threshold for tweeter detect
325
540
2
750
mA
A
ILIM_TW
Load current limit for tweeter detect
STANDBY MODE
VIH_STBY
STANDBY input voltage for logic-level high
STANDBY input voltage for logic-level low
STANDBY pin current
2
0
5.5
0.7
0.2
V
V
VIL_STBY
ISTBY_PIN
0.1
85
µA
MUTE MODE
GMUTE
Output attenuation
MUTE pin ≤ 0.9Vdc, VIN = 1 Vrms on all inputs
dB
DC DETECT
VTH_DCD_POS
VTH_DCD_NEG
DC detect positive threshold default value
DC detect negative threshold default value
PVDD = 14.4 Vdc, register 0x0E = 8EH
PVDD = 14.4 Vdc, register 0x0F = 3DH
6.5
V
V
–6.5
DC detect step response time for four
channels
tDCD
4.3
0.5
s
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
VOH_CLIPOTW
2.4
V
V
high (open-drain logic output)
External 47-kΩ pullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
VOL_CLIPOTW
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Rext = 20 kΩ, master mode
operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CLIP_OTW signal delay when output
clipping detected
tDELAY_CLIPDET
FAULT REPORT
VOH_FAULT
20
µs
FAULT pin output voltage for logic-level
high (open-drain logic output)
2.4
External 47-kΩ pullup resistor to 3 V–5.5 V
V
FAULT pin output voltage for logic-level low
(open-drain logic output)
VOL_FAULT
0.5
OPEN/SHORT DIAGNOSTICS
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
RS2P, RS2G
200
1300
1.5
Ω
Ω
Ω
Minimum load resistance to detect open
circuit
ROPEN_LOAD
RSHORTED_LOAD
Including speaker wires
Including speaker wires
300
0.5
800
1
Maximum load resistance to detect short
circuit
I2C ADDRESS DECODER
Time delay to latch I2C address after POR
Voltage on I2C_ADDR pin for address 0
Voltage on I2C_ADDR pin for address 1
Voltage on I2C_ADDR pin for address 2
Voltage on I2C_ADDR pin for address 3
tLATCH_I2CADDR
300
0%
µs
Connect to SGND
0%
25%
55%
85%
15%
45%
35%
65%
100%
External resistors in series between D_BYP and SGND
as a voltage divider
VI2C_ADDR
VD_BYP
75%
Connect to D_BYP
100%
I2C
Power-on hold time before I2C
communication
tHOLD_I2C
STANDBY high
1
ms
fSCL
SCL clock frequency
100
5.5
1.1
kHz
V
VIH_SCL
VIL_SCL
SCL pin input voltage for logic-level high
SCL pin input voltage for logic-level low
2.1
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
–0.5
V
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOH_SDA
VOL_SDA
VIH_SDA
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
SDA pin input voltage for logic-level high
2.4
0
V
V
V
I2C read, 3-mA sink current
0.4
5.5
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
2.1
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIL_SDA
SDA pin input voltage for logic-level low
Capacitance for SCL and SDA pins
–0.5
1.1
10
V
Ci
pF
OSCILLATOR
OSC_SYNC pin output voltage for
logic-level high
VOH_OSCSYNC
VOL_OSCSYNC
VIH_OSCSYNC
VIL_OSCSYNC
2.4
2
3.6
0.5
V
V
V
V
I2C_ADDR pin set to MASTER mode
I2C_ADDR pin set to SLAVE mode
OSC_SYNC pin output voltage for
logic-level low
OSC_SYNC pin input voltage for logic-level
high
3.6
OSC_SYNC pin input voltage for logic-level
low
0.8
I2C_ADDR pin set to MASTER mode, fS = 500 kHz,
maximum capacitive loading = 5 pF
3.76
3.13
2.68
4.0
3.33
2.85
4.24
3.63
3.0
I2C_ADDR pin set to MASTER mode, fS = 417 kHz,
maximum capacitive loading = 5 pF
fOSC_SYNC
OSC_SYNC pin clock frequency
MHz
I2C_ADDR pin set to MASTER mode, fS = 357 kHz,
maximum capacitive loading = 5 pF
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TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
1000
300
UNIT
ns
tr
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
ns
tw(H)
tw(L)
tsu2
th2
4
4.7
4.7
4
µs
SCL pulse duration, low
µs
Setup time for START condition
START condition hold time after which first clock pulse is generated
Data setup time
µs
µs
tsu1
th1
250
0(1)
4
ns
Data hold time
ns
tsu3
CB
Setup time for STOP condition
Load capacitance for each bus line
µs
400
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
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TYPICAL CHARACTERISTICS
THD+N vs POWER at 1kHz
THD+N vs FREQUENCY at 1 Watt
100
10
10
1
1
0.1
21 VDC, 4 Ω
14.4 VDC, 2 Ω
14.4 VDC, 4 Ω
14.4 VDC, 4 Ω
14.4 VDC, 2 Ω
0.1
0.01
0.01
21 VDC, 4 Ω
21 VDC, 2 Ω, PBTL
10 100 200
0.001
10
0.1
1
100
1k
10k 20k
P
O
− Output Power − W
f − Frequency − Hz
G001
G002
Figure 3.
Figure 4.
COMMON-MODE REJECTION RATIO (TAS5424)
CROSSTALK
0
−20
−30
−40
−50
−60
−70
−80
−90
−40
−60
−80
−100
−120
−140
10
100
1k
10k 20k
10
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G004
G003
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
IMD SMPTE 19 kHz, 20 kHz 1:1
NOISE FFT
−60
−70
0
−20
−80
−40
−90
−60
−100
−110
−120
−80
−100
−120
10
100
1k
10k
30k
10
100
1k
10k
30k
f − Frequency − Hz
f − Frequency − Hz
G005
G006
Figure 7.
Figure 8.
EFFICIENCY,
FOUR CHANNELS AT 4 Ω EACH
DEVICE POWER DISSIPATION
FOUR CHANNELS INTO 4 Ω
100
90
80
70
60
50
40
30
20
10
12
10
8
6
4
2
0
0
0
4
8
12
16
20
24
28
32
0
5
10
15
20
P − Power Per Channel − W
P − Power Per Channel − W
G007
G008
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
DC DETECT VOLTAGE
vs
REGISTER 0E VALUES
20
18
16
14
12
10
8
PVDD = 20 V
PVDD = 14.4 V
PVDD = 8 V
6
4
2
0
65 6a 6f 74 79 7e 83 88 8d 92 97 9c a1 a6 ab b0 b5 ba bf c4 c9
Register 0E − Hex
G009
Figure 11.
DC DETECT VOLTAGE
vs
REGISTER 0F VALUES
0
−2
−4
PVDD = 8 V
−6
−8
PVDD = 14.4 V
−10
−12
−14
−16
−18
−20
PVDD = 20 V
00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b 50 55 5a 5f 64
Register 0F − Hex
G010
Figure 12.
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DESCRIPTION OF OPERATION
OVERVIEW
The TAS5414 and TAS5424 are single-chip, four-channel, analog-input audio amplifiers for use in the
automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments,
but with changes needed by the automotive industry. This technology allows for reduced power consumption,
reduced heat, and reduced peak currents in the electrical system. The TAS5414 and TAS5424 realize an audio
sound system design with smaller size and lower weight than traditional class-AB solutions.
The TAS5414 and TAS5424 are composed of eight elements:
•
•
•
•
•
•
•
•
Preamplifier
PWM
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
Preamplifier
The preamplifier of the TAS5414 and TAS5424 is a high-input-impedance, low-noise, low-offset-voltage input
stage with adjustable gain. The high input impedance of the TAS5414 and TAS5424 allows the use of low-cost
1-µF input capacitors while still achieving extended low-frequency response. The preamplifier is powered by a
dedicated, internally regulated supply, which gives it excellent noise immunity and channel separation. Also
included in the preamp are:
1. Mute Pop-and-Click Control—An audio input signal is reshaped and amplified as a step when a mute is
applied at the crest or trough of the signal. Such a step is perceived as a loud click. This is avoided in the
TAS5414 and TAS5424 by ramping the gain gradually when a mute or play command is received.
Another form of click and pop can be caused by the start or stopping of switching in a class-D amplifier.
The TAS5414 and TAS5424 incorporate a patented method to reduce the pop energy during the
switching startup and shutdown sequence. Fault conditions require rapid protection response by the
TAS5414 and the TAS5424, which do not have time to ramp the gain down in a pop-free manner. The
device transitions into Hi-Z mode when an OV, UV, OC, OT, or DC fault is encountered. Also, activation
of the STANDBY pin may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. The gain is set
outside of the global feedback resistors of the TAS5414 and the TAS5424, thus allowing for stability in the
system under all load conditions and gain settings.
3. DC Offset Reduction Circuitry—Circuitry has been incorporated to reduce the dc offset. DC offset in
high-gain amplifiers can produce audible clicks and pops when the amplifier is started or stopped. The
offset reduction circuitry can be disabled or enabled via I2C.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5414 and TAS5424, the modulator is an
advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation
capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of
PWMs when the input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power
FET stage. The TAS5414 and TAS5424 use patent-pending techniques to avoid shoot-through and are
optimized for EMI and audio performance.
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DESCRIPTION OF OPERATION (continued)
Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSon of
75 mΩ for high efficiency and maximum power transfer to the load. These FETs are designed to handle large
voltage transients during load dump.
Load Diagnostics
The TAS5414 and TAS5424 incorporate load diagnostic circuitry designed to help pinpoint the nature of output
misconnections during installation. The TAS5414 and the TAS5424 include functions for detecting and
determining the status of output connections. The following diagnostics are supported:
•
•
•
•
•
Short to GND
Short to PVDD
Short across load (R < 1 Ω, typical)
Open load (R > 800 Ω, typical)
Tweeter detection
The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter
detect status can be read from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The TAS5414 and TAS5424 contain circuitry designed to detect
shorts and open conditions on the outputs. The load diagnostic function can only be invoked when the
output is in the Hi-Z mode. There are four phases of test during load diagnostics and two levels of test. In
the full level, all channels must be in the Hi-Z state. All four phases are tested on each channel, all four
channels at the same time. When fewer than four channels are in Hi-Z, the reduced level of test is the
only available option. In the reduced level, only short to PVDD and short to GND can be tested. Load
diagnostics can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is
already in play mode, it must Mute and then Hi-Z before the load diagnostic can be performed. By
performing the mute function, the normal pop- and click-free transitions occur before the diagnostics
begin. The diagnostics are performed as shown in Figure 13. Figure 14 shows the impedance ranges for
the open-load and shorted-load diagnostics. The results of the diagnostic are read from the diagnostic
register for each channel via I2C. Note: Do not send a command via I2C to register 0x0C during the load
diagnostic test.
Hi-Z Channel Synchronization
Playback
/
Mute
Phase1
S2G
Phase2
S2P
Phase3
OL
Phase4
SL
OUT1P
OUT1M
~50 ms
~50 ms
~50 ms
~50 ms
~50 ms
~50 ms
~50 ms
~50 ms
VSpeaker
(OUT1M–OUT1P)
100 ms
100 ms
150 ms
150 ms
<100 ms
T0188-01
Figure 13. Load Diagnostics Sequence of Events
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DESCRIPTION OF OPERATION (continued)
Short Detection
Range
Open Detection
Range
Short Detected
Normal Load Detected
Open Detected
RLoad
(Including Wires)
1.5
300
1300
0.5
1 (Typ)
800 (Typ)
M0067-01
Figure 14. Open and Shorted Load Detection
2. Tweeter Detection—The tweeter detection function is an ac diagnostic used to determine proper
connection of the tweeter when a passive crossover is used. The proper implementation of this diagnostic
function is dependent on the amplitude of a user-supplied test signal and on the impedance vs frequency
curve of the acoustic package. The tweeter function is invoked via I2C, and all four channels should be
tested individually. The tweeter detection uses the average cycle-by-cycle current limit circuit (see CBC
section) to measure the current to the load. The current level for the tweeter detection threshold is
typically 550 mA. The system (external to the TAS5414 and TAS5424) must generate a tone burst in the
10-kHz to 25-kHz range. If the tone burst employs a frequency higher than 20 kHz, and if a sufficiently
smooth amplitude ramp is used, the tweeter detection signal is silent. The frequency and amplitude of this
tone burst must be calibrated by the user to result in a current draw greater than the selected threshold
level when the tweeter is present. The tweeter detection results are monitored on the CLIP_OTW pin
during the application of the test tone. If the current threshold is attained during measurement, the tweeter
is present; then the CLIP_OTW pin is asserted. When the tweeter detector is activated, pulses on the
CLIP_OTW pin begin to toggle at 250 kHz to 500 kHz. As the detection signal gets stronger due to higher
load current, the density (or duty cycle) of the pulses increases.
Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to
limit the output current flow when the average current limit (ILIM) threshold is exceeded. The overall effect
on the audio in the case of a current overload is quite similar to a voltage-clipping event, where power is
temporarily limited at the peaks of the musical signal and normal operation continues without disruption
when the overload is removed. The TAS5414 and TAS5424 do not prematurely shut down in this
condition. All four channels continue in play mode and pass signal.
2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground,
a peak-current detector is used, and the affected channel shuts down in 200 µs to 390 µs if the conditions
are severe enough. The shutdown speed depends on a number of factors, such as the impedance of the
short circuit, supply voltage, and switching frequency. Only the shorted channels are shut down in such a
scenario. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and
the affected channel(s) are recorded in the I2C fault register. If the supply or ground short is strong
enough to exceed the peak current threshold but not severe enough to trigger the OCSD, the peak
current limiter prevents excess current from damaging the output FETs, and operation returns to normal
after the short is removed.
3. DC Detect—This circuit detects a dc offset continously during normal operation at the output of the
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DESCRIPTION OF OPERATION (continued)
amplifier. If the dc offset reaches the level defined in the I2C registers for the specified time period, the
circuit triggers. By default a dc detection event does not shut the output down. The shutdown function can
be enabled or disabled via I2C. If enabled, the triggered channel shuts down, but the others remain
playing and the FAULT pin is asserted. The positive dc level and negative dc level are defined in I2C
registers and can have separate thresholds.
4. Clip Detect—The clip detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, a signal is passed to the CLIP_OTW pin and it is asserted until the
100% duty-cycle PWM signal is no longer present. All four channels are connected to the same
CLIP_OTW pin. Through I2C, the CLIP_OTW signal can be changed to clip-only, OTW-only, or both. A
fourth mode, used only during diagnostics, is the option to report tweeter detection events on this pin (see
the Tweeter Detection section). The microcontroller in the system can monitor the signal at the
CLIP_OTW pin and may be configured to reduce the volume to all four channels in an active
clipping-prevention circuit.
5. Overtemperature Warning (OTW) and Overtemperature Shutdown (OTSD)—By default, the
CLIP_OTW pin is set to indicate an OTW. This can be changed via I2C commands. If selected to indicate
a temperature warning, the CLIP_OTW pin is asserted when the die temperature reaches 125°C. The
OTW has three temperature thresholds with a 10°C hysteresis. Each threshold is indicated in I2C register
0x04 bits 5, 6, and 7. The TAS5414 and TAS5424 still function until the temperature reaches the OTSD
threshold. 155°C, at which time the outputs are placed into Hi-Z mode and the FAULT pin is asserted. I2C
is still active in the event of an OTSD and the registers can be read for faults, but all audio ceases
abruptly. The OTSD resets at 145°C, to allow the TAS5414/5424 to be turned back on through I2C. The
OTW is still indicated until the temperature drops below 115°C. All temperatures are nominal values.
6. Undervoltage (UV) and Power-on-Reset (POR)—The undervoltage (UV) protection detects low voltages
on PVDD, AVDD, and CP. In the event of an undervoltage, the FAULT pin is asserted and the I2C
register is updated, depending on which voltage caused the event. Power-on-reset (POR) occurs when
PVDD drops low enough. A POR event causes the I2C to go into a high-impedance state. After the device
recovers from the POR event, the device must be re-initialized via I2C.
7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD
reaches the overvoltage threshold, the FAULT pin is asserted and the I2C register is updated. If the
voltage increases beyond the load dump threshold of 29 Vdc, the device shuts down and must be
restarted once the voltage returns to a safe value. After the device recovers from the ≈ load dump event,
the device must be re-initialized via I2C. The TAS5414 and TAS5424 can withstand 50-V load-dump
voltage spikes (see Figure 15). Also depicted in this graph are the voltage thresholds for normal operation
region, overvoltage operation region, and load-dump protection region. Figure 13 shows the regions of
operating voltage and the profile of the load dump event. Battery charger voltages from 25 V to 35 V can
be withstood for up to 1 hour.
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DESCRIPTION OF OPERATION (continued)
PVDD
50 V
100 ms
Max
50 V
Max Ramp Rate
25 V/ms
Load Dump Protection
29 V–50 V
I2C Stop
Standby Mode
POR
I2C Start
29 V
26 V
Overvoltage Protection Region
23 V–29 V
23 V
22 V
Hi-Z All Ch’s
14.4 V
Normal Operating Region
8 V–22 V
Ready to Get
Off Hi-Z State
Time
T0189-01
Figure 15. Voltage Operating Regions With Load Dump Transition Defined
Power Supply
The power for the device is most commonly provided by a car battery that can have a large voltage swing, 8 Vdc
to 18 Vdc. PVDD is a filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate
driver. The high-side FET gate driver is supplied by a charge pump (CP) supply. The charge pump supplies the
gate drive voltage for all four channels. The analog circuitry is powered by AVDD, which is a provided by an
internal linear regulator. A 0.1µF/10V external bypass capacitor is needed at the A_BYP pin for this supply. It is
recommended that no external components except the bypass capacitor be attached to this pin. The digital
circuitry is powered by DVDD, which is provided by an internal linear regulator. A 0.1µF/10V external bypass
capacitor is needed at the D_BYP pin. It is recommended that no external components except the bypass
capacitor be attached to this pin.
The TAS5414 and TAS5424 can withstand fortuitous open ground and power conditions. Fortuitous open
ground usually occurs when a speaker wire is shorted to ground, allowing for a second ground path through the
body diode in the output FETs. The uniqueness of the diagnostic capabilities allows the speakers and speaker
wires to be debugged, eliminating the need to remove the amplifier to diagnose the problem.
I2C Serial Communication Bus
The TAS5414 and TAS5424 communicate with the system processor via the I2C serial communication bus. The
TAS5414 and TAS5424 are I2C slave-only devices. The processor can poll the TAS5414 and the TAS5424 via
I2C to determine the operating status of the device. All fault conditions and detections are reported via I2C.
There are also numerous features and operating conditions that can be set via I2C.
The I2C bus allows control of the following configurations:
•
Independent gain control of each channel. The gain can be set to 12 dB, 20 dB, 26 dB, and 32 dB.
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DESCRIPTION OF OPERATION (continued)
•
Select current limit (for 2-Ω and for 4-Ω loads). This allows optimal design of the filter inductor, and the use of
smaller gauge speaker wires for 4-Ω applications.
•
•
•
•
•
•
•
Select AM non-interference switching frequency
Select the function of OTW_CLIP pin
Enable or disable dc detect function with selectable threshold
Place channel in Hi-Z (switching stopped) mode (mute)
Select tweeter detect, set detect threshold and initiate function
Initiate open/short load diagnostic
Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the TAS5414 and the TAS5424 include a single
pin that allows up to four devices to work together in a system with no additional hardware required for
communication or synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the
I2C address for that device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2,
and to D_BYP for slave 3. The OSC_SYNC pin is used to synchronize the internal clock oscillators and thereby
avoid beat frequencies. An external oscillator can also be applied to this pin for external control of the switching
frequency.
Table 2. Table 7. I2C_ADDR Pin Connection
DESCRIPTION
I2C_ADDR PIN CONNECTION
I2C ADDRESS
0xD8/D9
TAS5414/5424 0 (OSC MASTER) To SGND pin
TAS5414/5424 1 (OSC SLAVE1)
TAS5414/5424 2 (OSC SLAVE2)
TAS5414/5424 3 (OSC SLAVE3)
35% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
65% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
To D_BYP pin
0xDA/DB
0xDC/DD
0xDE/DF
(1) RI2C_ADDR with 5% or better tolerance is recommended.
I2C Bus Protocol
The TAS5414 and TAS5424 have a bidirectional serial control interface that is compatible with the Inter IC (I2C)
bus protocol and supports 100-kbps data transfer rates for random and sequential write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 16. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5414 and TAS5424 hold SDA LOW
during the acknowledge-clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on
the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the
master generates a stop condition to release the bus.
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8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
SDA
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
Figure 16. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are
licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the
TAS5414 and the TAS5424, the I2C master uses addresses shown in Figure 16. Read and write data can be
transmitted using single-byte or multiple-byte data transfers.
Random Write
As shown in Figure 17, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the TAS5414 or TAS5424 device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the internal memory address being accessed. After
receiving the address byte, the TAS5414 or TAS5424 again responds with an acknowledge bit. Next, the master
device transmits the data byte to be written to the memory address being accessed. After receiving the data
byte, the TAS5414 or TAS5424 again responds with an acknowledge bit. Finally, the master device transmits a
stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-01
Figure 17. Random Write Transfer
Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master device to TAS5414 or TAS5424 as shown in Figure 17. After receiving each data
byte, the TAS5414 or TAS5424 responds with an acknowledge bit and the I2C subaddress is automatically
incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
Figure 18. Sequential Write Transfer
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Random Read
As shown in Figure 19, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write
bit, the TAS5414 or TAS5424 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5414 or TAS5424
address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After receiving
the address and the read/write bit, the TAS5414 or TAS5424 again responds with an acknowledge bit. Next, the
TAS5414 or TAS5424 transmits the data byte from the memory address being read. After receiving the data
byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte
data-read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
Figure 19. Random Read Transfer
Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the TAS5414 or TAS5424 to the master device as shown in Figure 20. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I2C subaddress by one. Note: The fault registers do not have sequential read capabilities.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 20. Sequential Read Transfer
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Table 3. TAS5414/5424 I2C Addresses
SELECTABLE WITH
FIXED ADDRESS
READ/WRITE
I2C
ADDRESS
ADDRESS PIN
BIT
DESCRIPTION
MSB
6
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
0
0
4
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
LSB
0
TAS5414/5424 0
(OSC MASTER)
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
1
1
1
1
1
1
1
1
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
1
TAS5414/5424 1
(OSC SLAVE1)
0
1
TAS5414/5424 2
(OSC SLAVE2)
0
1
TAS5414/5424 3
(OSC SLAVE3)
0
1
Table 4. I2C Address Register Definitions
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
R/W
R
REGISTER DESCRIPTION
Latched fault register 1, global and channel fault
Latched fault register 2, dc offset and overcurrent detect
Latched fault register 3, load diagnostics
R
R
R
Latched fault register 4, load diagnostics
R
External status register 1, temperature and voltage detect
External status register 2, Hi-Z and low-low state
External status register 3, mute and play modes
External status register 4, load diagnostics
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
External control register 1, channel gain select
External control register 2, dc offset reduction and current-limit select
External control register 3, switching frequency and clip pin select
External control register 4, load diagnostic, master mode select
External control register 5, output state control
External control register 6, output state control
External control register 7, dc detect level select
External control register 8, dc detect level select
Table 5. Fault Register 1 (0x00) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overtemperature warning has occurred
DC offset has occurred in any channel
Overcurrent shutdown has occurred in any channel
Overtemperature shutdown has occurred
Charge pump undervoltage has occurred
AVDD, analog voltage, undervoltage has occurred
PVDD undervoltage has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
PVDD overvoltage has occurred
Table 6. Fault Register 2 (0x01) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Ovecurrent shutdown channel 1 has occurred
Overcurrent shutdown channel 2 has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
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Table 6. Fault Register 2 (0x01) Protection (continued)
D7
–
D6
–
D5
–
D4
–
D3
–
D2
1
D1
–
D0
–
FUNCTION
Overcurrent shutdown channel 3 has occurred
Overcurrent shutdown channel 4 has occurred
DC offset channel 1 has occurred
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
DC offset channel 2 has occurred
–
1
–
–
–
–
–
–
DC offset channel 3 has occurred
1
–
–
–
–
–
–
–
DC offset channel 4 has occurred
Table 7. Fault Register 3 (0x02) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 1 has occurred
Output short to PVDD channel 1 has occurred
Shorted load channel 1 has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 1 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 2 has occurred
Output short to PVDD channel 2 has occurred
Shorted load channel 2 has occurred
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 2 has occurred
Table 8. Fault Register 4 (0x03) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 3 has occurred
Output short to PVDD channel 3 has occurred
Shorted load channel 3 has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 3 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 4 has occurred
Output short to PVDD channel 4 has occurred
Shorted load channel 4 has occurred
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 4 has occurred
Table 9. External Status Register 1 (0x04) Fault Detection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults are present, default value
PVDD overvoltage fault is present
PVDD undervoltage fault is present
AVDD, analog voltage fault is present
Charge-pump voltage fault is present
Overtemperature shutdown is present
Overtemperature warning
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
1
–
–
–
–
–
Overtemperature warning level 1
1
0
1
–
–
–
–
–
Overtemperature warning level 2
1
1
1
–
–
–
–
–
Overtemperature warning level 3
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Table 10. External Status Register 2 (0x05) Output State of Individual Channels
D7
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
FUNCTION
0
–
–
–
–
–
–
–
1
Output is in Hi-Z mode, not in low-low mode(1), default value
–
–
–
–
–
–
0
Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
0
–
Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
0
–
–
Channel 3 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
0
–
–
–
Channel 4 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
1
–
–
–
–
Channel 1 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 2 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 3 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 4 low-low mode (0 = not low-low, 1 = low-low)(1)
–
1
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
(1) Low-low is defined as both outputs actively pulled to ground.
Table 11. External Status Register 3 (0x06) Play and Mute Modes
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Mute mode is enabled, play mode disabled, default value
Channel 1 play mode is enabled
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 play mode is enabled
–
–
–
–
–
1
–
–
Channel 3 play mode is enabled
–
–
–
–
1
–
–
–
Channel 4 play mode is enabled
–
–
–
1
–
–
–
–
Channel 1 mute mode is disabled
Channel 2 mute mode is disabled
Channel 3 mute mode is disabled
Channel 4 mute mode is disabled
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Table 12. External Status Register 4 (0x07) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No channels are set in load diagnostics mode, default value
Channel 1 is in load diagnostics mode
Channel 2 is in load diagnostics mode
Channel 3 is in load diagnostics mode
Channel 4 is in load diagnostics mode
Reserved
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
X
X
X
X
–
–
–
–
Table 13. External Control Register 1 (0x08) Gain Select
D7
1
–
–
–
–
–
–
–
–
–
0
0
1
D6
0
–
–
–
–
–
–
–
–
–
0
1
1
D5
1
–
–
–
–
–
–
0
0
1
–
–
–
D4
0
–
–
–
–
–
–
0
1
1
–
–
–
D3
1
–
–
–
0
0
1
–
–
–
–
–
–
D2
0
–
–
–
0
1
1
–
–
–
–
–
–
D1
1
0
0
1
–
–
–
–
–
–
–
–
–
D0
0
0
1
1
–
–
–
–
–
–
–
–
–
FUNCTION
Set gain for all channels to 26 dB, default value
Set channel 1 gain to 12 dB
Set channel 1 gain to 20 dB
Set channel 1 gain to 32 dB
Set channel 2 gain to 12 dB
Set channel 2 gain to 20 dB
Set channel 2 gain to 32 dB
Set channel 3 gain to 12 dB
Set channel 3 gain to 20 dB
Set channel 3 gain to 32 dB
Set channel 4 gain to 12 dB
Set channel 4 gain to 20 dB
Set channel 4 gain to 32 dB
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Table 14. External Control Register 2 (0x09) DC Offset Reduction and Current Limit
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Enable dc offset reduction, set current limit to level 1
Disable channel 1 dc offset reduction
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Disable channel 2 dc offset reduction
–
–
–
–
–
1
–
–
Disable channel 3 dc offset reduction
–
–
–
–
1
–
–
–
Disable channel 4 dc offset reduction
–
–
–
1
–
–
–
–
Set channel 1 current limit (0 = level 1, 1 = level 2)
Set channel 2 current limit (0 = level 1, 1 = level 2)
Set channel 3 current limit (0 = level 1, 1 = level 2)
Set channel 4 current limit (0 = level 1, 1 = level 2)
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Table 15. External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
0
D0
1
FUNCTION
Set fS = 417 kHz, configure clip and OTW, 45° phase, disable hard stop
Set fS = 500 kHz
–
–
–
–
–
–
0
0
–
–
–
–
–
–
1
0
Set fS = 357 kHz
–
–
–
–
–
–
1
1
Invalid frequency selection (do not set)
Configure CLIP_OTW pin for tweeter detect only
Configure CLIP_OTW pin for clip detect only
Configure CLIP_OTW pin for overtemperature warning only
Enable hard-stop mode
–
–
–
–
0
0
–
–
–
–
–
–
0
1
–
–
–
–
–
–
1
0
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
Set fS to a 90° phase difference between adjacent channels
Reserved
X
X
–
–
–
–
–
–
Table 16. External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
D7
0
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Disable load diagnostics and dc detect SD, master mode
Enable channel 1, load diagnostics
Enable channel 2, load diagnostics
Enable channel 3, load diagnostics
Enable channel 4, load diagnostics
Enable dc detect shutdown on all channels
Enable tweeter-detect mode
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
Enable slave mode (external oscillator must be provided)
Reserved
X
–
–
–
–
–
–
–
Table 17. External Control Register 5 (0x0C) Output Control
D7
0
D6
0
D5
0
D4
1
D3
1
D2
1
D1
1
D0
1
FUNCTION
All channels, Hi-Z, mute, reset disabled
–
–
–
–
–
–
–
0
Set channel 1 to mute mode, non-Hi-Z
Set channel 2 to mute mode, non-Hi-Z
Set channel 3 to mute mode, non-Hi-Z
Set channel 4 to mute mode, non-Hi-Z
Set non-Hi-Z channels to play mode, (unmute)
Reserved
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
1
1
–
–
–
–
–
1
–
–
–
–
–
–
–
Reset device (I2C does not respond with an ACK)
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Table 18. External Control Register 6 (0x0D) Output Control
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Low-low state disabled all channels
0
–
–
–
–
X
–
–
–
–
–
–
1
Set channel 1 to low-low state
Set channel 2 to low-low state
Set channel 3 to low-low state
Set channel 4 to low-low state
Reserved
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
X
X
X
–
–
–
–
Table 19. External Control Register 7 (0x0E) Positive DC Detect Threshold Selection
D7
1
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
FUNCTION
Default positive dc detect value
0
1
1
0
0
1
0
1
Minimum positive dc detect value
X
1
X
1
X
0
X
0
X
1
X
0
X
1
X
1
See Figure 11 to set positive dc detect value
Maximum positive dc detect value
Table 20. External Control Register 8 (0x0F) Negative DC Detect Threshold Selection
D7
0
D6
0
D5
1
D4
1
D3
1
D2
1
D1
0
D0
1
FUNCTION
Default negative dc detect value
0
1
1
0
0
1
0
1
Minimum negative dc detect value
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
See Figure 12 to set negative dc detect value
Maximum negative dc detect value
Hardware Control Pins
The TAS5414 and TAS5424 incorporate four discrete hardware pins for real-time control and indication of device
status.
FAULT pin: This active-low, open-drain output pin indicates the presence of a fault condition that requires
the TAS5414 and TAS5424 to go automatically into the Hi-Z mode or standby mode. When this pin is
asserted high, the device has acted to protect itself and the system from potential damage. The exact nature
of the fault can be read via I2C with the exception of faults that are the result of PVDD voltage excursions
above 25 Vdc or below 5.5 Vdc. In these instances, the device goes into standby mode and the I2C bus is
no longer operational. However, the fault is still indicated due to the fact that the FAULT pin is open-drain
and active-high.
CLIP_OTW pin: The function of this active-high pin is configured by the user to indicate one of the following
conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.
The configuration is selected via I2C. During tweeter detect diagnostics, this pin also is asserted when a
tweeter is present.
MUTE pin: This active-low pin is used for hardware control of the mute/unmute function for all four channels.
Capacitor CMUTE is used to control the time constant for the gain ramp needed to produce a pop- and
click-free mute function. For pop- and click-free operation, the mute function should be implemented through
I2C commands. The use of a hard mute with an external transistor does not ensure pop- and click-free
operation, and is not recommended unless an emergency hard mute function is required in case of a loss of
I2C control. The value of CMUTE must be 330 nF for proper pop- and click-free operation.
STANDBY pin: When this active-low pin is asserted, the device goes into a complete shutdown, and current
draw is limited to 2 µA, typical. This is pin typically asserted when the car ignition is in the off position. It can
also be used to shut down the device rapidly when certain operating conditions are violated. All I2C register
content is lost when this pin is asserted. The I2C bus goes into the high-impedance state when the
STANDBY pin is asserted.
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EMI Considerations
Automotive level EMI performance depends on both careful integrated circuit design and good system level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
TAS5414 and TAS5424 design.
The TAS5414 and TAS5424 have minimal parasitic inductances due to the short leads on the PSOP3 package.
This dramatically reduces the EMI that results from current passing from the die to the system PCB. Each
channel of the TAS5414 and TAS5424 also operates at a different phase. The phase between channels is I2C
selectable to either 45° or 90°, to reduce EMI caused by high-current switching. The TAS5414 and TAS5424
incorporate patent-pending circuitry that optimizes output transitions that cause EMI.
AM Radio EMI Reduction
To reduce interference in the AM radio band, the TAS5414 and TAS5424 have the ability to change the
switching frequency via I2C commands. The recommended frequencies are listed in Table 21. The fundamental
frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be
present due to the switching frequency being demodulated by the AM radio. To function properly, AM avoidance
requires the use of a 20-kΩ, 1% tolerance Rext resistor.
Table 21. Recommended Switching Frequencies for AM Mode Operation
US
EUROPEAN
SWITCHING
FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
522-540
540–914
417
500
417
500
417
357
540–917
917–1125
1125–1375
1375–1547
1547–1700
500
417
500
417
357
914–1122
1122–1373
1373–1548
1548–1701
Operating States
The operating regions, or states, of the TAS5414 and TAS5424 are depicted in the following tables.
Table 22. Operating States and Supplies
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z, floating
CHARGE PUMP
Stopped
Active
OSCILLATOR
Stopped
Active
I2C
AVDD and DVDD
Stopped
Active
Active
Active
OFF
ON
ON
ON
Hi-Z, weak pulldown
Switching at 50%
Switching with audio
Mute
Active
Active
Normal operation
Active
Active
Table 23. Global Faults and Actions
LATCHED/
SELF-
CLEARING
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
MODES
POR
UV
Voltage fault
All
FAULT pin
I2C + FAULT pin
Hard mute (no ramp)
Standby
Hi-Z
Self-clearing
Hi-Z, mute, normal
CP UV
OV
Hi-Z
Hi-Z
Load dump
OTW
All
FAULT pin
Standby
None
Thermal warning
Thermal fault
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + CLIP_OTW pin
I2C + FAULT pin
None
Self-clearing
Self-clearing
OT
Hard mute
Standby
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Table 24. Channel Faults and Actions
LATCHED/
SELF-
CLEARING
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
Open/short
diagnostic
Diagnostic
Hi-Z (I2C activated)
I2C
None
None
Latched
Clipping online
Warning
Normal
CLIP_OTW pin
CLIP_OTW pin
None
None
Self-clearing
Self-clearing
CBC load current
limit
Online protection
Mute, normal
Current limit
Start OC
timer
OC fault
Output channel fault
Mute, normal
Normal
I2C + FAULT pin
I2C + FAULT pin
Hard mute
Hard mute
Hi-Z
Hi-Z
Latched
Latched
DC detect
Min Rise Time
29 V to 50 V: 1 ms
50 V
29 V
Load Dump
Protection
29 V – 50 V
LD
Detect
OV
Detect
OV Protection Region 23 V – 29 V
Normal Operating Region 8 V – 22 V
23 V
22 V
PVDD
FAULT
I2C
CLK
Hard Stop
15 V
OUTM
(Filtered)
15 V
Time
t0
t1
Outputs
Deglitch Pulled
Time Down
t2
OV
T0190-01
Figure 21. Sequence of Events for Supply Transition Out of Normal Operating Region
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50 V
Load Dump
Protection
29 V–50 V
LD
Reset
26 V
23 V
OV Protection Region 23 V–29 V
OV
Reset
PVDD
FAULT
Fault Does Not Reset Until Fault
Register 1 Is Read
I2C
CLK
Ready to Get
Out of Hi-Z
State
15-V
OUTP or
OUTM
Time
(Filtered)
Outputs
Pulled
Down
t0 t1
t2 t3
OV
Oscillator
Start-Up Time
Deglitch Time
T0191-01
Figure 22. Sequence of Events for Supply Transition Back Into Normal Operating Region
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Power Shutdown and Restart Sequence Control
tGAIN
tCM
tCM
tGAIN
HIZ_CTLx
(All Channels)
Internal I2C Reset
When HIZ_CTLx = 1
LOW_LOW_CTLx
(All Channels)
MUTE_CTLx
(All Channels)
MUTE Pin
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
HIZ_MODx
LOW_LOW_MODx
PLAY_MODx
MUTE_MODx
T0192-01
Figure 23. Click- and Pop-Free Shutdown and Restart Sequence Timing Diagram
With Four Channels Sharing the Mute Pin
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tGAIN
tCM
tCM
tGAIN
HIZ_CTL1
HIZ_CTL2,3,4
Internal I2C Reset
When HIZ_CTL1 = 1
LOW_LOW_CTL1
LOW_LOW_CTL2,3,4
MUTE_CTL
Internal I2C Reset When
When HIZ_CTL2,3,4 = 1
MUTE Pin
"Pop"
"Pop"
OUT1_P
(Filtered)
OUT2,3,4_P
(Filtered)
T0193-01
Figure 24. Individual Channel Shutdown and Restart Sequence Timing Diagram
32
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Latched Fault Shutdown and Restart Sequence Control
tI2C_CL
tDEGLITCH
tDEGLITCH
tGAIN
tCM
UV
Detect
UV
Reset
PVDD Normal Operating Region
PVDD UV Hysteresis Region
PVDD
VUV + VUV_HY
VUV
VPOR
HIZ_CTLx
Internal I2C Write
MUTE_CTL
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
“Pop”
OUTx_P (Filtered)
T0194-01
Figure 25. Latched Global Fault Shutdown and Restart Timing Diagram
(UV Shutdown and Recovery)
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tI2C_CL
tDEGLITCH
tDEGLITCH
tCM
tGAIN
UV
Detect
UV
Reset
PVDD Normal Operating Region
PVDD UV Hysteresis Region
PVDD
VUV + VUV_HY
VUV
VPOR
Internal I2C Write
HIZ_CTL1
HIZ_CTL2,3,4
MUTE_CTL
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
“Pop”
“Pop”
“Pop”
OUT1_P (Filtered)
OUT2,3,4_P (Filtered)
T0195-01
Figure 26. Latched Global Fault Shutdown and Individual Channel Restart Timing Diagram
(UV Shutdown and Recovery)
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APPLICATION INFORMATION
+
s r o t s i s e R
u - p l l u P
P S D o i d a R
Figure 27. TAS5414 Application Schematic
35
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APPLICATION INFORMATION (continued)
s t u p n I o i d u A
s r o t s i s e R
p u - l l u P
Figure 28. TAS5424 Typical Application Schematic
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APPLICATION INFORMATION (continued)
Parallel Operation (PBTL)
TAS5414 and TAS5424 can be used to drive four 4Ω loads, two 2Ω loads, or even one 1Ω load by paralleling
BTL channels on the load side of the LC output filter. For parallel operation, identical I2C settings are required
for any two paralleled channels (especially gain and current-limit settings) in order to have reliable system
performance and evenly dissipated power on multiple channels. Having identical gain and current-limit settings
can also prevent energy feeding back from one channel to the other. For smooth power up, power down, and
mute operation, the same control commands (such as mute, play, Hi-Z, etc.) should be sent to the paralleled
channels at the same time. Load diagnostic is also supported for parallel connection. Paralleling on the
TAS5414 and TAS5424 side of the LC output filter is not supported, and can result in device failure.
DEMODULATION FILTER DESIGN
The TAS5414 and TAS5424 amplifier outputs are driven by high-current LDMOS transistors in an H-bridge
configuration. These transistors are either off or fully on. The result is a square-wave output signal with a duty
cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be
used to recover the audio signal. The main purpose of the demodulation filter is to attenuate the high-frequency
components of the output signals that are out of the audio band. Design of the demodulation filter significantly
affects the audio performance of the power amplifier. Therefore, to meet the device THD+N specification, the
selection of the inductors used in the output filter should be carefully considered. The rule is that the inductance
should remain stable within the range of peak current seen at maximum output power and deliver approximately
5 µH of inductance at 16 A. If this rule is observed, the TAS5414 and TAS5424 should not have distortion issues
due to the output inductors. Another parameter to be considered is the idle-current loss in the inductor. This can
be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05. If
the dissipation factor is above this value, idle current increases. In general, 10-µH inductors suffice for most
applications. The frequency response of the amplifier is slightly altered by the change in output load resistance;
however, unless tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to
deviate from 10 µH.
THERMAL INFORMATION
The thermally augmented package provided with the TAS5414 and TAS5424 is designed to interface directly to
heat sinks using a thermal interface compound (for example, Artic Silver, Ceramique thermal compound.) The
heat sink then absorbs heat from the ICs and couples it to the local air. If louvers or fans are supplied, this
process can reach equilibrium and heat can be continually removed from the ICs. Because of the efficiency of
the TAS5414 and TAS5424, heat sinks can be smaller than those required for linear amplifiers of equivalent
performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
•
•
•
RθJC (the thermal resistance from junction to case, or in this case the heat slug)
Thermal grease thermal resistance
Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal
grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal
resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W
(4.52°C-mm2/W). The approximate exposed heat slug size is as follows:
TAS5424, 44-pin PSOP3 …………………. 0.124 in2 (80 mm2)
TAS5414, 36-pin PSOP3 …………………. 0.124 in2 (80 mm2)
Dividing the example thermal grease area resistance by the area of the heat slug gives the actual resistance
through the thermal grease for both parts:
TAS5424, 44-pin PSOP3 ………………… 0.40°C/W
TAS5414, 36-pin PSOP3 ………………… 0.40°C/W
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APPLICATION INFORMATION (continued)
The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance
generally is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or
measured.
Thus, for a single monaural channel in the IC, the system RθJA = RθJC + thermal grease resistance + heat sink
resistance.
The following table indicates modeled parameters for one TAS5414 or TAS5424 IC on a heat sink. The junction
temperature is set at 115°C in both cases while delivering 20 Wrms per channel into 4-Ω loads with no clipping.
It is assumed that the thermal grease is about 0.001 inches (0.0254 mm) thick (this is critical).
Device
Ambient temperature
TAS5414, 36-Pin PSOP3
25°C
Power to load
20 W × 4
1.90 W × 4
7.6°C
Power dissipation
∆T inside package
∆T through thermal grease
Required heatsink thermal resistance
Junction temperature
System RθJA
3°C
10.45°C/W
115°C
11.85°C/W
90°C
RθJA × power dissipation
As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases
to 0.002 inches (0.0508 mm) thick, the required heat sink thermal resistance changes to 6°C/W for the PSOP3.
38
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PACKAGE OPTION ADDENDUM
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8-Mar-2007
PACKAGING INFORMATION
Orderable Device
TAS5414TDKDQ1
TAS5414TDKDRQ1
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DKD
36
29 Green (RoHS & CU NIPDAU Level-3-245C-168 HR
no Sb/Br)
SSOP
DKD
36
500 Green (RoHS & CU NIPDAU Level-3-245C-168 HR
no Sb/Br)
TAS5424TDKDQ1
TAS5424TDKDRQ1
PREVIEW
PREVIEW
SSOP
SSOP
DKD
DKD
44
44
29
TBD
TBD
Call TI
Call TI
Call TI
Call TI
500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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