TAS5424C-Q1 [TI]
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS;
| 型号： | TAS5424C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS 放大器 |
| 文件： | 总39页 (文件大小：1224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5414C-Q1
TAS5424C-Q1
www.ti.com
SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS
Check for Samples: TAS5414C-Q1, TAS5424C-Q1
1
FEATURES
2
•
•
•
•
•
TAS5414C-Q1 – Single-Ended Input
•
•
44-Pin PSOP3 (DKE) Power SOP Package With
Heat Slug Up for TAS5424C-Q1
TAS5424C-Q1 – Differential Input
64-Pin QFP (PHD) Power Package With Heat
Slug Up for TAS5414C-Q1
Four-Channel Digital Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
Typical Output Power at 10% THD+N
•
•
•
•
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100
–
–
–
–
28 W/Ch Into 4 Ω at 14.4 V
50 W/Ch Into 2 Ω at 14.4 V
79 W/Ch Into 4 Ω at 24 V
ISO9000:2002 TS16949 Certified
–40°C to 105°C Ambient Temperature Range
150 W/Ch Into 2 Ω at 24 V (PBTL)
APPLICATIONS
•
Channels Can Be Paralleled (PBTL) for High-
Current Applications
OEM/Retail Head Units and Amplifier Modules
Where
Feature
Densities
and
System
•
•
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
Configurations Require Reduction in Heat
From the Audio Power Amplifier
Patented Pop- and Click-Reduction
Technology
DESCRIPTION
–
–
Soft Muting With Gain Ramp Control
Common-Mode Ramping
The TAS5414C-Q1 and TAS5424C-Q1 are four-
channel digital audio amplifiers designed for use in
automotive head units and external amplifier
modules. They provide four channels at 23 W
continuously into 4 Ω at less than 1% THD+N from a
14.4-V supply. Each channel can also deliver 38 W
into 2 Ω at 1% THD+N. The TAS5414C-Q1 uses
single-ended analog inputs, whereas the TAS5424C-
Q1 employs differential inputs for increased immunity
to common-mode system noise. The digital PWM
topology of the device provides dramatic
improvements in efficiency over traditional linear
amplifier solutions. This reduces the power dissipated
by the amplifier by a factor of ten under typical music
playback conditions. The device incorporates all the
functionality needed to perform in the demanding
OEM applications area. The devices have built-in
load diagnostic functions for detecting and diagnosing
misconnected outputs to help to reduce test time
during the manufacturing process.
•
•
•
•
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
•
•
Channel Gains: 12-dB, 20-dB, 26-dB, 32-dB
Load Diagnostic Functions:
–
–
–
Output Open and Shorted Load
Output-to-Power and -to-Ground Shorts
Patented Tweeter Detection
•
Protection and Monitoring Functions:
–
–
–
Short-Circuit Protection
Load-Dump Protection to 50 V
Fortuitous Open-Ground and -Power
Tolerant
–
Patented Output DC Level Detection While
Music Playing
–
–
–
Overtemperature Protection
Over- and Undervoltage Conditions
Clip Detection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TAS5414C-Q1
TAS5424C-Q1
SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
2
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments are shown as follows.
DKE Package
(Top View)
Figure 1. TAS5424C-Q1 44-Pin Package
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PHD Package
(Top View)
Figure 2. TAS5414C-Q1 64-Pin Package
4
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Table 1. PIN FUNCTIONS
PIN
DKE
PACKAGE
PHD PACKAGE
TYPE
DESCRIPTION
NAME
TAS5424C-Q1
NO.
TAS5414C-Q1
NO.
A_BYP
14
11
PBY
DO
Bypass pin for the AVDD analog regulator
Reports CLIP, OTW, or both. It also reports tweeter detection
during tweeter mode. Open-drain
CLIP_OTW
10
6
Top of main storage capacitor for charge pump (bottom goes to
PVDD)
CP
34
41
CP
CPC_BOT
CPC_TOP
D_BYP
33
35
9
40
42
5
CP
CP
Bottom of flying capacitor for charge pump
Top of flying capacitor for charge pump
PBY
DO
Bypass pin for DVDD regulator output
FAULT
5
1
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
3, 7, 8, 9, 12, 14, 16,
17, 21, 22, 23, 24, 25,
26, 30, 31, 32, 35, 38,
39, 43, 46, 49, 50, 51,
55, 56, 57, 58, 59, 60
7, 11, 12, 28,
29, 32, 38, 39
GND
GND
Ground
I2C_ADDR
IN1_M
IN1_P
2
62
N/A
13
AI
AI
AI
AI
AI
AI
AI
AI
AI
I2C address bit
16
15
18
17
20
19
22
21
Inverting analog input for channel 1 (TAS5424C-Q1 only)
Non-inverting analog input for channel 1
IN2_M
IN2_P
N/A
15
Inverting analog input for channel 2 (TAS5424C-Q1 only)
Non-inverting analog input for channel 2
IN3_M
IN3_P
N/A
19
Inverting analog input for channel 3 (TAS5424C-Q1 only)
Non-inverting analog input for channel 3
IN4_M
IN4_P
N/A
20
Inverting analog input for channel 4 (TAS5424C-Q1 only)
Non-inverting analog input for channel 4
Signal return for the four analog channel inputs (TAS5414C-Q1
only)
IN_M
N/A
18
ARTN
MUTE
6
2
AI
DI/DO
PO
Gain ramp control: mute (low), play (high)
Oscillator input from master or output to slave amplifiers
– polarity output for bridge 1
OSC_SYNC
OUT1_M
OUT1_P
OUT2_M
OUT2_P
OUT3_M
OUT3_P
OUT4_M
OUT4_P
1
61
48
47
45
44
37
36
34
33
41
40
37
36
31
30
27
26
PO
+ polarity output for bridge 1
PO
– polarity output for bridge 2
PO
+ polarity output for bridge 2
PO
– polarity output for bridge 3
PO
+ polarity output for bridge 3
PO
– polarity output for bridge 4
PO
+ polarity output for bridge 4
23, 24, 25, 42,
43, 44
PVDD
27, 28, 29, 52, 53, 54
PWR
PVDD supply
REXT
SCL
13
4
10
64
63
4
AI
DI
Precision resistor pin to set analog reference
I2C clock input from system I2C master
I2C data I/O for communication with system I2C master
SDA
3
DI/DO
DI
STANDBY
8
Active-low STANDBY pin. Standby (low), power up (high)
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
30
PVDD
DC supply voltage range
Pulsed supply voltage range
Supply voltage ramp rate
Relative to GND
–0.3
–1
V
V
PVDDMAX
PVDDRAMP
IPVDD
t ≤ 100 ms exposure
50
15
V/ms
A
Externally imposed dc supply current per PVDD or GND
pin
±12
IPVDD_MAX
IO
Pulsed supply current per PVDD pin (one shot)
Maximum allowed dc current per output pin
Pulsed output current per output pin (single pulse)
Maximum current, all digital and analog input pins(2)
Maximum current on MUTE pin
t < 100 ms
17
±13.5
±17
±1
A
A
(1)
IO_MAX
t < 100 ms
A
IIN_MAX
DC or pulsed
DC or pulsed
mA
mA
mA
IMUTE_MAX
IIN_ODMAX
±20
7
Maximum sink current for open-drain pins
Input voltage range for pin relative to GND (SCL, SDA,
I2C_ADDR pins)
Supply voltage range:
6V < PVDD < 24 V
VLOGIC
–0.3
–0.3
–0.3
–0.3
6
V
V
V
Supply voltage range:
6 V < PVDD < 24 V
VMUTE
Voltage range for MUTE pin relative to GND
Input voltage range for STANDBY pin
7.5
5.5
Supply voltage range:
6 V < PVDD < 24 V
VSTANDBY
Supply voltage range:
6 V < PVDD < 24 V
VOSC_SYNC
VGND
Input voltage range for OSC_SYNC pin relative to GND
Maximum voltage between GND pins
Maximum ac-coupled input voltage for TAS5414C-Q1(2)
analog input pins
3.6
±0.3
1.9
V
V
,
Supply voltage range:
6 V < PVDD < 24 V
VAIN_AC_MAX_5414
Vrms
Maximum ac-coupled differential input voltage for
TAS5424C-Q1(2), analog input pins
Supply voltage range:
6 V < PVDD < 24 V
VAIN_AC_MAX_5424
3.8
Vrms
TJ
Maximum operating junction temperature range
Storage temperature range
–55
–55
150
150
°C
°C
Tstg
(1) Pulsed current ratings are maximum survivable currents externally applied to the device. The device may encounter high currents during
reverse-battery, fortuitous open-ground, and fortuitous open-supply fault conditions.
(2) See the Application Information section for information on analog input voltage and ac coupling.
THERMAL CHARACTERISTICS
PARAMETER
VALUE (Typical)
UNIT
Junction-to-case (heat slug) thermal
resistance, DKE package
RθJC
RθJC
RθJA
1
Junction-to-case (heat slug) thermal
resistance, PHD package
1.2
°C/W
This device is not intended to be used without a heatsink. Therefore, RθJA
is not specified. See the Thermal Information section.
Junction-to-ambient thermal resistance
Exposed pad dimensions, DKE package
Exposed pad dimensions, PHD package
13.8 × 5.8
8 × 8
mm
6
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
ELECTROSTATIC DISCHARGE (ESD)
PARAMETER
Package
Pins
VALUE
UNIT
(Typical)
Human Body Model
(HBM)
All
All
3000
V
AEC-Q100-002
Corner pins excluding OSC_SYNC
1000
500
400
750
600
400
DKE
PHD
All other pins (including OSC_SYNC) except CP pin
CP pin (Non-Corner Pin)
V
V
Changed Device Model
(CDM)
AEC-Q100-011
Corner pins excluding SCL
All pins (including SCL) except CP and CP_Top
CP and CP_Top pins
RECOMMENDED OPERATING CONDITIONS(1)
MIN
6
TYP
MAX
UNIT
V
PVDDOP
VAIN_5414
VAIN_5424
TA
DC supply voltage range relative to GND
Analog audio input signal level (TAS5414C-Q1)
Analog audio input signal level (TAS5424C-Q1)
Ambient temperature
14.4
24
0.25–1(3)
0.5–2(3)
105
(2)
(2)
AC-coupled input voltage
AC-coupled input voltage
0
Vrms
Vrms
°C
0
–40
An adequate heat sink is required
to keep TJ within specified range.
TJ
Junction temperature
–40
115
°C
RL
Nominal speaker load impedance
2
3
4
Ω
VPU
Pullup voltage supply (for open-drain logic outputs)
3.3 or 5
5.5
50
10
V
Resistor connected between open-
drain logic output and VPU supply
RPU_EXT
RPU_I2C
RI2C_ADD
RREXT
External pullup resistor on open-drain logic outputs
I2C pullup resistance on SDA and SCL pins
10
1
kΩ
kΩ
4.7
20
Total resistance of voltage divider for I2C address
slave 1 or slave 2, connected between D_BYP and
GND pins
10
50
kΩ
External resistance on REXT pin
1% tolerance required
19.8
10
20.2
120
kΩ
CD_BYP
CA_BYP
,
External capacitance on D_BYP and A_BYP pins
nF
COUT
CIN
External capacitance to GND on OUT_X pins
150
680
nF
External capacitance to analog input pin in series
with input signal
0.47
μF
CFLY
CP
Flying capacitor on charge pump
Charge pump capacitor
0.47
0.47
100
1
1
1.5
1.5
μF
μF
nF
pF
50V needed for Load Dump
CMUTE
MUTE pin capacitor
220
75
1000
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
(1) The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical
Characteristics table for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.
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ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPERATING CURRENT
IPVDD_IDLE
All four channels in MUTE mode
170
93
2
220
mA
PVDD idle current
IPVDD_Hi-Z
All four channels in Hi-Z mode
IPVDD_STBY
PVDD standby current
STANDBY mode, TJ ≤ 85°C
10
μA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
23
28
79
38
50
25
63
POUT
Output power per channel
W
40
PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%,
1 kHz, Tc = 75°C
150
90
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, Tc = 75°C
4 channels operating, 23-W output power/ch, L = 10 μH,
TJ ≤ 85°C
EFFP
Power efficiency
90%
AUDIO PERFORMANCE
VNOISE
Noise voltage at output
Zero input, and A-weighting
60
85
100
μV
P = 1 W, f = 1 kHz, enhanced crosstalk enabled via I2C
(reg. 0x10)
Channel crosstalk
70
dB
Common-mode rejection ratio (TAS5424C-
Q1)
CMRR5424
f = 1 kHz, 1 Vrms referenced to GND, G = 26 dB
60
60
75
dB
dB
PSRR
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P = 1 W, f = 1 kHz
75
0.02%
357
THD+N
Total harmonic distortion + noise
0.1%
378
442
530
106
336
392
470
63
Switching frequency selectable for AM interference
avoidance
fS
Switching frequency
417
kHz
500
RAIN
Analog input resistance
Internal shunt resistance on each input pin
85
kΩ
Vrms
V
AC-coupled common-mode input voltage (zero
differential input)
VIN_CM
VCM_INT
Common-mode input voltage
Internal common-mode input bias voltage
1.3
Internal bias applied to IN_M pin
3.3
12
20
26
32
0
11
19
25
31
–1
13
21
27
33
1
Source impedance = 0 Ω, gain measurement taken at 1
W of power per channel
G
Voltage gain (VO/VIN
)
dB
dB
GCH
Channel-to-channel variation
Any gain commanded
PWM OUTPUT STAGE
RDS(on)
FET drain-to-source resistance
Output offset voltage
Not including bond wire resistance, TJ = 25°C
Zero input signal, G = 26 dB
65
90
mΩ
VO_OFFSET
±10
±50
mV
PVDD OVERVOLTAGE (OV) PROTECTION
VOV_SET
PVDD overvoltage shutdown set
PVDD overvoltage shutdown clear
24.6
24.4
26.4
25.9
28.2
27.4
V
V
VOV_CLEAR
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET
PVDD undervoltage shutdown set
PVDD undervoltage shutdown clear
4.9
6.2
5.3
6.6
5.6
7
V
V
VUV_CLEAR
AVDD
VA_BYP
A_BYP pin voltage
A_BYP UV voltage
6.5
4.8
5.3
V
V
V
VA_BYP_UV_SET
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV
DVDD
VD_BYP
D_BYP pin voltage
3.3
V
8
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER-ON RESET (POR)
I2C active above this voltage
VPOR
PVDD voltage for POR
4
V
V
VPOR_HY
REXT
VREXT
PVDD recovery hysteresis voltage for POR
0.1
Rext pin voltage
1.27
V
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
Recovery voltage for CP UV
4.8
4.9
V
V
VCPUV_CLEAR
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
96
112
122
128
138
°C
°C
TOTW1_SET
/
106
TOTW2_CLEAR
Junction temperature for overtemperature
warning
TOTW2_SET
/
116
126
136
130
132
142
152
150
148
158
168
170
°C
°C
°C
°C
TOTW3_CLEAR
TOTW3_SET
/
TOTSD_CLEAR
Junction temperature for overtemperature
shutdown
TOTSD
Junction temperature for overtemperature
foldback
TFB
Per channel
CURRENT LIMITING PROTECTION
Level 1
5.5
7.3
9
ILIM
Current limit (load current)
A
A
Level 2 (default)
10.6
12.7
15
OVERCURRENT (OC) SHUTDOWN PROTECTION
Level 1
7.8
9.8
12.2
17.7
IMAX
Maximum current (peak output current)
Level 2 (default), Any short to supply, ground, or other
channels
11.9
14.8
TWEETER DETECT
ITH_TW
Load-current threshold for tweeter detect
330
2
445
2.1
560
mA
A
ILIM_TW
Load-current limit for tweeter detect
STANDBY MODE
VIH
STANDBY input voltage for logic-level high
STANDBY input voltage for logic-level low
STANDBY pin current
V
V
VIL
0.7
0.2
ISTBY
0.1
100
25
μA
MUTE MODE
GMUTE
MUTE pin ≤ 0.5 V for 200ms or I2C Mute Enabled
Output attenuation
dB
DC DETECT
VTH_DC_TOL
DC detect threshold tolerance
%
s
DC detect step-response time for four
channels
tDCD
5.3
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
high (open-drain logic output)
VOH_CLIPOTW
VOL_CLIPOTW
2.4
V
V
External 47-kΩ pullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
0.5
20
CLIP_OTW signal delay when output
clipping detected
tDELAY_CLIPDET
FAULT REPORT
VOH_FAULT
μs
FAULT pin output voltage for logic-level high
(open-drain logic output)
2.4
External 47-kΩ pullup resistor to 3 V–5.5 V
V
FAULT pin output voltage for logic-level low
(open-drain logic output)
VOL_FAULT
0.5
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ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPEN, SHORT DIAGNOSTICS
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
RS2P, RS2G
200
1300
1.5
Ω
Ω
Ω
Minimum load resistance to detect open
circuit
ROPEN_LOAD
RSHORTED_LOAD
Including speaker wires
300
0.5
740
1
Maximum load resistance to detect short
circuit
Including speaker wires
I2C ADDRESS DECODER
Time delay to latch I2C address after POR
tLATCH_I2CADDR
300
0%
μs
Voltage on I2C_ADDR pin for address 0
Voltage on I2C_ADDR pin for address 1
Voltage on I2C_ADDR pin for address 2
Voltage on I2C_ADDR pin for address 3
Connect to GND
0%
25%
55%
85%
15%
45%
35%
65%
100%
External resistors in series between D_BYP and GND as
a voltage divider
VI2C_ADDR
VD_BYP
75%
Connect to D_BYP
100%
I2C
Power-on hold time before I2C
communication
tHOLD_I2C
STANDBY high
1
ms
fSCL
VIH
VIL
SCL clock frequency
400
5.5
1.1
kHz
V
SCL pin input voltage for logic-level high
SCL pin input voltage for logic-level low
2.1
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
–0.5
V
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOH
VO
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
SDA pin input voltage for logic-level high
2.4
V
V
V
I2C read, 3-mA sink current
0.4
5.5
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIH
2.1
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIL
SDA pin input voltage for logic-level low
Capacitance for SCL and SDA pins
–0.5
1.1
10
V
C I
pF
OSCILLATOR
OSC_SYNC pin output voltage for logic-
level high
VOH
VOL
VIH
VIL
2.4
2
V
V
V
V
I2C_ADDR pin set to MASTER mode
I2C_ADDR pin set to SLAVE mode
OSC_SYNC pin output voltage for logic-
level low
0.5
0.8
OSC_SYNC pin input voltage for logic-level
high
OSC_SYNC pin input voltage for logic-level
low
I2C_ADDR pin set to MASTER mode, fS = 500 kHz
I2C_ADDR pin set to MASTER mode, fS = 417 kHz
I2C_ADDR pin set to MASTER mode, fS = 357 kHz
3.76
3.13
2.68
4
3.33
2.85
4.24
3.63
3.0
fOSC_SYNC
OSC_SYNC pin clock frequency
MHz
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TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
300
UNIT
ns
tr
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
300
ns
tw(H)
tw(L)
tsu2
th2
0.6
1.3
0.6
0.6
100
0(1)
0.6
μs
SCL pulse duration, low
μs
Setup time for START condition
START condition hold time until generation of first clock pulse
Data setup time
μs
μs
tsu1
th1
ns
Data hold time
ns
tsu3
CB
Setup time for STOP condition
Load capacitance for each bus line
μs
400
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
Figure 3. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 4. Timing for Start and Stop Conditions
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TYPICAL CHARACTERISTICS
THD+N
vs
THD+N
versus
BTL OUTPUT POWER at 1kHz
PBTL OUTPUT POWER at 1kHz
Figure 5.
Figure 6.
TAS5424C-Q1
COMMON-MODE REJECTION RATIO
versus
THD+N
versus
FREQUENCY at 1 Watt
FREQUENCY
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
CROSSTALK
versus
FREQUENCY
NOISE FFT
Figure 9.
Figure 10.
EFFICIENCY,
FOUR CHANNELS AT 4 Ω EACH
DEVICE POWER DISSIPATION
FOUR CHANNELS AT 4 Ω EACH
100
90
80
70
60
50
40
30
20
10
0
12
10
8
6
4
2
0
0
4
8
12
16
20
24
28
32
0
5
10
15
20
P − Power Per Channel − W
P − Power Per Channel − W
G007
G008
Figure 11.
Figure 12.
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DESCRIPTION OF OPERATION
OVERVIEW
The TAS5414C-Q1 and TAS5424C-Q1 are single-chip, four-channel, analog-input audio amplifiers for use in the
automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments,
but with changes needed by the automotive industry. This technology allows for reduced power consumption,
reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound system
design with smaller size and lower weight than traditional class-AB solutions.
There are eight core design blocks:
•
•
•
•
•
•
•
•
Preamplifier
PWM
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
Preamplifier
The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The
high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency
response. A dedicated, internally regulated supply pwoers the preamplifier, giving it excellent noise immunity and
channel separation. The preamplifier also includes:
1. Mute Pop-and-Click Control— The device ramps the gain gradually when ib receiving a mute or play
command. The start or stopping of switching in a class-D amplifier can cause another form of click and pop.
The TAS5414C-Q1 and TAS5424C-Q1 incorporate a patented method to reduce the pop energy during the
switching startup and shutdown sequence. Fault conditions require rapid protection response by the
TAS5414C-Q1and the TAS5424C-Q1, which do not have time to ramp the gain down in a pop-free manner.
The device transitions into Hi-Z mode when encountering an OV, UV, OC, OT, or dc fault. Also, activation of
the STANDBY pin may not be pop-free.
2. Gain Control—Setting of gains for the four channels occurs in the preamplifier via I2C control registers,
outside of the global feedback resistors of the device, thus allowing for stability of the system at all gain
settings with properly loaded conditions.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5414C-Q1 and TAS5424C-Q1, the modulator is
an advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100%
modulation capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation
characteristic of PWMs when the input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V 65-mΩ FETs for high efficiency and
maximum power transfer to the load. These FETs can handle large voltage transients during load dump.
Load Diagnostics
The device incorporates load diagnostic circuitry designed to help pinpoint the nature of output misconnections
during installation. The TAS5414C-Q1 and the TAS5424C-Q1 include functions for detecting and determining the
status of output connections. The devices support the following diagnostics:
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•
•
•
•
•
Short to GND
Short to PVDD
Short across load
Open load
Tweeter detection
Reporting to the system of the presence of any of the short or open conditions occurs via I2C register read. One
can read the tweeter-detect status from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open
conditions on the outputs. Invocation of the load diagnostic function can only occur when the output is in the
Hi-Z mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all
channels must be in the Hi-Z state. Testing covers all four phases on each channel, all four channels at the
same time. When fewer than four channels are in Hi-Z, the reduced level of test is the only available option.
In the reduced level, the only tests available are short to PVDD and short to GND. Load diagnostics can
occur at power up before moving the amplifier out of Hi-Z mode. If the amplifier is already in play mode, it
must Mute and then Hi-Z before performing the load diagnostic. By performing the mute function, the normal
pop- and click-free transitions occur before the diagnostics begin. Performance of the diagnostics is as
shown in Figure 13. Figure 14 shows the impedance ranges for the open-load and shorted-load diagnostics.
Reading the results of the diagnostics is from the diagnostic register via I2C for each channel. With the
default settings and MUTE capacitor, the S2G and S2P phase take approximately 20 ms each, the OL phase
takes approximately 100 ms, and the SL takes approximately 230 ms. In I2C register 0x10, bit D4 can extend
the test time for S2P and S2G to 80 ms each. To prevent false S2G and S2P faults, this time extension is
necessary if the output pins have a capacitance higher than 680 nF to ground .
Figure 13. Load Diagnostics Sequence of Events
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Figure 14. Open- and Shorted-Load Detection
2. Tweeter Detection—Tweeter detection is an alternate operating mode used to determine the proper
connection of a frequency-dependent load (such as a speaker with a crossover). Invoking of weeter detection
is via I2C, with individual testing of all four channels recommended. Tweeter detection uses the average
cycle-by-cycle current limit circuit (see CBC section) to measure the current delivered to the load. The proper
implementation of this diagnostic function depends on the amplitude of a user-supplied test signal and on the
impedance-versus-frequency curve of the acoustic load. The system (external to the TAS5414C-Q1 and
TAS5424C-Q1) must generate a signal to which the load responds. The frequency and amplitude of this
signal must be calibrated by the user to result in a current draw that is greater than the tweeter detection
threshold when the load under test is present, and less than the detection threshold if the load is
unconnected. The current level for the tweeter detection threshold, as well as the maximum current that can
safely be delivered to a load when in tweeter-detection mode, is in the Electrical Characteristics section of
the data sheet. Reporting of the tweeter-detection results is on the CLIP_OTW pin during the application of
the test signal. With tweeter detection activated (indicating that the tested load is present), pulses on the
CLIP_OTW pin begin to toggle. The pulses on the CLIP_OTW pins report low whenever the current exceeds
the detection threshold, and the pin remains low until the current no longer exceeds the threshold. The
minimum low-pulse period that one can expect is equal to one period of the switching frequency. Having an
input signal that increases the duration of detector activation (for example, increasing the amplitude of the
input
signal)
increases
the
amount
of
time
for
which
the
pin
reports
low.
NOTE: Because tweeter detection is an alternate operating mode, place the channels to be tested in Play
mode (via register 0x0C) after tweeter detection has been activated in order to commence the detection
process. Additionally, set up the CLIP_OTW pin via register 0x0A to report the results of tweeter detection.
Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to limit
the output current flow to the average current limit (ILIM) threshold. The overall effect on the audio in the case
of a current overload is quite similar to a voltage-clipping event, temporarily limiting power at the peaks of the
musical signal and normal operation continues without disruption on removal of the overload. The
TAS5414C-Q1 and TAS5424C-Q1 do not prematurely shut down in this condition. All four channels continue
in play mode and pass signal.
2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground,
the device uses a peak-current detector, and the affected channel shuts down in 200 μs to 390 μs if the
conditions are severe enough. The shutdown speed depends on a number of factors, such as the impedance
of the short circuit, supply voltage, and switching frequency. Only the shorted channels shut down in such a
scenario. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the
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I2C fault register saves a record of the affected channels. If the supply or ground short is strong enough to
exceed the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter
prevents excess current from damaging the output FETs, and operation returns to normal after the short is
removed.
3. DC Detect—This circuit detects a dc offset at the output of the amplifier continuously during normal
operation. If the dc offset reaches the level defined in the I2C registers for the specified time period, the
circuit triggers. By default, a dc detection event does not shut the output down. Disabling and enabling the
shutdown function is via I2C. If enabled, the triggered channel shuts down, but the others remain playing, but
with the FAULT pin asserted. The I2C registers define the dc level.
4. Clip Detect—The clip detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, a signal passed to the CLIP_OTW pin asserts it until the 100% duty-
cycle PWM signal is no longer present. All four channels connect to the same CLIP_OTW pin. Through I2C,
one can change the CLIP_OTW signal clip-only, OTW-only, or both. A fourth mode, used only during
diagnostics, is the option to report tweeter detection events on this pin (see the Tweeter Detection section).
The microcontroller in the system can monitor the signal at the CLIP_OTW pin, and may have a
configuration that reduces the volume to all four channels in an active clipping-prevention circuit.
5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD) and Thermal Foldback—By
default, the CLIP_OTW pin setting indicates an OTW. One can make changes via I2C commands. If selected
to indicate a temperature warning, CLIP_OTW pin assertion occurs when the die temperature reaches
warning level 1 as shown in the electrical specifications. The OTW has three temperature thresholds with a
10°C hysteresis. I2C register 0x04 indicates each threshold in bits 5, 6, and 7. The device still functions until
the temperature reaches the OTSD threshold, at which time the outputs go into Hi-Z mode and the device
asserts the FAULT pin. I2C is still active in the event of an OTSD, and one can read the registers for faults,
but all audio ceases abruptly. After the OTSD resets, one can turn the device back on through I2C. The OTW
indication remains until the temperature drops below warning level 1. The thermal foldback decreases the
channel gain.
6. Undervoltage (UV) and Power-on-Reset (POR)—The undervoltage (UV) protection detects low voltages on
PVDD, AVDD, and CP. In the event of an undervoltage, the device asserts the FAULT pin and updates the
I2C registerd, depending on which voltage caused the event. Power-on reset (POR) occurs when PVDD
drops low enough. A POR event causes the I2C to go into a high-impedance state. After the device recovers
from the POR event, the device re-initialization occur via I2C.
7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches
the overvoltage threshold, the device asserts the FAULT pin iand updates the I2C register. The device can
withstand 50-V load-dump voltage spikes.
Power Supply
A car battery that can have a large voltage range most commonly provides the power for the device. PVDD is a
filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate driver. The supply for
the high-side FET gate driver comes from a charge pump (CP). The charge pump supplies the gate-drive voltage
for all four channels. AVDD, provided by an internal linear regulator powers the analog circuitry. This supply
requires 0.1-μF, 10-V external bypass capacitor at the A_BYP pin. TI recommends not connecting any external
components except the bypass capacitor to this pin. DVDD, which comes from an internal linear regulator,
powers the digital circuitry. The D_BYP pin requires a 0.1-μF, 10-V external bypass capacitor. TI recommends
not connecting any external components except the bypass capacitor to this pin.
The TAS5414C-Q1 and TAS5424C-Q1 can withstand fortuitous open-ground and -power conditions. Fortuitous
open ground usually occurs when a speaker wire shorts to ground, allowing for a second ground path through
the body diode in the output FETs. The diagnostic capability allows debugging of the speakers and speaker
wires, eliminating the need to remove the amplifier to diagnose the problem.
I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions
and detections are via I2C. There are also numerous features and operating conditions that one can set via I2C.
The I2C bus allows control of the following configurations:
•
Independent gain control of each channel. The gain can be set to 12 dB, 20 dB, 26 dB, and 32 dB.
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•
•
•
•
•
•
•
Select the AM non-interference switching frequency
Select the functionality of the OTW_CLIP pin
Enable or disable the dc-detect function with selectable threshold
Place a channel in Hi-Z (switching stopped) mode (mute)
Select tweeter detect, set the detection threshold, and initiate the function
Initiate the open- and shorted-load diagnostic
Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the TAS5414C-Q1 and the TAS5424C-Q1 include
a single pin that allows up to four devices to work together in a system with no additional hardware required for
communication or synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the
I2C address for that device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2,
and to D_BYP for slave 3. The OSC_SYNC pin is for synchronizing the internal clock oscillators, thereby avoid
beat frequencies. One can apply an external oscillator to this pin for external control of the switching frequency.
Table 2. Table 7. I2C_ADDR Pin Connection
I2C_ADDR VALUE
0 (OSC MASTER)
I2C_ADDR PIN CONNECTION
I2C ADDRESSES
0xD8/D9
To SGND pin
1 (OSC SLAVE1)
2 (OSC SLAVE2)
3 (OSC SLAVE3)
35% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
65% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
To D_BYP pin
0xDA/DB
0xDC/DD
0xDE/DF
(1) TI recommends RI2C_ADDR resistors with 5% or better tolerance.
I2C Bus Protocol
The TAS5414C-Q1 and TAS5424C-Q1 have a bidirectional serial control interface that is compatible with the
Inter IC (I2C) bus protocol and supports 400-kbps data transfer rates for random and sequential write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface programs the registers of the device and reads device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A
HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data-
bit transitions must occur within the low time of the clock period. Figure 15 shows these conditions. The master
generates the 7-bit slave address and the read/write bit to open communication with another device and then
wait for an acknowledge condition. The TAS5414C-Q1 and TAS5424C-Q1 hold SDA LOW during the
acknowledge-clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. There must be an external
pullup resistor for the SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of
bytes that one can transmit between start and stop conditions. When the last word transfers, the master
generates a stop condition to release the bus.
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8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
Figure 15. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are
licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the
TAS5414C-Q1 and the TAS5424C-Q1, the I2C master uses addresses shown in Figure 15. Transmission of read
and write data can be via single-byte or multiple-byte data transfers.
Random Write
As shown in Figure 16, a random write or single-byte write transfer begins with the master device transmitting a
start condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a single-byte write data transfer, the read/write bit is a 0. After receiving the
correct I2C device address and the read/write bit, the device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the internal memory address being accessed. After
receiving the address byte, the device again responds with an acknowledge bit. Next, the master device
transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the
TAS5414C-Q1 or TAS5424C-Q1 again responds with an acknowledge bit. Finally, the master device transmits a
stop condition to complete the single-byte write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-01
Figure 16. Random-Write Transfer
Sequential Write
A sequential write transfer is identical to a single-byte data-write transfer except for the transmisson of multiple
data bytes by the master device to TAS5414C-Q1 or TAS5424C-Q1 as shown in Figure 17. After receiving each
data byte, the device responds with an acknowledge bit and automatically increments the I2C subaddress by
one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
Figure 17. Sequential Write Transfer
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Random Read
As shown in Figure 18, a random read or single-byte read transfer begins with the master device transmitting a
start condition followed by the I2C device address and the read/write bit. For the single-byte read transfer, the
master device transmits both a write followed by a read. Initially, a write transfers the address byte or bytes of
the internal memory address to be read. Thus, the read/write bit is a 0. After receiving the address and the
read/write bit, the TAS5414C-Q1 or TAS5424C-Q1 responds with an acknowledge bit. In addition, after sending
the internal memory address byte or bytes, the master device transmits another start condition followed by the
device address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After
receiving the address and the read/write bit, the device again responds with an acknowledge bit. Next, the
TAS5414C-Q1 or TAS5424C-Q1 transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
Figure 18. Random Read Transfer
Sequential Read
A sequential read transfer is identical to a single-byte read transfer except for the transmission of multiple data
bytes by the TAS5414C-Q1 or TAS5424C-Q1 to the master device as shown in Figure 19. Except for the last
data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I2C subaddress by one. After receiving the last data byte, the master device transmits a not-
acknowledge followed by a stop condition to complete the transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 19. Sequential Read Transfer
20
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Table 3. TAS5414C-Q1 and TAS5424C-Q1 I2C Addresses
SELECTABLE WITH
ADDRESS PIN
READ/WRITE
BIT
I2C
ADDRESS
FIXED ADDRESS
I2C_ADDR VALUE
MSB
6
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
0
0
4
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
LSB
0
0 (OSC MASTER)
1 (OSC SLAVE1)
2 (OSC SLAVE2)
3 (OSC SLAVE3)
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
1
1
1
1
1
1
1
1
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
1
0
1
0
1
0
1
Table 4. I2C Address Register Definitions
ADDRESS
0x00
TYPE
Read
REGISTER DESCRIPTION
Latched fault register 1, global and channel fault
Latched fault register 2, dc offset and overcurrent detect
Latched diagnostic register 1, load diagnostics
Latched diagnostic register 2, load diagnostics
External status register 1, temperature and voltage detect
External status register 2, Hi-Z and low-low state
External status register 3, mute and play modes
External status register 4, load diagnostics
0x01
Read
0x02
Read
0x03
Read
0x04
Read
0x05
Read
0x06
Read
0x07
Read
0x08
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
–
External control register 1, channel gain select
External control register 2, overcurrent control
External control register 3, switching frequency and clip pin select
External control register 4, load diagnostic, master mode select
External control register 5, output state control
External control register 6, output state control
Not used
0x09
0x0A
0x0B
0x0C
0x0D
0x0E, 0x0F
0x10
Read, Write
Read
External control register 7, dc detect threshold selection
0x13
External status register 5, overtemperature shutdown and thermal foldback
Table 5. Fault Register 1 (0x00) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overtemperature warning has occurred.
DC offset has occurred in any channel.
Overcurrent shutdown has occurred in any channel.
Overtemperature shutdown has occurred.
Charge-pump undervoltage has occurred.
AVDD, analog voltage, undervoltage has occurred.
PVDD undervoltage has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
PVDD overvoltage has occurred.
Table 6. Fault Register 2 (0x01) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overcurrent shutdown channel 1 has occurred.
–
–
–
–
–
–
–
1
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Table 6. Fault Register 2 (0x01) Protection (continued)
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
1
D0
–
FUNCTION
Overcurrent shutdown channel 2 has occurred.
Overcurrent shutdown channel 3 has occurred.
Overcurrent shutdown channel 4 has occurred.
DC offset channel 1 has occurred.
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
DC offset channel 2 has occurred.
–
1
–
–
–
–
–
–
DC offset channel 3 has occurred.
1
–
–
–
–
–
–
–
DC offset channel 4 has occurred.
Table 7. Diagnostic Register 1 (0x02) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 1 has occurred.
Output short to PVDD channel 1 has occurred.
Shorted load channel 1 has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 1 has occurred.
–
–
–
1
–
–
–
–
Output short to ground channel 2 has occurred.
Output short to PVDD channel 2 has occurred.
Shorted load channel 2 has occurred.
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 2 has occurred.
Table 8. Diagnostic Register 2 (0x03) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 3 has occurred.
Output short to PVDD channel 3 has occurred.
Shorted load channel 3 has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 3 has occurred.
–
–
–
1
–
–
–
–
Output short to ground channel 4 has occurred.
Output short to PVDD channel 4 has occurred.
Shorted load channel 4 has occurred.
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 4 has occurred.
Table 9. External Status Register 1 (0x04) Fault Detection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults are present, default value.
PVDD overvoltage fault is present.
PVDD undervoltage fault is present.
AVDD, analog voltage fault is present.
Charge-pump voltage fault is present.
Overtemperature shutdown is present.
Overtemperature warning
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
0
0
1
–
–
–
–
–
0
1
1
–
–
–
–
–
Overtemperature warning level 1
1
0
1
–
–
–
–
–
Overtemperature warning level 2
1
1
1
–
–
–
–
–
Overtemperature warning level 3
22
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TAS5424C-Q1
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Table 10. External Status Register 2 (0x05) Output State of Individual Channels
D7
0
D6
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
FUNCTION
0
–
–
–
–
–
–
1
–
Output is in Hi-Z mode, not in low-low mode(1), default value.
–
–
–
–
–
–
0
Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
0
–
Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
0
–
–
Channel 3 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
0
–
–
–
Channel 4 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
1
–
–
–
–
Channel 1 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 2 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 3 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 4 low-low mode (0 = not low-low, 1 = low-low)(1)
–
1
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
(1) Low-low is defined as both outputs actively pulled to ground.
Table 11. External Status Register 3 (0x06) Play and Mute Modes
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Mute mode is disabled, play mode disabled, default value, (Hi-Z mode).
Channel 1 play mode is enabled.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 play mode is enabled.
–
–
–
–
–
1
–
–
Channel 3 play mode is enabled.
–
–
–
–
1
–
–
–
Channel 4 play mode is enabled.
–
–
–
1
–
–
–
–
Channel 1 mute mode is enabled.
–
–
1
–
–
–
–
–
Channel 2 mute mode is enabled.
–
1
–
–
–
–
–
–
Channel 3 mute mode is enabled.
1
–
–
–
–
–
–
–
Channel 4 mute mode is enabled.
Table 12. External Status Register 4 (0x07) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No channels are set in load diagnostics mode, default value.
Channel 1 is in load diagnostics mode.
Channel 2 is in load diagnostics mode.
Channel 3 is in load diagnostics mode.
Channel 4 is in load diagnostics mode.
Channel 1 is in overtemperature foldback.
Channel 2 is in overtemperature foldback.
Channel 3 is in overtemperature foldback.
Channel 4 is in overtemperature foldback.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Table 13. External Control Register 1 (0x08) Gain Select
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
0
FUNCTION
Set gain for all channels to 26 dB, default value.
Set channel 1 gain to 12 dB.
–
–
–
–
–
–
0
0
–
–
–
–
–
–
0
1
Set channel 1 gain to 20 dB.
–
–
–
–
–
–
1
1
Set channel 1 gain to 32 dB.
–
–
–
–
0
0
–
–
Set channel 2 gain to 12 dB.
–
–
–
–
0
1
–
–
Set channel 2 gain to 20 dB.
–
–
–
–
1
1
–
–
Set channel 2 gain to 32 dB.
–
–
0
0
–
–
–
–
Set channel 3 gain to 12 dB.
–
–
0
1
–
–
–
–
Set channel 3 gain to 20 dB.
–
–
1
1
–
–
–
–
Set channel 3 gain to 32 dB.
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
www.ti.com
Table 13. External Control Register 1 (0x08) Gain Select (continued)
D7
0
D6
0
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
Set channel 4 gain to 12 dB.
Set channel 4 gain to 20 dB.
Set channel 4 gain to 32 dB.
0
1
–
–
–
–
–
–
1
1
–
–
–
–
–
–
Table 14. External Control Register 2 (0x09) Overcurrent Control
D7
1
D6
1
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
FUNCTION
Current limit level 2 for all channels, thermal foldback is active.
Disable thermal foldback
–
–
–
–
–
–
–
1
–
–
–
0
–
–
–
–
Set channel 1 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 2 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 3 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 4 overcurrent limit ( 0 - level 1, 1 - level 2)
Reserved
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
1
1
1
–
Table 15. External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
1
1
0
1
Set fS = 417 kHz, report clip and OTW, 45° phase, disable hard stop,
CLIP_OTW pin does not report thermal foldback.
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0
0
1
–
–
–
1
–
–
–
0
1
0
–
–
–
–
0
1
1
–
–
–
–
–
–
–
0
0
1
–
–
–
–
–
–
–
Set fS = 500 kHz
Set fS = 357 kHz
Invalid frequency selection (do not set)
Configure CLIP_OTW pin to report tweeter detect only.
Configure CLIP_OTW pin to report clip detect only.
Configure CLIP_OTW pin to report overtemperature warning only.
Enable hard-stop mode.
Set fS to a 180° phase difference between adjacent channels.
Send sync pulse from OSC_SYNC pin (device must be in master mode).
Configure CLIP_OTW pin to report thermal foldback
Table 16. External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
0
1
0
0
0
0
Clock output disabled, master clock mode, dc detection enabled, load
diagnostics disabled
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Run channel 1 load diagnostics
Run channel 2 load diagnostics
Run channel 3 load diagnostics
Run channel 4 load diagnostics
Disable dc detection on all channels
Enable tweeter-detect mode
Enable slave mode (external oscillator is necessary)
Enable clock output on OSC_SYNC pin (valid only in master mode)
Table 17. External Control Register 5 (0x0C) Output Control
D7
0
D6
0
D5
0
D4
1
D3
1
D2
1
D1
1
D0
1
FUNCTION
All channels, Hi-Z, mute, reset disabled, dc detect is enabled
Set channel 1 to mute mode, non-Hi-Z
–
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
Set channel 2 to mute mode, non-Hi-Z
24
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TAS5424C-Q1
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Table 17. External Control Register 5 (0x0C) Output Control (continued)
D7
–
D6
D5
–
D4
–
D3
–
D2
0
D1
–
D0
–
FUNCTION
Set channel 3 to mute mode, non-Hi-Z
–
–
–
–
1
–
–
–
–
0
–
–
–
Set channel 4 to mute mode, non-Hi-Z
Set non-Hi-Z channels to play mode, (unmute)
DC detect shutdown disabled, but still reports a fault
Reserved
–
–
0
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
Reset device
Table 18. External Control Register 6 (0x0D) Output Control
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Low-low state disabled, all channels
–
–
–
–
–
–
–
1
Set channel 1 to low-low state
–
–
–
–
–
–
1
–
Set channel 2 to low-low state
–
–
–
–
–
1
–
–
Set channel 3 to low-low state
–
–
–
–
1
–
–
–
Set channel 4 to low-low state
–
–
–
1
–
–
–
–
Connect channel 1 and channel 2 for parallel BTL mode
Connect channel 3 and channel 4 for parallel BTL mode
Reserved
–
–
1
–
–
–
–
–
1
1
–
–
–
–
–
–
Table 19. External Control Register 7 (0x10) Miscellaneous Selection
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
1
Normal speed CM ramp, normal S2P & S2G timing, no delay between
LDG phases, Crosstalk Enhancement Disabled, Default DC detect value
(1.6V)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
1
–
–
–
1
–
–
0
1
–
–
–
0
0
–
–
–
Minimum DC detect value (0.8 V)
Maximum DC detect value (2.4 V)
Enable crosstalk enhancement
Adds a 20-ms delay between load diagnostic phases
Short-to-power (S2P) and short-to-ground (S2G) load-diagnostic phases
take 4x longer
–
–
1
–
1
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Slow common-mode ramp, increase the default time by 3x
Reserved
Slower common-mode (CM) ramp-down from mute mode
Table 20. External Status Register 5 (0x13) Overtemperature and Thermal Foldback Status
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Default overtemperature foldback status, no channel is in foldback
Channel 1 in thermal foldback
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 in thermal foldback
–
–
–
–
–
1
–
–
Channel 3 in thermal foldback
–
–
–
–
1
–
–
–
Channel 4 in thermal foldback
–
–
–
1
–
–
–
–
Channel 1 in overtemperature shutdown
Channel 2 in overtemperature shutdown
Channel 3 in overtemperature shutdown
Channel 4 in overtemperature shutdown
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
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TAS5414C-Q1
TAS5424C-Q1
SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
www.ti.com
Hardware Control Pins
There are four discrete hardware pins for real-time control and indication of device status.
FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition that requires the
device to go into the Hi-Z mode or standby mode. On assertion of this pin, the device has protected itself and
the system from potential damage. One can read the exact nature of the fault via I2C with the exception of
PVDD undervoltage faults below POR, in which case the I2C bus is no longer operational. However, the fault
is still indicated due to FAULT pin assertion.
CLIP_OTW pin: Configured via I2C, this active-low open-drain pin\ indicates one of the following conditions:
overtemperature warning, the detection of clipping, or the logical OR of both of these conditions. During
tweeter detect diagnostics, assertion of this pin also occurs when a tweeter is present. If overtemperature
warning is set, the device can indicate thermal foldback on this pin too.
MUTE pin: This active-low pin is used for hardware control of the mute-unmute function for all four channels.
Capacitor CMUTE controls the time constant for the gain ramp needed to produce a pop- and click-free mute
function. For pop- and click-free operation, implementation of the mute function should be through I2C
commands. The use of a hard mute with an external transistor does not ensure pop- and click-free operation,
and TI does not recommended it except as an emergency hard mute function in case of a loss of I2C control.
Sharing the CMUTE capacitor between multiple devices is disallowed.
STANDBY pin: On assertion of this active-low pin, the device goes into a complete shutdown, and the typical
current-draw limit is 2 μA, typical. STANDBY can be used to shut down the device rapidly. If all channels are
in Hi-Z, the device enters standby in approximately 1 ms; if, not a quick ramp-down occurs that takes
approximately 20 ms. The outputs ramp down quickly if not already in Hi-Z, so externally biasing the MUTE
pin prevents the device from entering standby. All I2C register content is lost and the I2C bus goes into the
high-impedance state on assertion of the STANDBY pin.
EMI Considerations
Automotive-level EMI performance depends on both careful integrated circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The phase between channels is I2C selectable to either 45° or 180°, to reduce EMI caused by
high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI.
AM Radio Avoidance
To reduce interference in the AM radio band, the device has the ability to change the switching frequency via I2C
commands. Table 21 lists the recommended frequencies. The fundamental frequency and its second harmonic
straddle the AM radio band listed. This eliminates the tones that can be present due to demodulation of the
switching frequency by the AM radio.
Table 21. Recommended Switching Frequencies for AM Mode Operation
US
EUROPEAN
SWITCHING
FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
540–670
680–980
417
500
417
500
417
500
522–675
676–945
417
500
417
500
417
500
990–1180
1190–1420
1430–1580
1590–1700
946–1188
1189–1422
1423–1584
1585–1701
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Operating Modes and Faults
The following tables depict the operating modes and faults.
Table 22. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z, floating
CHARGE PUMP
Stopped
OSCILLATOR
Stopped
I2C
AVDD and DVDD
Stopped
Active
Active
Active
OFF
ON
ON
ON
Hi-Z, weak pulldown
Switching at 50%
Switching with audio
Active
Active
Active
Active
Active
Active
Mute
Normal operation
Table 23. Global Faults and Actions
FAULT OR
EVENT
CATEGORY
LATCHED OR
SELF-
CLEARING
FAULT OR
EVENT
MONITORING
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
MODES
POR
UV
Voltage fault
All
FAULT pin
I2C + FAULT pin
Hard mute (no ramp)
Standby
Hi-Z
Self-clearing
Latched
Hi-Z, mute, normal
CP UV
OV
Load dump
All
FAULT pin
Standby
None
Self-clearing
Self-clearing
Latched
OTW
Thermal warning
Thermal fault
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + CLIP_OTW pin
I2C + FAULT pin
None
OTSD
Hard mute (no ramp)
Standby
Table 24. Channel Faults and Actions
LATCHED OR
SELF-
CLEARING
FAULT/
EVENT
FAULT OR EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
Open-short
diagnostic
Diagnostic
Hi-Z (I2C activated)
I2C
None
None
Latched
Clipping
Warning
Mute / Play
CLIP_OTW pin
None
None
Self-clearing
Self-clearing
CBC load current
limit
Online protection
Current Limit
Start OC
timer
OC fault
DC detect
Output channel fault
Warning
I2C + FAULT pin
Hard mute
Hard mute
Hi-Z
Hi-Z
Latched
Latched
OT Foldback
I2C + CLIP_OTW
pin
Reduce Gain
None
Self-clearing
Audio Shutdown and Restart Sequence
The gain ramp of the filtered output signal and the updating of the I2C registers correspond to the MUTE pin
voltage during the ramping process. The value of the external capacitor on the MUTE pin dictates the length of
time that the MUTE pin takes to complete its ramp. With the default 220-nF capacitor, the turnon common-mode
ramp takes approximately 26 ms and the gain ramp takes approximately 76 ms.
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tCM
tCM
tGAIN
tGAIN
HIZ_Report_x
(All Channels)
LOW_LOW_Report_x
(All Channels)
MUTE_Report_x
(All Channels)
PLAY_Report_x
MUTE Pin
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
T0192-02
Figure 20. Timing Diagram for Click- and Pop-Free Shutdown and Restart Sequence
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Latched-Fault Shutdown and Restart Sequence Control
tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
VUV
PVDD UV Hysteresis Region
VPOR
HIZ_x
Internal I2C Write
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
OUTx_P (Filtered)
T0194-02
Figure 21. Timing Diagram for Latched-Global-Fault Shutdown and Restart
(UV Shutdown and Recovery)
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www.ti.com
tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
PVDD UV Hysteresis Region
VUV
VPOR
Internal I2C Write
HIZ_Report_1
HIZ_Report_2,3,4
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
Pop
Pop
OUT1_P (Filtered)
OUT2,3,4_P (Filtered)
T0195-02
Figure 22. Timing Diagram for Latched-Global-Fault Shutdown and Individual-Channel Restart
(UV Shutdown and Recovery)
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
APPLICATION INFORMATION
Figure 23. TAS5414C-Q1 Typical Application Schematic
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www.ti.com
Parallel Operation (PBTL)
The device can drive more current by paralleling BTL channels on the load side of the LC output filter. Parallel
operation requires identical I2C settings for any two paralleled channels in order to have reliable system
performance and even power dissipation on multiple channels. For smooth power up, power down, and mute
operation, the same control commands (such as mute, play, Hi-Z, and so on) should be sent to the paralleled
channels at the same time. The device also supports load diagnostics for parallel connection. There is no support
for paralleling on the device side of the LC output filter, which can result in device failure. When paralleling
channels, use the parallel BTL I2C control bits in register 0x0D. Parallel channels 1 and 2, and/or channels 3 and
4. Setting these bits allows the thermal foldback to react on both channels equally.
Input Filter Design
For the TAS5424C-Q1 device, the input filters for the P and M inputs of a single channel should be identical. For
the TAS5414C-Q1, the IN_M pin should have an impedance to GND that is equivalent to the parallel combination
of the input impedances of all IN_P channels combined, including any source impedance from the previous stage
in the system design. For example, if each of the four IN_P channels have a 1-µF dc blocking capacitor, 1 kΩ of
series resistance due to an input RC filter, and 1 kΩ of source resistance from the DAC supplying the audio
signal, then the IN_M channel should have a 4-µF capacitor in series with a 500-Ω resistor to GND (4 × 1 µF in
parallel = 4 µF; 4 × 2 kΩ in parallel = 500 Ω).
Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. TI recommends the use of a second-order LC filter to recover
the audio signal. The main purpose of the demodulation filter is to attenuate the high-frequency components of
the output signals that are out of the audio band. Design of the demodulation filter significantly affects the audio
performance of the power amplifier. Therefore, to meet the system THD+N needs, carefully consider the
selection of the inductors used in the output filter. The rule is that the inductance should stay above 10% of the
inductance value within the range of peak current seen at maximum output power in the system design.
Line Driver Applications
In many automotive audio applications, the end user would like to use the same head unit to drive either a
speaker (with several ohms of impedance) or an external amplifier (with several kilohms of impedance). The
design is capable of supporting both applications; however, the one must design the output filter and system to
handle the expected output load conditions.
Thermal Information
The design of the thermally augmented package is for interface directly to heat sinks using a thermal interface
compound (for example, Arctic Silver, Ceramique thermal compound). The heat sink then absorbs heat from the
ICs and couples it to the local air. With proper thermal management this process can reach equilibrium at a lower
temperature and heat can be continually removed from the ICs. Because of the device efficiency, heat sinks can
be smaller than those required for linear amplifiers of equivalent performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
•
•
•
RθJC (the thermal resistance from junction to case, or in this case the heat slug)
Thermal resistance of the thermal grease
Thermal resistance of the heat sink
One can calculate the thermal resistance of the thermal grease from the exposed heat slug area and the
manufacturer's value for the area thermal resistance of the thermal grease (expressed in °C-in2/W or °C-mm2/W).
The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about
0.007°C-in2/W (4.52°C-mm2/W). The approximate exposed heat slug size is as follows:
44-pin PSOP3
64-pin QFP
0.124 in2 (80 mm2)
0.099 in2 (64 mm2)
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SLOS795C –SEPTEMBER 2013–REVISED JULY 2013
Dividing the example area thermal resistance of the thermal grease by the area of the heat slug gives the actual
resistance through the thermal grease for both parts:
44-pin PSOP3
64-pin QFP
0.06°C/W
0.07°C/W
The thermal resistance of thermal pads is generally considerably higher than a thin thermal-grease layer.
Thermal tape has an even higher thermal resistance and should not be used at all. The heat-sink vendor
generally predicts heat sink thermal resistance, either modeled using a continuous-flow dynamics (CFD) model,
or measured.
Thus, for a single monaural channel in the IC, the system RθJA = RθJC + thermal-grease resistance + heat-sink
resistance.
The following table indicates modeled parameters for one device on a heat sink. The junction temperature setting
is at 115°C while delivering 20 watts per channel into 4-Ω loads with no clipping. The assumed thickness of the
thermal grease is about 0.001 inches (0.0254 mm).
Device
Ambient temperature
64-Pin QFP
25°C
Power to load
20 W × 4
1.9 W × 4
7.6°C
Power dissipation
ΔT inside package
ΔT through thermal grease
Required heatsink thermal resistance
Junction temperature
System RθJA
0.46°C
10.78°C/W
115°C
11.85°C/W
90°C
RθJA × power dissipation
Electrical Connection of Heat Slug and Heat Sink
Electrically connect the heat sink attached to the heat slug of the device to GND, or leave it floating. Do not
connect the heat slug to any other electrical node.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2013
PACKAGING INFORMATION
Orderable Device
TAS5414CTPHDRQ1
TAS5424CTDKERQ1
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
HTQFP
HSSOP
PHD
64
44
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
TAS5414CTQ1
PREVIEW
DKE
500
Green (RoHS
& no Sb/Br)
Level-3-245C-168 HR
-40 to 105
TAS5424CQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5414CTPHDRQ1
HTQFP
PHD
64
1000
330.0
24.4
17.0
17.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHD 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TAS5414CTPHDRQ1
1000
Pack Materials-Page 2
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