TAS3204PAGR [TI]
AUDIO DSP WITH ANALOG INTERFACE; 音频DSP与模拟接口
| 型号： | TAS3204PAGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AUDIO DSP WITH ANALOG INTERFACE |
| 文件： | 总72页 (文件大小：1211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
1 Introduction
1.1 Features
•
•
•
•
•
•
•
48-Bit Data Path and 28-Bit Coefficients
•
High-Quality Audio Performance:
102-dB ADC/105-dB DAC (Typical) DNR
768 Words of 48-Bit Data Memory
1022 Words of 28-Bit Coefficient Memory
3K Words of 55-Bit Program RAM
Hardware Single-Cycle Multiplier (28×48)
2812 Instructions Per Fs
•
Eight-Channel Programmable Audio DSP
(Four-Channel Digital and Four-Channel
Analog)
•
Three Differential Stereo Analog Inputs
Multiplexed to Two Stereo Input ADCs
5.88K Words of 24-Bit Delay Memory
(122.5 ms at 48 kHz)
•
•
Two Differential Stereo Output DACs
Two Serial Audio Inputs (Four Channels) and
Two Serial Audio Outputs (Four Channels)
•
Data Formats: Left Justified, Right Justified,
and I2S
Two I2C Ports for Slave or Master Download
•
•
135-MHz Maximum Speed, >2800 Processing
Cycles Per Sample at 48 kHz
•
•
•
Single 3.3-V Power Supply
512×Fs XTAL Input in Master Mode,
512×Fs MCLK_IN in Slave Mode
Graphical Development Environment Provided
for Audio Processing; e.g., EQ, Algorithm
Development, Etc.
•
•
48-kHz Sample Rate in Master Mode
44.1 or 48-kHz Sample Rate in Slave Mode
1.2 Applications
•
•
•
MP3 Docking Systems
Digital Televisions
Mini-Component Audio
TAS3204
SDIN1
SDIN2
4
2
Digital Audio
Processor Core
Output
SAP
Input
SAP
4
2
SDOUT1
SDOUT2
2
2
2
48-Bit Data Path
28-Bit Coefficients
76-Bit MAC
Differential
Analog
In
Stereo
ADC
Stereo
DAC
2
2
2
2
Differential
Analog
Out
3K Code RAM
1K Upper Data RAM
768 Lower Data RAM
1.2K Coeff. RAM
Boot ROM
2
Stereo
ADC
Stereo
DAC
2
MCLK_IN
LRCLK_IN
Volume
Update
PLL
and
Clock
Control
SCLK_IN
8051 MCU
8-Bit Microprocessor
3
MCLK_OUTx
LRCLK_OUT
SCLK_OUT
256 IRAM
2K ERAM
I2C Port #1
I2C Port #2
16K Code RAM
10K Code ROM
I2C
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
Contents
Introduction ............................................... 1
1
2
8.1 Absolute Maximum Ratings ......................... 37
8.2 Package Dissipation Ratings........................ 37
8.3 Recommended Operating Conditions............... 37
8.4 Electrical Characteristics ............................ 38
8.5 Audio Specifications................................. 38
8.6 Timing Characteristics............................... 41
8.6.1 Master Clock ....................................... 41
1.1 Features .............................................. 1
1.2 Applications........................................... 1
Functional Description ................................. 3
2.1 Analog Input/MUX/Stereo ADCs ..................... 4
2.2 Stereo DACs.......................................... 4
2.3 Analog Reference System............................ 4
2.4 Power Supply......................................... 4
8.6.2 Serial Audio Port, Slave Mode..................... 42
8.6.3 Serial Audio Port Master Mode Signals
2.5
Clocks, Digital PLL, and Serial Data Interface ....... 4
(TAS3204)........................................... 43
8.6.4 Pin-Related Characteristics of the SDA and SCL
I/O Stages for F/S-Mode I2C-Bus Devices.......... 44
2.6 I2C Control Interface.................................. 6
2.7 8051 Microcontroller ................................. 6
2.8 Audio Digital Signal Processor Core ................. 6
Physical Characteristics ............................... 7
3.1 Terminal Assignments ................................ 7
3.2 Ordering Information.................................. 7
3.3 Terminal Descriptions ................................ 8
3.4 Reset (RESET) - Power-Up Sequence ............. 10
3.5 Voltage Regulator Enable (VREG_EN) ............. 10
3.6 Power-On Reset (RESET) .......................... 10
3.7 Power Down (PDN) ................................. 10
3.8 I2C Bus Control (CS0)............................... 11
3.9 Programmable I/O (GPIO) .......................... 11
3.10 Input and Output Serial Audio Ports ................ 12
8.6.6 Reset Timing........................................ 46
I2C Register Map........................................ 47
9.1 Clock Control Register (0x00) ...................... 48
9.2 Microcontroller Clock Control Register.............. 48
9.3 Status Register (0x02) .............................. 49
3
9
9.4
I2C Memory Load Control and Data Registers (0x04
and 0x05)............................................ 50
9.5
Memory Access Registers (0x06 and 0x07) ........ 51
9.6 Device Version (0x08)............................... 52
9.7
Analog Power Down Control (0x10 and 0x11),
ESFR (0xE1 and 0xE2) ............................. 52
9.8
9.9
Analog Input Control (0x12), ESFR (0xE3) ......... 53
Dynamic Element Matching (0x13), ESFR (0XE4).. 53
4
Algorithm and Software Development Tools for
TAS3204.................................................. 18
9.10 Current Control Select (0x14, 0x15, 0x17, 0x18),
ESFR (0xE5, 0xE6, 0xE7, 0xE9).................... 54
9.11 DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB,
5
6
Clock Controls .......................................... 19
Microprocessor Controller .......................... 21
0xEC, 0xEE)......................................... 58
6.1
8051 Microprocessor Addressing Mode ............ 22
9.12 ADC and DAC Reset (0x1E), ESFR (0xFB) ........ 60
9.13 ADC Input Gain Control (0x1F), ESFR (0xFA)...... 60
9.14 MCLK_OUT Divider (0x21 and 0x22) ............... 61
9.15 Digital Cross Bar (0x30 to 0x3F) .................... 61
9.16 Extended Special Function Registers (ESFR) Map. 63
6.2 General I2C Operations ............................. 23
6.3 I2C Slave Mode Operation .......................... 24
6.4 I2C Master-Mode Device Initialization .............. 27
Digital Audio Processor (DAP) Arithmetic Unit . 33
7.1 DAP Instructions Set ................................ 34
7.2 DAP Data Word Structure........................... 35
Electrical Specifications .............................. 37
7
8
10 Application Information............................... 68
10.1 Schematics .......................................... 68
10.2 Recommended Oscillator Circuit.................... 69
2
Contents
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
2 Functional Description
The TAS3204 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker,
and MP3 player docking systems. It includes analog interface functions: three multiplex (MUX) stereo
inputs with two stereo analog-to-digital converters (ADCs), two stereo digital-to-analog converters (DACs)
with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio
processing are also provided. The TAS3204 has a programmable audio digital signal processor (DSP) that
preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle
28×48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM.
The TAS3204 is composed of eight functional blocks:
1. Analog input/mux/stereo ADC
2. Two stereo DACs
3. Analog reference system
4. Power supply
5. Clocks, digital pll, and serial data interface
6. I2C control interface
7. 8051 microcontroller
8. Audio DSP – digital audio processing
DPLL
Master/Slave
Oscillator
512Fs XTAL
SCL1/SDA1
SCL2/SDA2
8051 Microprocessor Core
Control
I2C
Control
Interface
Registers
External
RAM 2K
MCLK_IN
512Fs
8-Bit
MCU
GPIO1/2
Internal
Slave
RAM 256
Volume
Update
Code
Clock
Divider
RAM 16K
LRCLK_IN
SCLK_IN
Clock
Generation
DSP
Control
Memory
Interface
DSP Core
LRCLK_OUT
SCLK_OUT
Coefficient
RAM 1.2K
Serial Audio Port
Input
Cross
Bar
Data RAM
1K Upper Mem
768 Lower Mem
Code
SDIN1/2
Data
Path
Mixer
Output Cross
SDOUT1/2
Bar Mixer
RAM 3K
Two Differential
Stereo Analog
Outputs
Two Stereo
DAC
128Fs
Three
Differential
Stereo
Two Stereo
ADC
AVDD
DVDD
Power
Analog Inputs
Supply
Legend
Clocks
Internal Connection
External Connection
Digital Data
Analog Data
Figure 2-1. Expanded Functional Block Diagram
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Functional Description
3
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
2.1 Analog Input/MUX/Stereo ADCs
These modules allow three differential analog stereo inputs to be sent to either of two ADCs to be
converted to digital data. The input multiplexers include a preamplifier. This amplifier is driving the ADCs,
and it is digitally controlled with changes synchronized with the sample clock of the ADC. Minimal
crosstalk between selected channels and unselected channels is maintained. When inputs are not needed
they are configured for minimal noise. Also included in this module are two fully differential over sampled
stereo ADCs. The ADCs are sigma-delta modulators with 256 times over-sampling ratio. Because of the
over-sampling nature of the audio ADCs and integrated digital decimation filters, requirements for analog
anti-aliasing filtering are relaxed. Filter performance for the ADCs are specified under physical
characteristics.
2.2 Stereo DACs
This module includes two stereo audio DACs, each of which consists of a digital interpolation filter, digital
sigma-delta modulator and an analog reconstruction filter. Each DAC can operate a maximum of 48 kHz.
Each DAC upsamples the incoming data by 128 and performs interpolation filtering and processing on this
data before conversion to a stereo analog output signal. The sigma-delta modulator always operates at a
rate of 128Fs, which ensures that quantization noise generated within the modulator stays low within the
frequency band below Fs/2.4 at all sample rates. The digital interpolation filters for interpolation from Fs to
8×Fs are included in the audio DSP upper memory (reserved for analog processing), while interpolation
from 8×Fs to 128Fs is done in a dedicated hardware sample and hold filter. The TAS3204 includes two
stereo line driver outputs. All line drivers are capable of driving up to a 10-kΩ load. Each stereo output can
be in power-down mode when not used. Popless operation is achieved by conforming to start and stop
sequences in the device controller code.
2.3 Analog Reference System
This module provides all internal references needed by the analog modules. It also provides bias currents
for all analog blocks. External decoupling capacitors are needed along with an external 1%-tolerance
resistor to set the internal bias currents. It includes a band-gap reference and several voltage buffers and
a tracking current reference. The TAS3204 also uses an internally generated mid supply that is used to
rereference all analog inputs and is present on all analog outputs. VMID is the analog mid supply and can
be used when buffered externally to rereference the analog inputs and outputs. The voltage reference
REXT requires a 22-kΩ 1% resistor to ground. The reference system can be powered down separately.
2.4 Power Supply
The power supply contains supply regulators that provide analog and digital regulated power for various
sections of the TAS3204. Only one external 3.3-V supply is required. All other voltages are generated on
chip from the external 3.3-V supply.
2.5 Clocks, Digital PLL, and Serial Data Interface
These modules provide the timing and serial data interface for the TAS3204. The clocking system for the
device is illustrated in Figure 2-2. The TAS3204 can be either clock master or clock slave depending on
the configuration. However, master mode is the primary mode of operation.
4
Functional Description
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
DPLL
×5.5
135-MHz DCLK
Microprocessor Clock
÷4
MCLK_OUT
÷2
Programmable
Divider
MCLK_OUT2
MCLK_OUT3
Programmable
Divider
From DAP
Parallel
Data
Serial
Audio Port
Transmitter
SDOUT
LRCLK
Re-Creation
24.576 MHz
24.576 MHz
To DAP
Parallel
Data
Serial
Audio Port
Receiver
SDIN
512Fs
Crystal
Oscillator
256Fs
128Fs
64Fs
LRCLK_OUT
SCLK_OUT
÷2
÷2
÷2
÷64
MCLKI
Master/
Slave
Figure 2-2. Clock Generation
DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends
upon the quality of the MCLK_IN. The TAS3204 is not robust with respect to MCLK_IN errors (glitches,
etc.); if the MCLK_IN frequency changes under operation, the device must be reset.
Master mode operation:
•
External 512Fs crystal oscillator is used to generate all internal clocks plus all clocks for external
asynchronous sampling rate converter (ASRC) output (if external ASRC is present).
•
•
•
LRCLK_OUT is fixed at 48 kHz (Fs).
SCLK_OUT is fixed at 64Fs.
MCLK_OUT is fixed at 256Fs. In master mode, the external ASRC converts incoming serial audio data
to 48-kHz sample rate synchronous to the internally generated serial audio data clocks.
•
In master mode, all clocks generated for the TAS3204 are derived from the 24.576-MHz crystal. The
internal oscillator drives the crystal and generates the main clock to digital PLL (DPLL), master clock
outputs, 256Fs clock to the ADC, and 128Fs clock to the DAC. The DPLL generates internal clocks for
the DAP and the 8051 microprocessor.
Slave mode operation:
•
MCLK_IN (512Fs), SCLK_IN (64Fs), and LRCLK_IN (Fs) are supplied externally. Clock generation is
similar to the master mode with the exception of the ADC and the DAC blocks. MCLK_IN signal is
divided down and sent directly to the ADC and the DAC blocks. Therefore, audio performance
depends on the MCLK_IN signal.
•
•
DSP, MCU, and I2C clocks are still derived from external crystal oscillator.
MCLK_OUT, SCLK_OUT, and LRCLK_OUT are passed through from clock inputs (MCLK_IN,
SCLK_IN, and LRCLK_IN).
•
•
Internal analog clocks for ADC and DACs are derived from external MCLK_IN input, so analog
performance depends on MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation in analog
performance is to be expected.
Sample rate change/clock change
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Functional Description
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
–
–
Sample rate change on the fly should be handled by customer system controller. The TAS3204
device does not include any internal clock error or click/pop detection/management.
Customer-specific DAP filter coefficients must be uploaded by customer system controller on
changing sample rate.
In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz
or 48 kHz.
2.6 I2C Control Interface
The TAS3204 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing
status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download
programs and data from external memory such as an EEPROM. See Section 6 for more information. I2C
interface is not 5-V tolerant.
2.7 8051 Microcontroller
The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as
requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing
cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program
cannot be altered. The microcontroller has specialized hardware for a master and slave interface
operation, volume updates, and a programmable interval-timer interrupt.
2.8 Audio Digital Signal Processor Core
The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of
an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can
include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or
third-party algorithms, is running in the DAP. The 8051 microcontroller has access to DAP resources such
as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The
primary blocks of the audio DSP core are:
•
•
•
•
•
•
48-bit data path with 76-bit accumulator
DSP controller
Memory interface
Coefficient RAM (1K×28)
Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)
Program RAM (3K×55)
The DAP is discussed in detail in the following sections.
6
Functional Description
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
3 Physical Characteristics
3.1 Terminal Assignments
PAG PACKAGE
(TOP VIEW)
1
2
3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
MCLK_OUT1
MCLK_OUT2
MCLK_OUT3
DVDD2
I2C1_SCL
I2C1_SDA
GPIO2
GPIO1
MUTE
CS0
PDN
DVSS1
DVDD1
VR_PLL
AVSSI
AIN1LP
AIN1LM
AIN1RP
AIN1RM
AIN2LP
4
5
DVSS2
MCLK_IN
XTAL_OUT
XTAL_IN
AVDD3
VR_ANA
AVSS_ESD
AVSSO
AOUT1RP
AOUT1RM
AOUT1LP
AOUT1LM
6
7
8
9
10
11
12
13
14
15
16
3.2 Ordering Information
TA
PLASTIC 64-PIN PQFP (PN)
0°C to 70°C
TAS3204PAG
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Physical Characteristics
7
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
3.3 Terminal Descriptions
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
Analog input, channel 1, left, – input
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
13
12
15
14
17
16
19
18
21
20
23
22
33
34
35
36
29
30
31
32
AIN1LM
AIN1LP
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Pull to VMID(3)
Pull to VMID(3)
Pull to VMID(3)
Pull to VMID(3)
Pull to VMID(3)
Pull to VMID(3)
Analog input, channel 1, left, + input
Analog input, channel 1, right, – input
Analog input, channel 1, right, + input
Analog input, channel 2, left, – input
Analog input, channel 2, left, + input
Analog input, channel 2, right, – input
Analog input, channel 2, right, + input
Analog input, channel 3, left, – input
Analog input, channel 3, left, + input
Analog input, channel 3, right, – input
Analog input, channel 3, right,+ input
Analog output, channel 1, left, – output
Analog output, channel 1, left, + output
Analog output, channel 1, right, – output
Analog output, channel 1, right, + output
Analog output, channel 2, left, – output
Analog output, channel 2, left, + output
Analog output, channel 2, right, – output
Analog output, channel 2, right,+ output
AIN1RM
AIN1RP
AIN2LM
AIN2LP
AIN2RM
AIN2RP
AIN3LM
AIN3LP
AIN3RM
AIN3RP
AOUT1LM
AOUT1LP
AOUT1RM
AOUT1RP
AOUT2LM
AOUT2LP
AOUT2RM
AOUT2RP
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
AVDD1
AVSS1
AVDD2
AVSS2
AVDD3
24
11
28
37
40
Power
Power
Power
Power
Power
Analog supply ground
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
Analog supply ground
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
AVSS3
CS0
38
6
Power
Analog supply ground
I2C secondary address
Digital Input
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
DVDD1
DVSS1
DVDD2
DVSS2
DVDD3
DVSS3
GPIO1
9
8
Power
Power
Digital supply ground
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
45
44
57
56
4
Power
Power
Digital supply ground
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
Power
Power
Digital supply ground
General-purpose I/O pin. When booting from internal ROM, the
TAS3204 streams audio when GPIO1 is low; otherwise it mutes.
Digital IO
Digital IO
Digital Input
GPIO2
3
General-purpose I/O pin
Slave I2C serial control data interface input/output. Normally connected
to system micro.
I2C1_SCL
1
(1) I = input; O = output
(2) All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.
(3) Pull to VMID when analog input is in single-ended mode.
8
Physical Characteristics
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TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
I2C1_SDA
2
Digital I/O
Slave I2C serial clock input. Normally connected to system micro.
Master I2C serial control data interface input/output. Normally
connected to EEPROM.
I2C2_SCL
64
Digital Input
I2C2_SDA
LRCLK_IN
63
58
51
Digital I/O
Digital Input
Digital Output
Master I2C serial clock input. Normally connected to EEPROM.
Serial data input left/right clock for I2S interface
Serial data output left/right clock for I2S interface
Pulldown
Pulldown
LRCLK_OUT
MCLK input is used in slave mode. MCLK_IN must be locked to
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).
MCLK_IN
43
48
Digital Input
MCLK_OUT1
Digital Output
12.288 MHz clock output. This output is valid even when reset is LOW.
The frequency for this clock is 6.144 MHz/(n+1) where n is programable
in the range 0 to 255. Default value is 1.024 MHz. This output is valid
even when reset is LOW.
MCLK_OUT2
47
Digital Output
The frequency for this clock is 512 kHz/(n+1) where n is programmable
in the range 0 to 255. Default value is 512 kHz. This output is valid
even when reset is LOW.
MCLK_OUT3
MUTE
46
5
Digital Output
Digital Input
This pin needs to be programmed as mute pin in the application code.
In has no function in default after reset.
Pulldown
Power down, active LOW. After successful boot, its function is defined
by the boot code.
PDN
7
Digital Input
N/A
RESERVED
RESET
50
62
Pulldown
Pullup
Connect to ground.
System reset input, active low. A system reset is generated by applying
a logic LOW to this terminal.
Digital Input
Requires a 22-kΩ (1%) external resistor to ground to set analog
currents. Trace capacitance must be kept low.
REXT
27
Analog Output
SCLK_IN
SCLK_OUT
SDIN1/GPIO3
SDIN2/GPIO4
SDOUT1
59
52
61
60
54
53
Digital Input
Digital Output
Digital I/O
Serial data input bit clock for I2S interface
Serial data output bit clock for I2S interface
Serial data input #1 for I2S interface or programmable for GPIO #3
Serial data input #2 for I2S interface or programmable for GPIO #4
Serial data output #1 for I2S interface
Pullup
Pullup
Digital I/O
Digital Output
Digital Output
SDOUT2
Serial data output #2 for I2S interface
Analog mid supply reference. This pin must be decoupled with a 0.1-µF
low-ESR capacitor and an external 10-µF filter cap.(4)
VMID
25
Analog Output
Voltage reference for analog supply. A pin-out of the internally
regulated 1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and AVSS_PLL.
This terminal must not be used to power external devices.(4)
VR_ANA
39
Power
Voltage reference for digital supply. A pin-out of the internally regulated
1.8 V power. A 0.1-µF low ESR capacitor and a 4.7-µF filter capacitor
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices.(4)
VR_DIG
VR_PLL
55
10
Power
Power
Voltage reference for DPLL supply. A pin-out of internally regulated
1.8-V power supply. A 0.1-µF low-ESR capacitor and a 4.7-µF filter
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices.(4)
Band gap output. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used
to power external devices.(4)
VREF
26
49
Analog Output
Digital Input
Voltage regulator enable. When enabled LOW, this input causes the
power-supply regulators to be enabled.
VREG_EN
XTAL_IN
41
42
Digital Input
Crystal input. A 24.576-MHz (512Fs) crystal should be used.
Crystal output.
XTAL_OUT
Digital Output
(4) If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling.
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3.4 Reset (RESET) - Power-Up Sequence
The RESET pin is an asynchronous control signal that restores all TAS3204 components to the default
configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts
initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A
reset can be initiated by applying a logic 0 on RESET.
As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus
operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain
in that state until device initialization has completed.
The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and
setting the default register values. Once these are complete, the TAS3204 enables its master I2C interface
and disables its slave I2C interface.
Using the master interface, the TAS3204 automatically tests to see if an external I2C EEPROM is at
address "1010x". The value x can be chip selects, other information, or don't care, depending on the
EEPROM selected.
If a memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 begins to load the program, coefficient and/or data memories from
the external EEPROM. If an external EEPROM is present, the download is considered complete when an
end of program header is read by the TAS3204. At this point, the TAS3204 disables the master I2C
interface, enable the slave I2C interface, and start normal operation. After a successful download, the
micro program counter is reset, and the downloaded micro and DAP application firmware controls
execution.
If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3204 disables the
master I2C interface and enables the slave I2C interface initialization to load the slave default
configuration. In this default configuration, the TAS3204 streams audio from input to output if the GPIO1
pin is asserted LOW; if the GPIO1 pin is asserted HIGH, the ADC and the DAC are muted.
Note: The master and slave interfaces do not operate simultaneously.
3.5 Voltage Regulator Enable (VREG_EN)
Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are
lost in this power down mode. A full power-up/reset/program-load sequence must be completed before the
device is operational.
3.6 Power-On Reset (RESET)
On power up, it is recommended that the TAS3204 RESET be held LOW until DVDD has reached 3.3 V.
This can be done by programming the system controller or by using an external RC delay circuit. The
1-kΩ and 1-µF values provide a delay of approximately 200 µs. The values of R and C can be adjusted to
provide other delay values as necessary.
3.7 Power Down (PDN)
The TAS3204 supports a number of power-down modes.
PDN can be used to put the device into power saving standby mode. PDN is user-firmware definable. Its
default configuration is to stop all clocks, power down all analog circuitry, and ramp down volume for all
digital inputs. This mode is used to minimize power consumption while preserving register settings. If there
is no EEPROM or if the EEPROM has an invalid image–i.e., an unsuccessful boot from the EEPROM–and
PDN is pulled low, the TAS3204 is in powerdown mode. After a successful boot, PDN is defined by the
boot code.
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Individual power down DAC and ADC – Each stereo DAC and ADC can be powered down individually. To
avoid audible artifacts at the outputs, the sequences defined in the TI document TAS3108/TAS3108IA
Firmware Programmer's Guide (SLEU067) must be followed. The control signals for these operations are
defined as ESFR. The feature is made available to the board controller via the I2C interface.
Power down of analog reference – The analog reference can be powered down if all DAC and ADC are
powered down. This operation is handled by the device controller through the ESFRs, and is made
available to the board controller via the I2C interface.
3.8 I2C Bus Control (CS0)
The TAS3204 has a control to specify the slave and master I2C address. This control permits up to two
TAS3204 devices to be placed in a system without external logic. GPIO pins are level sensitive. They are
not edge triggered.
See Section 6.3 for a complete description of this pin.
3.9 Programmable I/O (GPIO)
The TAS3204 has four GPIO pins and two general purpose input pins that are 8051 firmware
programmable.
GPIO1 and GPIO2 pins are single function I/O pins. Upon power up, GPIO1 is an input. If there is an
unsuccessful boot and GPIO1 is pulled high externally, the DAC output is disabled. If there is an
unsuccessful boot and the GPIO1 is pulled low externally, the DAC output is enabled. If there is a
successful boot, GPIO1 is pulled low by the internal microprocessor, and its function is defined by the boot
code in the EEPROM.
GPIO3 and GPIO4 pins are dual function I/O pins. These pins can be used as SDIN1 and SDIN2
respectively.
Mute and power down functions have to be programmed in the EEPROM boot code. These are
general-purpose input pins and can be programmed for functions other than mute and power down.
For more information, see the Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's
Guide (SLEU067).
3.9.1 No EEPROM is Present or a Memory Error Occurs
Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the
TAS3204 is in one of two modes, depending on the setting of GPIO1.
• GPIO1 is logic HIGH
With GPIO1 held HIGH during initialization, the TAS3204 comes up in the default configuration with the
serial data outputs not active. Once the TAS3204 has completed the default initialization procedure,
after the status register is updated and the I2C slave interface is enabled, then GPIO1 is an output and
is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can
access the TAS3204 through the I2C interface and read the status register to determine the load
status.
If a memory-read error occurs, the TAS3204 reports the error in the status register (I2C subaddress
0x02).
• GPIO1 is logic LOW
With GPIO1 held LOW during initialization, the TAS3204 comes up in an I/O test configuration. In this
case, once the TAS3204 completes its default test initialization procedure, the status register is
updated, the I2C slave interface is enabled, and the TAS3204 streams audio unaltered from input to
output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc.
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In this configuration, GPIO1 is an output signal that is driven LOW. If the external logic is no longer
driving GPIO1 low after the load has completed (~100 ms following a reset if no EEPROM is present),
the state of GPIO1 can be observed.
Then the system controller can access the TAS3204 through the I2C interface and read the status
register to determine the load status.
If the GPIO1 state is not observed, the only indication that the device has completed its initialization
procedure is the fact that the TAS3204 streams audio and the I2C slave interface has been enabled.
3.9.2 GPIO Pin Function After Device Is Programmed
Once the TAS3204 has been programmed, either through a successful boot load or via slave I2C
download, the operation of GPIO can be programmed to be an input and/or output.
3.10 Input and Output Serial Audio Ports
Serial data is input on SDIN1/SDIN2 on the TAS3204, allowing up to four channels of digital audio input.
The TAS3204 supports serial data in 16-, 20-, or 24-bit data in left, right, and I2S serial data formats. The
parameters for the clock and serial data interface input formats are I2C configurable.
Serial data is output on SDOUT1 and SDOUT2, allowing up to four channels of digital audio output.
SDOUT port supports the same formats as the SDIN port. Output data rate is the same data rate as the
input. The SDOUT output uses the SCLK_OUT and LRCLK_OUT signals to provide synchronization.
The TAS3204 supported data formats are listed in Table 3-1.
Table 3-1. Supported Data Formats
Input SAP (SDIN1, SDIN2)
2-channel I2S
Output SAP (SDOUT1, SDOUT2)
2-channel I2S
2-channel left-justified
2-channel right-justified
2-channel left-justified
2-channel right-justified
Table 3-2. Serial Data Input and Output Formats
Input
Control
IM[3:0]
Output
Control
OM[3:0]
Data
Rates
(kHz)
MAX
SCLK
(MHz)
Mode
Serial Format
Word Lengths
0000
0001
0010
0000
0001
0010
Left-justified
Right-justified
I2S
16, 20, 24
16, 20, 24
16, 20, 24
2-channel
32–48
3.072
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Input Port
Word Size
Output Port
Word Size
15
16
14 13
11 10
8
0x00
XX IW[2:0] OW[2:0] DWFMT (Data Word Format)
31
24
23
15
8
7
0
S
Slave Addr Ack
Subaddr
Ack
xxxxxxxx
Ack
xxxxxxxx
Ack
DWFMT
Ack
IOM
Ack
7
4
3
0
IM[3:0]
OM[3:0]
Input Port
Format
Output Port
Format
R0003-01
Figure 3-1. Serial Data Controls
Table 3-3. Serial Data Input and Output Data Word Sizes
IW1, OW1
IW0, OW0
FORMAT
0
0
1
1
0
1
0
1
Reserved
16-bit data
20-bit data
24-bit data
Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3204 should not be commanded to unmute until after the
SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a
volume or bass or treble update is taking place can cause the update not to be completed properly.
When the TAS3204 is transmitting serial data, it uses the negative edge of SCLK to output a new data bit.
The TAS3204 samples incoming serial data on the rising edge of SCLK.
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3.10.1 2-Channel I2S Timing
In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of the
data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data
on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3204 masks unused trailing data-bit positions.
2
2-Channel I S (Philips Format) Stereo Input/Output
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
1
0
23 22
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
0
19 18
16-Bit Mode
15 14
15 14
T0034-04
Figure 3-2. I2S 64fS Format
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3.10.2 2-Channel Left-Justified Timing
In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the
data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written
MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused trailing data-bit
positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
LRCLK
Right Channel
Left Channel
MSB
LSB MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
0
1
0
23 22
19 18
15 14
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
Figure 3-3. Left-Justified 64fS Format
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3.10.3 2-Channel Right-Justified Timing
In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW
when right-channel data is transmitted. SCLK is a bit clock running at 64 × fS which clocks in each bit of
the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK
toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The
data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused
leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
LRCLK
SCLK
Right Channel
Left Channel
MSB
LSB MSB
LSB
0
24-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
0
23 22
19 18
19 18
15 14
15 14
15 14
1
1
1
20-Bit Mode
16-Bit Mode
0
0
0
0
T0034-03
Figure 3-4. Right-Justified 64fS Format
3.10.4 SAP Input to SAP Output—Processing Flow
All SAP data format options other than I2S result in a two-sample delay from input to output. If I2S
formatting is used for both the input SAP and the output SAP, the polarity of LRCLK must be inverted.
However, if I2S format conversions are performed between input and output, the delay becomes either 1.5
samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core
relative to the sample rate of the incoming data.
The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use
the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core
operate on sample windows that are 180° out of phase with respect to the sample window used by the
output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the audio DSP core to process the data. If the processing cycle completes
all processing tasks before the midpoint of the processing sample period, the output SAP outputs this
processed data. However, if the processing time extends past the midpoint of the processing sample
period, the output SAP outputs the data processed during the previous processing sample period. In the
former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output
is 2.5 samples.
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The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions
are performed that involve the I2S format. However, which delay time is obtained for a particular
application is determinable and fixed for that application, providing care is taken in the selection of
MCLK_IN/XTAL_IN with respect to the incoming sample clock, LRCLK.
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4 Algorithm and Software Development Tools for TAS3204
The TAS3204 algorithm and software development tool set is a combination of classical development
tools and graphical development tools. The tool set is used to build, debug, and execute programs in both
the audio DSP and 8051 sections of the TAS3204.
Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level
debuggers. The 8051 can be programmed exclusively in ANSI C.
The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051
tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator.
The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete
environment with an IDE, context-sensitive editor, assembler, and simulator/debugger.
Graphical development tooling provides a means of programming the audio DSP core and 8051 through a
graphical drag-and-drop interface using modular audio software components from a component library.
The graphical tooling produces audio DSP assembly and 8051 ANSI C code as well as coefficients and
data. The classical tools can also be used to produce the executable code.
In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051
code on both simulators and EVM hardware.
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5 Clock Controls
Clock management for the TAS3204 consists of two control structures:
• Master clock management
–
Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and
the audio DSP core
–
–
The master clock (MCLK_IN or XTAL_IN) is the source for these clocks.
In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the
DPLL output drives the microprocessor and audio DSP clocks.
–
Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the
microprocessor and audio DSP clocks.
•
Serial audio port (SAP) clock management
–
–
Oversees SAP master/slave mode
Controls output of SCLKOUT, and LRCLK in the SAP master mode
Input pin MCLK_IN or XTAL_IN provides the master clock for the TAS3204. Within the TAS3204, these
two inputs are combined by an OR gate and, thus, only one of these two sources can be active at any one
time. The source that is not active must be logic 0.
The TAS3204 only supports dynamic sample-rate changes between any of the supported sample
frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the
TAS3204 remains in normal operation and the register contents are preserved. To avoid producing audio
artifacts during the sample-rate changes, a volume or mute control can be included in the application
firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be
provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL
source attached to MCLK_IN.
When the TAS3204 is used in a system in which the master clock frequency (fMCLK) can change, the
TAS3204 must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1
should be used.
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Enable Mute and
Wait for Completion
RESET Pin = Low
Change f
MCLK
Are
No
Clocks
Stable?
Yes
RESET Pin = High
After
TAS3204
Initializes,
Re-initialize
I2C Registers
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure
When the serial audio port (SAP) is in the master mode, the SAP uses the XTAL_IN master clock to drive
the serial port clocks SCLK_OUT and LRCLK. When the SAP is in the slave mode, MCLK_IN, SCLK_IN,
and LRCLK_IN are input clocks. SCLK_OUT and LRCLK_OUT are derived from SCLK_IN and
LRCLK_IN, respectively.
See Clock Register (0x00), Section 9.1, for information on programming the clock register.
Table 5-1. TAS3204 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz)
MCLK/
MCLK
Freq
(MHz)
SCLKIN
Rate
(× fS)
SCLK_IN
Freq
(MHz)
SCLK_OUT
Rate
FS Sample
Rate (kHz)
Ch Per
SDIN
LRCLK
Ratio
(× fS)
Ch Per
SDOUT
LRCLK
(FS)
PLL
Multiplier
FDSPCLK
(MHz)
fDSPCLK/fS
(× fS)
Slave Mode, 2 Channels In, 2 Channels Out
44.1
48
2
2
512
256
22.579
24.576
64
64
2.822
3.072
64
64
2
2
64
64
5.5
5.5
124.2
135.2
2816
2816
Master Mode, 2 Channels In, 2 Channels Out
256 24.576 N/A
48
2
N/A
64
2
64
5.5
135.2
2816
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6 Microprocessor Controller
The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus
controllers the required I2C read data, and participates in most processing tasks requiring multiframe
processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing
I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program
cannot be altered. The microprocessor controller has specialized hardware for master and slave interface
operation, volume updates, and a programmable interval timer interrupt. For more information see the
TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
The TAS3204 has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations
(maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and
to read device status.
The TAS3204 also has a master-only I2C interface that is compatible with the I2C bus protocol and
supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes).
The master I2C interface is used to load program and data from an external I2C EEPROM.
On power up of the TAS3204, the slave interface is disabled and the master interface is enabled.
Following a reset, the TAS3204 disables the slave interface and enables the master interface. Using the
master interface, the TAS3204 automatically tests to see if an I2C EEPROM is at address 1010x. The
value x can be chip select, other information, or don’t cares, depending on the EEPROM selected. If a
memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 loads the program, coefficient, and/or data memories from the
EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length
data segment. At this point, the TAS3204 disables the master I2C interface, enables the slave I2C
interface, and starts normal operation.
If no memory is present or if an error occurred during the EEPROM read, TAS3204 disables the master
I2C interface, enables the slave I2C interface, and loads the unprogrammed default configuration. In this
default configuration, the TAS3204 streams audio from input to output if the GPIO pin is LOW. The master
and slave interfaces do not operate simultaneously.
In the slave mode, the I2C bus is used to:
•
Load the program and coefficient data
–
–
–
–
–
Microprocessor program memory
Microprocessor extended memory
Audio DSP core program memory
Audio DSP core coefficient memory
Audio DSP core data memory
•
•
Update coefficient and other control values
Read status flags
Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3204 has
been reset.
The master and slave modes do not operate simultaneously.
When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLK_IN or
XTAL_IN = 24.576 MHz.
When acting as an I2C slave, the data transfer rate is determined by the master device on the bus.
The I2C communication protocol for the I2C slave mode is shown in Figure 6-1.
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Start
Read or Write
(By Master)
Stop
(By Master)
(By Master)
Slave Address
(By Master)
Data Byte
Data Byte
(By Transmitter)
(By Transmitter)
C
S
0
R
/
A
C
K
M
S
L
S
B
A
C
K
M
S
L
S
B
A
S
0
1
1
0
1
0
C
K
S
W
B
B
(1)
Acknowledge
(By TAS3204)
Acknowledge
(By Receiver)
Acknowledge
(By Receiver)
MSB MSB-1 MSB-2
LSB
SDA
SCL
Start Condition
SDA ↓While SCL = 1
Stop Condition
SDA ↑While SCL = 1
Figure 6-1. I2C Slave-Mode Communication Protocol
6.1 8051 Microprocessor Addressing Mode
The 256 bytes of internal data memory address space is accessible using indirect addressing instructions
(including stack operations). However, only the lower 128 bytes are accessible using direct addressing.
The upper 128 bytes of direct address Data Memory space are used to access Extended Special Function
Registers (ESFRs).
6.1.1 Register Banks
There are four directly addressable register banks, only one of which may be selected at one time. The
register banks occupy Internal Data Memory addresses from 00 hex to 1F hex.
6.1.2 Bit Addressing
The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit addressable.
SFRs that have addresses of the form 1XXXX000 binary are also bit addressable.
6.1.3 External Data Memory
External data memory occupies a 2K × 8 address space. This space contains the External Special
Function Data Registers (ESFRs). The ESFR permit access and control of the hardware features and
internal interfaces of the TAS3204.
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6.1.4 Extended Special Function Registers
ESFRs provide signals needed for the M8051 to control the different blocks in the device. ESFR is an
extension to the M8051. Figure 6-2 shows how these registers are arranged.
8051 MCU
Internal
Data
DESTIN_DO
DESTIN_A
SFRWE
Memory
Bus
Address
Decoder
D
Control Out
D
WE
WE
CCLK
CCLK
SFRWA
ESFRDI
Control In
CCLK
Figure 6-2. Extended Special Function Registers
6.1.5 Memory Mapped Registers for DAP Data Memory
The following memory mapped registers are used for communication with the digital audio processor.
Table 6-1. Memory Mapped Registers
Address
0x0300
0x0301
Register
Dither Seed
PC Start
Comment
Sets the dither seed value
Sets the starting address of the
DAP
0x0302
Reserved
Reserved
Note that TAS3204 has the same memory mapped registers distinction of upper and lower memory for
these registers.
6.2 General I2C Operations
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated
circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data are
transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the
clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start,
and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time
of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open
communication with another device and then waits for an acknowledge condition. The slave holds SDA
LOW during acknowledge clock period to indicate an acknowledgement. When this occurs, the master
transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus
R/W bit (one byte). All compatible devices share the same signals via a bidirectional bus using a
wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the
HIGH level for the bus.
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There is no limit on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. Figure 6-3 shows the
TAS3204 read and write operation sequences.
As shown in Figure 6-3, an I2C read transaction requires that the master device first issue a write
transaction to give the TAS3204 the subaddress to be used in the read transaction that follows. This
subaddress assignment write transaction is then followed by the read transaction. For write transactions,
the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be
written. For I2C write transactions, the subaddress must always be included in the data written. There
cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If
a subaddress-assignment-only write transaction is followed by a second write transaction supplying the
data, erroneous behavior results. The first byte in the second write transaction is interpreted by the
TAS3204 as another subaddress replacing the one previously written.
TAS3204
Subaddress
(By Master)
Data
(By TAS3204)
Data
(By TAS3204)
TAS3204
Address
TAS3204
Address
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
TAS3204
Subaddress
(By Master)
TAS3204
Address
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Acknowledge
(By TAS3204)
Figure 6-3. I2C Subaddress Access Protocol
6.3 I2C Slave Mode Operation
The I2C slave mode is the mode that is used to change configuration parameters during operation and to
perform program and coefficient downloads from a master device. The coefficient download operation in
slave mode can be used to replace the I2C master-mode EEPROM download. The TAS3204 supports
both random and sequential I2C transactions. The TAS3204 I2C slave address is 011010xy, where the first
six bits are the TAS3204 device address and bit x is CS0, which is set by the TAS3204 internal
microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00
address when no connection is made to the pin. Table 6-1 and Table 6-3 show all the legal addresses for
I2C slave and master modes.
The number of data bytes plus the two bytes checksum must be evenly divisible by the word size.
The size field is equal to (header + payload + end checksum).
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The checksum is contained in the last two data transfer bytes. These are bytes 7 and 8. On single word
transfers (DAP data, DAP instruction), the checksum is always contained in a 8 byte frame that follows the
last data word, last two bytes. For multiword data register transfers data (micro program, micro external
data, and coefficient RAM), the checksum is included in the same byte transfer as data. To meet the
requirement above, the number of words that are transferred contain modulo 8 + 6 in the case of micro
program and data memory, and modulo 2 + 1 in the case of coefficient memory. When the slave I2C
download is used to replace or update sections of micro program, micro data, or DAP coefficient memory,
it is necessary to take these transfer size restrictions into consideration when determining program, data,
and coefficient placements.
The multi word transfers always store first word on the bus at a lower RAM address and increment such
that the last word in the transfer is stored with the highest target RAM address. Consecutive I2C frame
transfers increment target address such that the data in the last transfer is last in target memory address
space.
When the first I2C slave download register is written by the system controlle, the TAS3204 updates the
status register by setting a error bit to indicate an error for the memory type that is being loaded. This
error bit is reset when the operation complete and a valid checksum has been received. For example
when the micro program memory is being loaded, the TAS3204 sets a micro program memory error
indication in the status register at the start of the sequence. When the last byte of the micro program
memory and checksum is received, the TAS3204 clears the micro program memory error indication. This
enables the TAS3204 to preserve any error status indications that occur as a result of incomplete
transfers of data/ checksum error during a series of data and program memory load operations.
The checksum is always contained in the last two bytes of the data block. The I2C slave download is
terminated when a termination header with a zero-length byte-count file is received.
The status register always reflects status of EEPROM boot attempts, unless the user writes to the slave
control register. A write to the slave boot control register causes the EEPROM status register to reflect
slave boot attempt status.
NOTE
Once the micro program memory has been loaded, further updates to this memory are
prohibited until the device is reset. The TAS3204 I2C block does respond to the broadcast
address (00h).
Table 6-2. Slave Addresses
Base Address
0110 10
CS0
R/W
Slave Address
0x68
0
0
1
1
0
1
0
1
0110 10
0x69
0110 10
0x6A
0110 10
0x6B
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Table 6-3. Master Addresses
Base Address
1010 00
CS0
R/W
Master Address
0xA0
0
0
1
1
0
1
0
1
1010 00
0xA1
1010 00
0xA2
1010 00
0xA3
The following is an example use of the I2C master address to access an external EEPROM. The TAS3204
can address up to two EEPROMs depending on the state of CS0. Initially, the TAS3204 comes up in I2C
master mode. If it finds a memory such as the 24C512 EEPROM, it reads the headers and data as
previously described. In this I2C master mode, the TAS3204 addresses the EEPROMs as shown in
Table 6-4 and Table 6-5.
Table 6-4. EEPROM Address I2C TAS3204 Master Mode = 0xA1/A0
A0
(EEPROM)
MSB
CS0
R/W
1
0
1
0
0
0
0
1/0
Table 6-5. EEPROM Address I2C TAS3204 Master Mode = 0xA3/A2
A0
CS0
MSB
R/W
(EEPROM)
1
0
1
0
0
0
1
1/0
Random I2C Transactions
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For
random I2C read commands, the TAS3204 responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a given subaddress
does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in
accordance with the data assignment for that address space. If a write command is received for a mixer
subaddress, for example, the TAS3204 expects to see five 32-bit words. If fewer than five data words
have been received when a stop command (or another start command) is received, the data received is
discarded.
Sequential I2C Transactions
The TAS3204 also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS3204. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written to. As was true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data
is discarded.
Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.
If the master does not issue enough data-received acknowledges to receive all the data for a given
subaddress, the master device simply does not receive all the data.
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If the master device issues more data-received acknowledges than required to receive the data for a given
subaddress, the master device simply receives complete or partial sets of data, depending on how many
data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both
sequential and random, can impose wait states.
6.3.1 Multiple-Byte Write
Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-4. After receiving
each data byte, the TAS3204 responds with an acknowledge bit.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
Figure 6-4. Multiple-Byte Write Transfer
6.3.2 Multiple-Byte Read
Multiple data bytes are transmitted by the TAS3204 to the master device as shown in Figure 6-5. Except
for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Not
Acknowledge
D0 ACK
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A6
A0 R/W ACK D7
D0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 6-5. Multiple-Byte Read Transfer
6.4 I2C Master-Mode Device Initialization
I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions
do not start until the I2C bus is idle.
The TAS3204 uses the master mode to download from EEPROM the memory contents for the
microprocessor program memory, microprocessor extended memory, audio DSP core program memory,
audio DSP core coefficient memory, and audio DSP core data memory.
The TAS3204, when operating as an I2C master, can execute a complete download of any internal
memory or any section of any internal memory without requiring any wait states.
When the TAS3204 operates as an I2C master, the TAS3204 generates a repeated start without an
intervening stop command while downloading program and memory data from EEPROM. When a
repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to
transfer large blocks of data quickly.
The TAS3204 queries the bus for an I2C EEPROM at address 1010xxx. The value xxx can be chip select,
other information, or don’t cares, depending on the EEPROM selected.
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The first action of the TAS3204 as master is to transmit a start condition along with the device address of
the I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the
address byte, and the TAS3204 sends a subaddress byte, which the EEPROM acknowledges. Most
EEPROMs have at least 2-byte addresses and acknowledge as many as are appropriate. At this point, the
EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3204 acknowledges each
byte repeatedly to continue reading each data byte that is stored in memory.
The memory load information starts with reading the header and data information that starts at
subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with
no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header
locations.
The TAS3204 memory data can be stored and loaded in (almost) any order. Additionally, this addressing
scheme permits portions of the TAS3204 internal memories to be loaded.
2
I C EEPROM Memory Map
Block Header 1
Data Block 1
Block Header 2
Data Block 2
w
w
w
Block Header N
Data Block N
M0040−01
Figure 6-6. EEPROM Address Map
The TAS3204 sequentially reads EEPROM memory and loads its internal memory unless it does not find
a valid memory header block, is not able to read the next memory location because the end of memory
was reached, detects a checksum error, or reads an end-of-program header block. When it encounters an
invalid header or read error, the TAS3204 attempts to read the header or memory location three times
before it determines that it has an error. If the TAS3204 encounters a checksum error it attempts to reread
the entire block of memory two more times before it determines that it has an error.
Once the microprocessor program memory has been loaded, it cannot be reloaded until the TAS3204 has
been reset.
If an error is encountered, TAS3204 terminates its memory-load operation, loads the default configuration,
and disables further master I2C bus operations.
If an end-of-program data block is read, the TAS3204 has completed the initial program load.
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The I2C master mode uses the starting and ending I2C checksums to verify a proper EEPROM download.
The first 16-bit data word received from the EEPROM, the I2C checksum at subaddress 0x00, is stored
and compared against the 16-bit data word received for the last subaddress, the ending I2C checksum,
and the checksum that is computed during the download. These three values must be equal. If the read
and computed values do not match, the TAS3204 sets the memory read error bits in the status register
and repeats the download from the EEPROM two more times. If the comparison check fails the third time,
the TAS3204 sets the microprocessor program to the default value.
Table 6-6 shows the format of the EEPROM or other external memory load file. Each line of the file is a
byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending
checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four
bytes of the checksum.
Example:
Given the following example 8051 data or program block (must be a multiple of 4 bytes for these blocks):
10h
20h
30h
40h
50h
60h
70h
80h
The checksum = 10h + 20h + 30h + 30h + 40h + 50h + 60h + 70h + 80h = 240h, so
the values put in the checksum fields are MS byte = 02h and LS byte = 40h.
If the checksum is >FFFFh, then the 2-byte checksum field is the least-significant 2 bytes.
For example, if the checksum is 1D 45B6h, the checksum field is MS byte = 45h and LS byte = B6h.
Table 6-6. TAS3204 Memory Block Structures
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
12-Byte Header Block
Checksum code MS byte
Checksum code LS byte
Header ID byte 1 = 0x00
Checksum of bytes 2 through N + 12.
If this is a termination header, this value is 00 00
0
2 bytes
2 bytes
Must be 0x001F for the TAS3204 to load as part of
initialization. Any other value terminates the initialization
memory load sequence.
2
Header ID byte 2 = 0x1F
0x00 – Microprocessor program memory or termination
header
0x01 – Microprocessor external data memory
0x02 – Audio DSP core program memory
0x03 – Audio DSP core coefficient memory
0x04 – Audio DSP core data memory
0x05–06 – Audio DSP upper program memory
0x07 – Audio DSP Upper Coefficient Memory
0x08–FF – Reserved for future expansion
4
5
Memory to be loaded
1 byte
0x00
1 byte
Unused
Start TAS3204 memory address MS byte
Start TAS3204 memory address LS byte
6
2 bytes
If this is a termination header, this value is 0000.
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Total number of bytes transferred MS byte
12 + data bytes + last checksum bytes. If this is a
termination header, this value is 0000.
8
2 bytes
Total number of bytes transferred LS byte
10
11
0x00
0x00
1 bytes
1 bytes
Unused
Unused
Data Block for Microprocessor Program or Data Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data byte 2
12
16
4 bytes
4 bytes
1–4 microprocessor bytes
5–8 microprocessor bytes
Data byte 3
Data byte 4 (MS byte)
Data byte 5
Data byte 6
Data byte 7
Data byte 8
•
•
•
Data byte 4×(Z – 1) + 1
Data byte 4×(Z – 1) + 2
Data byte 4×(Z – 1) + 3
Data byte 4×(Z – 1) + 4 = N
0x00
N + 8
4 bytes
4 bytes
0x00
N + 12
Repeated checksum bytes 2 through N + 11
Checksum code MS byte
Checksum code LS byte
Data Block for Audio DSP Core Coefficient Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data byte 2
Coefficient word 1 (valid data in D27–D0) D7–D0
D15–D8
12
16
4 bytes
4 bytes
Data byte 3
D23–D16
D31–D24
Data byte 4 (MS byte)
Data byte 5
Data byte 6
Coefficient word 2
Data byte 7
Data byte 8
•
•
•
Data byte 4×(Z – 1) + 1
Data byte 4×(Z – 1) + 2
Data byte 4×(Z – 1) + 3
Data byte 4×(Z – 1) + 4 = N
0x00
N + 8
4 bytes
4 bytes
Coefficient word Z
0x00
N + 12
Repeated checksum bytes 2 through N + 11
Checksum code MS byte
Checksum code LS byte
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Data Block for Audio DSP Core Data Memory (Following 12-Byte Header)
Data byte 1 (LS byte)
Data byte 2
Data word 1 D7–D0
D15–D8
Data byte 3
D23–D16
12
18
6 bytes
Data byte 4
Data byte 5
D31–D24
D39–D32
Data byte 6 (MS byte)
Data byte 7
D47–D40
Data byte 8
Data byte 9
6 bytes
Data 2
Data byte 10
Data byte 11
Data byte 12
•
•
•
Data byte 6×(Z – 1) + 1
Data byte 6×(Z – 1) + 2
Data byte 6×(Z – 1) + 3
Data byte 6×(Z – 1) + 4
Data byte 6×(Z – 1) + 5
Data byte 6×(Z – 1) + 6 = N
0x00
N + 6
6 bytes
Data Z
0x00
0x00
N + 12
6 bytes
Repeated checksum bytes 2 through N + 11
0x00
Checksum code MS byte
Checksum code LS byte
Data Block for Audio DSP Core Program Memory (Following 12-Byte Header)
Program word 1 (valid data in D53–D0) D7–D0
Program byte 1 (LS byte)
Program byte 2
Program byte 3
Program byte 4
Program byte 5
Program byte 6
Program byte 7 (MS byte)
Program byte 8
Program byte 9
Program byte 10
Program byte 11
Program byte 12
Program byte 14
Program byte 15
•
D15–D8
D23–D16
D31–D24
D39–D32
D47–D40
D55–D48
12
7 bytes
19
7 bytes
Program word 2
•
•
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Program byte 7×(Z – 1) + 1
Program byte 7×(Z – 1) + 2
Program byte 7×(Z – 1) + 3
Program byte 7×(Z – 1) + 4
Program byte 7×(Z – 1) + 5
Program byte 7×(Z – 1) + 6
Program byte 7×(Z – 1) + 7 = N
0x00
N + 5
7 bytes
Program word Z
0x00
0x00
N + 12
0x00
7 bytes
Repeated checksum bytes 2 through N + 11
0x00
Checksum code MS byte
Checksum code LS byte
20-Byte Termination Block (Last Block of Entire Load Block)
0x00
BLAST – 19
2 bytes
2 bytes
First 2 bytes of termination block are always 0x0000.
Second 2 bytes are always 0x001F.
0x00
0x00
BLAST – 17
0x1F
BLAST – 15
BLAST – 14
0x00
1 byte
1 byte
0x00
•
Last 16 bytes must each be 0x00.
•
•
BLAST
0x00
1 byte
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7 Digital Audio Processor (DAP) Arithmetic Unit
The DAP arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and
coefficient memory blocks. The primary features of the DAP are:
•
Two pipe parallel processing architecture
–
–
–
–
–
–
–
48-bit data path with 76-bit accumulator
Hardware single cycle multiplier (28×48)
Three 48-bit general-purpose data registers and one 28-bit coefficient register
Four simultaneous operations per machine cycle
Shift right, shift left and bi-modal clip
Log2/Alog2
Magnitude Truncation
•
Hardware acceleration units
–
–
–
–
Soft volume controller
Delay memory
Dither generator
log2/2× estimator
•
•
•
•
•
1024 + 768 dual port ports words of data (24 and 48 bits, respectively)
1228 words of coefficient memory (28 bits)
3K word of program RAM (55 bits)
5.88K words of 24-bits delay memory (1.22 ms)
Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into
the same memory space for convenient addressing by the microcontroller.
•
Memory interface block contains four pointers, two for data memory and two for coefficient memory.
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28
28
28
Micro
Mem
IF
48
28
DATA RAM
1022 × 48
COEF RAM
1022 × 28
28
48
48
48
28
VOL (5 lsbs)
(EREG4)
DI (3 lsbs)
(EREG3)
48
48
28 48
48
48
28 48
28
LFS
(LFSR)
48
2
48
48
48
48
28
B
(BREG)
L
(CREG)
MD
(AREG)
MC
(RREG)
48
48
48
28
Barrel Shift,
NEG, ABS,
or THRU
LOG, ALOG,
NEG, ABS,
or THRU
DLYO
(EREG1)
Multiply
48
76
ACC
76
MR
48
BR
(PREG1)
LR
(PREG2) (PREG3)
“ZERO”
76
Legend
76
48
76
48
Register
Operand A
Operand B
28
32
48
ADD
28-bit data
32-bit data
48-bit data
76-bit data
76
CLIP
76
48
DLYI
(DREG9)
Delay RAM
5.8K × 24
Output Register File (DO1 – DO8)
(DREG1 – DREG8)
32
To Output SAP
Figure 7-1. DSP Core Block Diagram
7.1 DAP Instructions Set
Please see this information in the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
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7.2 DAP Data Word Structure
Figure 7-2 shows the data word structure of the DAP arithmetic unit. Eight bits of overhead or guard bits
are provided at the upper end of the 48-bit DAP word, and 16 bits of computational precision or noise bits
are provided at the lower end of the 48-bit word. The incoming digital audio words are all positioned with
the most significant bit abutting the 8-bit overhead/guard boundary. The sign bit in bit 39 indicates that all
incoming audio samples are treated as signed data samples The arithmetic engine is a 48-bit (25.23
format) processor consisting of a general-purpose 76-bit arithmetic logic unit and function-specific
arithmetic blocks. Multiply operations (excluding the function-specific arithmetic blocks) always involve
48-bit DAP words and 28-bit coefficients (usually I2C programmable coefficients). If a group of products is
to be added together, the 76-bit product of each multiplication is applied to a 76-bit adder, where a
DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations use the MAC
operation to maintain precision in the intermediate computational stages.
47
40 39
32 31
24 23 22 21 20 19 16 15
8
7
0
16-Bit Audio
18-Bit Audio
20-Bit Audio
Overhead/
Guard Bits
Precision/Noise Bits
24-Bit Audio
Figure 7-2. Arithmetic Unit Data Word Structure
To maximize the linear range of the 76-bit ALU, saturation logic is not used. In MAC computations,
intermediate overflows are permitted, and it is assumed that subsequent terms in the computation flow
correct the overflow condition (see Figure 7-3). The DAP memory banks include a dual port data RAM for
storing intermediate results, a coefficient RAM, and a fixed program ROM. Only the coefficient RAM,
assessable via the I2C bus, is available to the user.
(-73)
1
0
1
0
0
0
1
0
0
1
0
1
1
0
0
1
1
1
0
1
-73
-51
+
+
(-51)
(-124)
(-45)
+
1
1
1
1
0
1
1
0
0
1
1
0
-124
-45
+
(57)
(59)
Rollover
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
57
59
+
+
(-110)
-110
Figure 7-3. DSP ALU Operation With Intermediate Overflow
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D23 D22 - - - - - D1 D0
Input 24-Bit Data
0 . . . 0
47–40
D23 D22 - - - - - D1 D0
39 - - - - - - 16
0 . . . 0
15–0
8-Bit Headroom
and 16-Bit Noise
27–23
22 - - - - - - - - - - - - - - - 0
Coefficient
Representation
Head-
room
Scaling
Data (24 bits)
Fractional Noise
Multiplier
Output
75–71 70–63
62
–
39
12
38–31
30
–
0
12
8
31
5
8
48-Bit Clipping
POS48
NEG48
–
–
0x7F_F FFF_FFFF _FF
0x80_0 000_0000 _00
32-Bit Clipping
POS40
NEG40
–
–
0xXX_ 7FFF_FFFF _XX
0xXX_ 8000_0000 _XX
28-Bit Clipping
POS20
NEG20
–
–
0xXXXXX_ 7FFF_FFFF
0xXXXXX_ 8000_0000
Figure 7-4. DAP Data-Path Data Representation
36
Digital Audio Processor (DAP) Arithmetic Unit
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8 Electrical Specifications
8.1 Absolute Maximum Ratings(1)
over operating temperature range (unless otherwise noted)
DVDD
Digital supply voltage range
–0.5 V to 3.8 V
–0.5 V to 3.8 V
–0.5 V to DVDD + 0.5 V
–0.5 V to 2.3 V
–0.5 V to DVDD + 0.5 V
–0.5 V to 2.3 V(2)
±20 µA
AVDD
Analog supply voltage range
3.3-V TTL
VI
Input voltage range
Output voltage range
1.8 V LVCMOS (XTLI)
3.3 V TTL
VO
1.8 V LVCMOS (XTLO)
IIK
Input clamp current (VI < 0 or VI > DVDD)
Output clamp current (VO < 0 or VO > DVDD)
Operating free-air temperature range
Storage temperature range
IOK
TA
±20 µA
0°C to 70°C
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pin XTAL_OUT is the only TAS3204 output that is derived from the internal 1.8-V logic supply. The absolute maximum rating listed is for
reference; only a crystal should be connected to XTAL_OUT.
Note:
•
•
•
VR_ANA is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
VR_DIG is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
VR_PLL is derived from TAS3204 internal 1.8-V voltage regulator. This terminal must not be used to power external devices.
8.2 Package Dissipation Ratings
Package Description
T
A ≤ 25°C
Derating Factor
Above TA = 25°C
(mW/°C)
TA = 70°C
Power Rating
(mW)
Power Rating
(mW)
Package
Designator
Package Type
Pin Count
TQFP
64
PAG
1869
23.36
818
8.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
DVDD Digital supply voltage
AVDD Analog supply voltage
3
3
3.3
3.3
3.6
3.6
V
V
3.3 V TTL
2
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
1.8 V LVCMOS (XTL_IN)
3.3 V TTL
1.2
0.8
0.5
70
1.8 V LVCMOS (XTL_IN)
TA
TJ
Operating ambient air temperature
Operating junction temperature
Analog differential input
0
0
25
°C
°C
105
2
10
VRMS
kΩ
Resistance
Analog output load
Capacitance
100
pF
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8.4 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA
MIN
TYP
MAX UNIT
3.3-V TTL
2.4
VOH
High-level output voltage
V
1.8-V LVCMOS
(XTL_OUT)
IOH = –0.55 mA
IOL = 4 mA
1.44
3.3-V TTL
0.5
VOL
IOZ
IIL
Low-level output voltage
High-impedance output current
Low-level input current
V
1.8-V LVCMOS
(XTL_OUT)
IOL = 0.75 mA
0.4
3.3-V TTL
3.3-V TTL
VI = VIL
VI = VIL
VI = VIL
±20
±20
±20
µA
µA
1.8-V LVCMOS
(XTL_IN)
3.3-V TTL
VI = VIH
VI = VIH
±20
±20
IIH
High-level input current
µA
1.8-V LVCMOS
(XTL_IN)
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
IDVDD
IAVDD
Digital supply current
Analog supply current
Normal operation
Normal operation
Normal operation
130
60
mA
mA
mW
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
MCLK_IN = 24.576 MHz,
LRCLK = 48 kHz
627
Power
With voltage regulators on
With voltage regulators off
23
825
20
mW
µW
mW
V
Dissipation Digital and analog supply current
(Total)
Standby mode
Reset mode
VR_ANA
VR_PLL
VR_DIG
Internal voltage regulator – analog
Internal voltage regulator – PLL
Internal voltage regulator – digital
1.6
1.6
1.6
1.8
1.8
1.8
1.98
1.98
1.98
V
V
8.5 Audio Specifications
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Evaluation module. A-weighted,
–60 dB with respect to full scale
Dynamic range
100
dB
Overall performance:
input ADC – DAP –
DAC – line out
Evaluation module. –3 dB with
respect to full scale
THD+N
101
dB
A-weighted, –60 dB with respect to
full scale.
Dynamic range
THD+N
102
93
dB
dB
dB
–4 dB with respect to full scale.
One channel = –3 dB;
Other channel = 0 V
Crosstalk
84
ADC section
Power supply rejection ratio
Input resistance
1 kHz, 100 mVpp on AVDD
57
20
dB
kΩ
pF
Input capacitance
Pass band edge
10
0.45Fs
±0.01
0.55Fs
100
Hz
dB
Hz
dB
Sec
Pass band ripple
Stop band edge
ADC decimation filter
Stop band attenuation
Group delay
37÷Fs
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Audio Specifications (continued)
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, Fs = 48 kHz, 1-kHz sine wave full scale, over operating free-air temperature range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential full scale output
voltage
2
VRMS
A-weighted, –60 dB with respect to
full scale
Dynamic range
THD+N
105
95
dB
dB
dB
0-dBFS input, 0-dB gain
One channel –3 dBFS;
Other channel 0 V
DAC to ADC
84
DAC section
One channel –3 dB;
Other channel 0 V
Crosstalk
ADC to DAC
DAC to DAC
84
dB
dB
One channel –3 dBFS;
Other channel 0 V
84
56
Power supply rejection ratio
DC offset
1 kHz, 100 mVpp on AVDD
With respect to VREF
dB
mV
Hz
dB
Pass band edge
Pass band ripple
0.45Fs
±0.06
1.45 Fs to
0.55Fs
Transition band
Hz
DAC interpolation filter
Stop band edge
7.4Fs
-65
Hz
dB
Stop band attenuation
Filter group delay
21÷Fs
Sec
Figure 8-1. Frequency Response (ADC-DAC)
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Figure 8-2. THD+N (ADC-DAC)
40
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8.6 Timing Characteristics
The following sections describe the timing characteristics of the TAS3204.
8.6.1 Master Clock
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
(1)
f(XTAL_IN)
tc(1)
Frequency, XTAL_IN (1/ tc(1)
)
See
512Fs
1÷512Fs
512Fs
Hz
Sec
Hz
Cycle time, XTAL_IN
f(MCLK_IN)
Frequency, MCLK_IN (1/ tc(2))
(2)
tw(MCLK_IN) Pulse duration, MCLK_IN high
Crystal frequency deviation
See
0.4 tc(2)
0.5 tc(2)
0.6 tc(2)
ns
ppm
Hz
ns
50
f(MCLKO)
tr(MCLKO)
tf(MCLKO)
Frequency, MCLKO (1/ tc(3)
)
256Fs
Rise time, MCLKO
CL = 30 pF
CL = 30 pF
15
15
Fall time, MCLKO
ns
(3)
tw(MCLK_IN) Pulse duration, MCLKO high
See
HMCLKO
80
ns
XTAL_IN master clock
source
ps
ps
MCLKO jitter
MCLK_IN master clock
source
(4)
See
(5)
MCLKO = MCLK_IN
MCLKO < MCLK_IN
See
20
20
ns
ns
Delay time, MCLK_IN rising
td(MI-MO)
(5)(6)
edge to MCLKO rising edge
See
(1) Duty cycle is 50/50.
(2) Period of MCLK_IN = TMCLK_IN = 1/fMCLK_IN
(3) HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLK_IN when MCLKO = MCLK_IN. When MCLKO = 0.5 MCLK_IN or
0.25 MCLK_IN, the duty cycle of MCLKO is typically 50%.
(4) When MCLKO is derived from MCLK_IN, MCLKO jitter = MCLK_IN jitter
(5) Only applies when MCLK_IN is selected as master source clock
(6) Also applies to MCLKO falling edge when MCLKO = MCLK_IN/2 or MCLK_IN/4
XTALI
t
c(1)
t
w(MCLKI)
MCLKI
t
c(2)
t
d(MI-MO)
t
w(MCLKO)
t
t
r(MCLKO)
f(MCLKO)
MCLKO
t
c(3)
T0088-01
Figure 8-3. Master Clock Signal Timing Waveforms
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8.6.2 Serial Audio Port, Slave Mode
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
fLRCLK
Frequency, LRCLK (fS)
Pulse duration, SCLKIN high
Frequency, SCLKIN
48
0.4 tc(SCLKIN) 0.5 tc(SCLKIN) 0.6 tc(SCLKIN)
64 FS
kHz
ns
(1)
tw(SCLKIN)
fSCLKIN
See
(2)
See
MHz
Propagation delay, SCLKIN falling edge to
SDOUT
tpd1
16
ns
tsu1
th1
tsu2
th2
Setup time, LRCLK to SCLKIN rising edge
Hold time, LRCLK from SCLKIN rising edge
Setup time, SDIN to SCLKIN rising edge
Hold time, SDIN from SCLKIN rising edge
10
5
ns
ns
ns
ns
10
5
Propagation delay, SCLKIN falling edge to
SCLKOUT2 falling edge
tpd2
15
ns
(1) Period of SCLKIN = TSCLKIN = 1/fSCLKIN
(2) Duty cycle is 50/50.
t
t
c(SCLKIN)
w(SCLKIN)
SCLKIN
t
h1
t
su1
LRCLK
(Input)
t
pd1
SDOUT1
SDOUT2
SDOUT3
SDOUT4
t
h2
t
su2
SDIN1
SDIN2
SDIN3
SDIN4
t
pd2
SCLKOUT2
T0090-01
Figure 8-4. Serial Audio Port Slave Mode Timing Waveforms
42
Electrical Specifications
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8.6.3 Serial Audio Port Master Mode Signals (TAS3204)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f(LRCLK)
Frequency LRCLK
Rise time, LRCLK
CL = 30 pF
48
kHz
(1)
(1)
tr(LRCLK)
CL = 30 pF
12
12
ns
ns
tf(LRCLK)
Fall time, LRCLK
Duty cycle is 50/50
CL = 30 pF
f(SCLKOUT)
tr(SCLKOUT)
tf(SCLKOUT)
Frequency, SCLKOUT
Rise time, SCLKOUT
Fall time, SCLKOUT
64FS
MHz
ns
CL = 30 pF
12
12
5
CL = 30 pF
ns
tpd1(SCLKOUT) Propagation delay, SCLKOUT falling edge to LRCLK edge
ns
tpd2
tsu
th
Propagation delay, SCLKOUT falling edge to SDOUT1-2
Setup time, SDIN to SCLKOUT rising edge
5
ns
25
30
ns
Hold time, SDIN from SCLKOUT rising edge
ns
(1) Rise time and fall time measured from 20% to 80% of maximum height of waveform.
t
t
f(SCLKOUT)
r(SCLKOUT)
SCLKOUT2
SCLKOUT1
t
r(SCLKOUT)
t
f(SCLKOUT)
t
sk
t
t
pd1(SCLKOUT2)
pd1(SCLKOUT1)
LRCLK
(Output)
t
, t
f(LRCLK) r(LRCLK)
t
pd2
SDOUT1
SDOUT2
SDOUT3
SDOUT4
t
h
t
su
SDIN1
SDIN2
SDIN3
SDIN4
T0091-01
Figure 8-5. Serial Audio Port Master Mode Timing Waveforms
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8.6.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices
STANDARD MODE
FAST MODE
PARAMETER
TEST CONDITIONS
UNIT
MIN
–0.5
2
MAX
MIN
–0.5
MAX
VIL
LOW-level input voltage
HIGH-level input voltage
Hysteresis of inputs
0.8
0.8
V
V
V
VIH
Vhys
2
N/A
N/A
0.05 VDD
LOW-level output voltage (open drain or
open collector)
VOL1
3-mA sink current
0
0.4
V
Bus capacitance from 10 pF
to 400 pF
(1)
tof
Output fall time from VIHmin to VILmax
Input current, each I/O pin
250 7 + 0.1 Cb
250
ns
µA
ns
II
–10
N/A
10
–10(2)
10(2)
SCL pulse duration of spikes that must
be suppressed by the input filter
tSP(SCL)
N/A
14(3)
22(3)
SDA pulse duration of spikes that must
be suppressed by the input filter
tSP(SDA)
CI
N/A
N/A
10
ns
Capacitance, each I/O pin
10
pF
(1) Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I2C specification.
(2) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.
(3) These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles.
all values are referred to VIHmin and VILmax (see Section 8.6.4)
STANDARD MODE
PARAMETER
FAST MODE
UNIT
MIN
MAX
100
MIN
MAX
fSCL
SCL clock frequency
0
4
0
400(1)
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHD-STA
0.6
µs
tLOW
tHIGH
tSU-STA
tSU-DAT
tHD-DAT
tr
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for repeated START
Data setup time
4.7
4
1.3
0.6
0.6
100
µs
µs
µs
µs
µs
ns
ns
µs
µs
pF
4.7
250
0
(2)(3)
Data hold time
3.45
0
0.9
300
300
(4)
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL
1000 20 + 0.1 Cb
300 20 + 0.1 Cb
(4)
tf
tSU-STO
tBUF
Setup time for STOP condition
4
0.6
1.3
Bus free time between a STOP and START condition
Capacitive load for each bus line
4.7
Cb
400
400
Noise margin at the LOW level for each connected device
(including hysteresis)
VnL
VnH
0.1VDVDD
0.2VDVDD
0.1VDVDD
0.2VDVDD
V
V
Noise margin at the HIGH level for each connected device
(including hysteresis)
(1) In master mode, the maximum speed is 375 kHz.
(2) Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges
of SCL. TI recommends that a 2-kΩ pullup resistor be used to avoid potential timing issues.
(3) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT ≥ 250 ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
(4) Cb = total capacitance of one bus line in pF
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NOTE
SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be
valid by the rising and falling edges of SCL.
SDA
t
f
t
t
t
r
SU-DAT
HD-STA
t
t
SP
t
BUF
LOW
t
r
t
f
SCL
t
t
t
SU-STO
HD-DAT
SU-STA
t
t
HIGH
HD-STA
S
Sr
P
S
T0114-01
Figure 8-6. Start and Stop Conditions Timing Waveforms
8.6.5.1 Recommended I2C Pullup Resistors
It is recommended that the I2C pullup resistors RP be 4.7 kΩ (see Figure 8-7). If a series resistor is in the
circuit (see Figure 8-8), then the series resistor RS should be less than or equal to 300 Ω.
DVDD
TAS3204
External
Microcontroller
IP
IP
RP
RP
VI(SDA)
VI(SCL)
SDA
SCL
Figure 8-7. I2C Pullup Circuit (With No Series Resistor)
DVDD
TAS3204
External
Microcontroller
IP
RP
(2)
(2)
RS
RS
SDA
or
SCL
VI
(1)
VS
(1) VS = DVDD × RS/(RS – RP). When driven low, VS << VIL requirements.
(2) S ≤ 300 Ω
R
Figure 8-8. I2C Pullup Circuit (With Series Resistor)
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8.6.6 Reset Timing
control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(RESET)
tr(DMSTATE)
tr(run)
Pulse duration, RESET active
Time to outputs inactive
Time to enable I2C
200
ns
µs
100
50
ms
RESET
tw(RESET)
Initialization Complete
Internal Reset
tr(run)
Time to enable I2C
tr(DMSTATE)
Figure 8-9. Reset Timing
46
Electrical Specifications
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9 I2C Register Map
I2C registers are also mapped to some of the Extended Special Function Registers (ESFR). They are
defined in the following sections.
Table 9-1. I2C Register Map
NO. OF
BYTES
INITIALIZATION
VALUE
SUBADDRESS
REGISTER NAME
CONTENTS
0x00
0x01
0x02
0x03
Clock and SAP Control Register
Reserved
4
4
4
Description shown in Section 9.1
Reserved
0x00, 0x40, 0x1B, 0x22
0x00, 0x00, 0x00, 0x40
0x00, 0x00, 0x03, 0xFF
0x00, 0x00, 0x00, 0x00
Status Register
Unused
Description shown in Section 9.3
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x04
0x05
0x06
I2C Memory Load Control
I2C Memory Load Data
8
8
4
Description shown in Section 9.4
Description shown in Section 9.4
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
u(31:24)(1), MemSelect(23:16),
Addr(15:8), Addr(7:0)
Memory Select and Address
0x00, 0x00, 0x00, 0x00
D(63:56), D(55:48), D(47:40),
D(39:32), D(31:24), D(23:16),
D(15:8), D(7:0)
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x07
Data Register
16
0x08
0x09
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x30–0x3F
Device Version
Unused
4
TAS3204 version
Unused
0x00, 0x00, 0x00, 0x01
Unused
Unused
Analog Power Down Control 1
Analog Power Down Control 2
Analog Input Control
ADC Dynamic Element Matching
ADC2 Current Control 1
ADC2 Current Control 2
Unused
4
4
4
4
4
4
Analog Power Down Control 1
Analog Power Down Control 2
Analog Input Control
ADC Dynamic Element Matching
ADC1 Current Control 1
ADC1 Current Control 2
Unused
0x00, 0x00, 0x00, 0x1F
0x00, 0x00, 0x00, 0xFF
0x00, 0x00, 0x00, 0x01
0x00, 0x00, 0x00, 0x08
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
ADC1 Current Control 1
ADC1 Current Control 2
Unused
4
4
4
4
4
4
4
4
ADC2 Current Control 1
ADC2 Current Control 2
Unused
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
DAC Control 1
DAC Control 1
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x05
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00
See Section 9.15
DAC Control 2
DAC Control 2
Analog Test Modes
DAC Modulator Dither
ADC/DAC Digital Reset
Analog Input Gain Select
Clock Delay Setting ADC
MCLK_OUT2 Divider
MCLK_OUT3 Divider
Bypass Time
Analog Test Modes
DAC Modulator Dither
ADC/DAC Digital Reset
Analog Input Gain Select
Clock Delay Setting ADC
MCLK_OUT2 Divider
MCLK_OUT3 Divider
Bypass Time
4
4
4
4
Clock Delay Setting DAC
Digital Cross Bar
4
Clock Delay Setting DAC
Digital Cross Bar
32
(1) u indicates unused bits.
In the following sections, BOLD indicates the default state of the bit fields.
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9.1 Clock Control Register (0x00)
Register 0x00 provides the user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word
size, and serial audio port modes. Register 0x00 default = 0x00 00 1B 22.
Table 9-2. Clock Control Register (0x00)
D31
D30
D29
D28
D27
D26
D25
D24
DESCRIPTION
DESCRIPTION
–
–
–
–
–
–
–
–
Firmware definable
D23
–
D22
1
D21
–
D20
–
D19
–
D18
–
D17
–
D16
–
Master Mode (XTAL)
–
0
–
–
–
–
–
–
Slave mode (MCLK_IN)
D15
–
D14
–
D13
–
D12
–
D11
–
D10
–
D9
0
D8
0
DESCRIPTION
Output SAP 32 bit word
Output SAP 16 bit word
Output SAP 20 bit word
Output SAP 24 bit word
Input SAP 32 bit word
Input SAP 16 bit word
Input SAP 20 bit word
Input SAP 24 bit word
–
–
–
–
–
–
0
1
–
–
–
–
–
–
1
0
–
–
–
–
–
–
1
1
–
–
–
0
0
–
–
–
–
–
–
0
1
–
–
–
–
–
–
1
0
–
–
–
–
–
–
1
1
–
–
–
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
IM3
IM2
IM1
IM0
Input data format
OM3
OM2
OM1
OM0 Output data format
9.2 Microcontroller Clock Control Register
This register is reserved.
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9.3 Status Register (0x02)
During I2C download, the write operation to indicate that a particular memory is to be written causes the
TAS3204 to set an error bit to indicate a load for that memory type. This error bit is cleared when the
operation completes successfully.
Table 9-3. Status Register (0x02)
D31
D30
D29
D28
D27
D26
D25
D24
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
–
–
–
–
–
–
–
–
Firmware definable
Firmware definable
Firmware definable
D23
D22
D21
D20
D19
D18
D17
D16
–
–
–
–
–
–
–
–
D15
D14
D13
D12
D11
D10
D9
D8
–
–
–
–
–
–
–
–
D7
0
D6
0
D5
–
D4
–
D3
–
D2
–
D1
–
D0
1
Microprocessor program memory load error
Microprocessor external data memory load error
Audio DSP core program memory load error
Audio DSP core upper coefficient memory load error
Audio DSP core upper data memory load error
Invalid memory select
0
0
–
–
–
–
1
–
0
0
–
–
–
1
–
–
0
0
–
–
1
–
–
–
0
0
–
1
–
–
–
–
0
0
1
–
–
–
–
–
1
1
1
1
0
0
0
0
End-of-load header error
1
1
1
1
1
1
1
1
N, IC sampling clock is 33 MHz divided by 2N
No errors
0
0
0
0
0
0
0
0
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9.4 I2C Memory Load Control and Data Registers (0x04 and 0x05)
Registers 0x04 (Table 9-4) and 0x05 (Table 9-5) allow the user to download TAS3204 program code and
data directly from the system I2C controller. This mode is called the I2C slave mode (from the TAS3204
point of view). See the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details.
The I2C slave memory load port permits the system controller to load the TAS3204 memories as an
alternative to having the TAS3204 load its memory from EEPROM.
•
•
•
•
•
Micro program memory
Micro extended memory
DAP program memory
DAP coefficient memory
DAP data memory
The transfer is performed by writing to two I2C registers. The first register is a eight byte register that holds
the checksum, the memory to be written, the starting address, the number of data bytes to be transferred.
The second location holds 8 bytes of data. The memory load operation starts with the first register being
set. Then the data is written into the second register using the format shown. After the last data byte is
written into the second register, an additional two bytes are written which contain the two-byte checksum.
At that point, the transfer is complete and status of the operation is reported in the status register. The end
checksum is always contained in the last two bytes of the data block.
Table 9-4. TAS3204 Memory Load Control Register (0x04)
BYTE
DATA BLOCK FORMAT
SIZE
NOTES
Checksum of bytes 2 through N + 8. If this is a termination header,
this value is 00 00.
1–2
Checksum code
2 bytes
0: Microprocessor program memory
1: Microprocessor external data memory
2: Audio DSP core program memory
3: Audio DSP core coefficient memory
4: Audio DSP core data memory
5: Audio DSP core upper data memory
6: Audio DSP core upper coefficient memory
7–15: Reserved for future expansion
3-4
Memory to be loaded
2 bytes
1 byte
5
Unused
Reserved for future expansion
6–7
7–8
Starting TAS3204 memory address
Number of data bytes to be transferred
2 bytes If this is a termination header, this value is 0000.
2 bytes If this is a termination header, this value is 0000.
Table 9-5. TAS3204 Memory Load Data Register (0x05)
BYTE
8-BIT DATA
28-BIT DATA
0000 D27–D24
D7–D0
48-BIT DATA
0000 0000
0000 0000
D47–D40
D39–D32
D31–D24
D23–D16
D15–D8
54-BIT DATA
0000 0000
00 D53–D48
D47–D40
D39–D32
D31–D24
D23–D16
D15–D8
1
2
3
4
5
6
7
8
Datum 1 D7–D0
Datum 2 D7–D0
Datum 3 D7–D0
Datum 4 D7–D0
Datum 5 D7–D0
Datum 6 D7–D0
Datum 7 D7–D0
Datum 8 D7–D0
D15–D8
D7–D0
0000 D27–D24
D23–D16
D15–D8
D7–D0
D7–D0
D7–D0
I2C Register Map
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9.5 Memory Access Registers (0x06 and 0x07)
Registers 0x06 (Table 9-6) and 0x07 (Table 9-7) allow the user to access the internal resources of the
TAS3204. See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details.
Table 9-6. Memory Select and Address Register (0x06)
D31
D30
D29
D28
D27
D26
D25
D24
DESCRIPTION
–
–
–
–
–
–
–
–
Unused
D23
0
D22
0
D21
0
D20
0
D19
0
D18
0
D17
0
D16
1
DESCRIPTION
Audio DSP core coefficient memory select
Audio DSP core data memory select
Reserved
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
Microprocessor internal data memory select
Microprocessor external data memory select
SFR select
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
Microprocessor program RAM select
Audio DSP core program RAM select
Audio DSP core upper memory select
Audio DSP core program RAM select
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
D15
D14
D13
D12
D11
D10
D9
D8
DESCRIPTION
A0
A1
A2
A3
A4
A5
A6
A7
Memory address
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
A8
A9
A10
A11
A12
A13
A14
A15 Memory address
Table 9-7. Data Register (Peek and Poke) (0x07)
D63
D62
D61
D60
D59
D58
D57
D56
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
D63
D62
D61
D60
D59
D58
D57
D56 Data to be written or read
D55
D54
D53
D52
D51
D50
D49
D48
D55
D54
D53
D52
D51
D50
D49
D48 Data to be written or read
D47
D46
D45
D44
D43
D42
D41
D40
D47
D46
D45
D44
D43
D42
D41
D40 Data to be written or read
D39
D38
D37
D36
D35
D34
D33
D32
D39
D38
D37
D36
D35
D34
D33
D32 Data to be written or read
D31
D30
D29
D28
D27
D26
D25
D24
D31
D30
D29
D28
D27
D25
D26
D25 Data to be written or read
D23
D22
D21
D20
D19
D18
D17
D16
D23
D22
D21
D20
D19
D18
D17
D16 Data to be written or read
D15
D14
D13
D12
D11
D10
D9
D8
D15
D14
D13
D12
D11
D10
D9
D8
Data to be written or read
Data to be written or read
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
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9.6 Device Version (0x08)
Table 9-8. Device Version
D31
D30
D29
D28
D27
D26
D25
D24
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
–
–
–
–
–
–
–
–
Firmware definable
Firmware definable
Firmware definable
TAS3204 device version
D23
D22
D21
D20
D19
D18
D17
D16
–
–
–
–
–
–
–
–
D15
D14
D13
D12
D11
D10
D9
D8
–
–
–
–
–
–
–
–
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
9.7 Analog Power Down Control (0x10 and 0x11), ESFR (0xE1 and 0xE2)
ESFR 0xE1, 0xE2 have the same bit mapping and functions as IC registers 0x10, 0x11, respectively.
Table 9-9. Analog Power Down Control 1 (0x10/0xE1)
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
1
DESCRIPTION
Central reference enable
–
–
–
–
–
–
–
0
Power down central reference
ADC1 enable
–
–
–
–
–
–
1
–
–
–
–
–
–
–
0
–
ADC1 power down
–
–
–
–
–
1
–
–
ADC2 enable
–
–
–
–
–
0
–
–
ADC2 power down
–
–
–
–
1
–
–
–
ADC reference enable
ADC reference power down
DAC reference enable
DAC reference power down
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
–
0
–
–
–
–
Table 9-10. Analog Power Down Control 2 (0x11/0xE2)
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
D6
–
–
–
–
–
–
–
–
–
–
–
–
1
0
–
–
D5
–
–
–
–
–
–
–
–
–
–
1
0
–
–
–
–
D4
–
–
–
–
–
–
–
–
1
0
–
–
–
–
–
–
D3
–
–
–
–
–
–
1
0
–
–
–
–
–
–
–
–
D2
–
–
–
–
1
0
–
–
–
–
–
–
–
–
–
–
D1
–
–
1
0
–
–
–
–
–
–
–
–
–
–
–
–
D0
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DESCRIPTION
DAC1 left enable
DAC1 left power down
DAC1 right enable
DAC1 right power down
DAC2 left enable
DAC2 left power down
DAC2 right enable
DAC2 right power down
Line out 1 left enable
Line out 1 left power down
Line out 1 right enable
Line out 1 right power down
Line out 2 left enable
Line out 2 left power down
Line out 2 right enable
Line out 2 right power down
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9.8 Analog Input Control (0x12), ESFR (0xE3)
ESFR 0xE3 has the same bit mapping and functions as IC register 0x12.
Table 9-11. Analog Input Control
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
D6
–
–
–
–
–
–
–
–
–
–
–
–
0
1
–
–
D5
–
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
D4
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
D3
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
D2
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
D1
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
–
D0
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DESCRIPTION
–
Select input 1 to ADC 1
–
Select input 1 to ADC 2
–
Select input 2 to ADC 2
–
Select input 2 to ADC 2
–
Select input 3 to ADC 2
–
Select input 3 to ADC 2
ADC 1 differential input
ADC 1 single ended input
ADC 2 differential input
ADC 2 single ended input
9.9 Dynamic Element Matching (0x13), ESFR (0XE4)
ESFR 0xE4 has the same bit mapping and functions as IC register 0x13.
Table 9-12. Dynamic Element Matching
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
ADC dynamic element matching algorithm enabled (recommended
setting)
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
–
0
1
–
–
1
–
–
–
–
ADC dynamic element matching algorithm disabled
Dynamic weighted averaging enabled (recommended setting)
Dynamic weighted averaging disabled
Unused
Unused
Fast charge of cap on VREF (filtering disabled – recommended setting
at startup)
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
Slow charge of cap on VREF (filtering enabled – recommended setting
during normal operation)
–
–
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
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9.10 Current Control Select (0x14, 0x15, 0x17, 0x18), ESFR (0xE5, 0xE6, 0xE7, 0xE9)
ESFR 0xE5, 0xE6, 0xE7, 0xE9 have the same bit mapping and functions as IC register 0x14, 0x15, 0x17,
and 0x18, respectively.
Table 9-13. Current Control Select (0x14/0xE5)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
ADC2 summer current setting (left and right) = 130% of nominal current
(recommended setting)
–
–
–
–
–
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
ADC2 summer current setting (left and right) = 100% of nominal current
ADC2 summer current setting (left and right) = 100% of nominal current
ADC2 summer current setting (left and right) = 70% of nominal current
ADC2 quantizer current setting (left and right) = 137.5% of nominal
current (recommended setting)
–
–
–
–
0
0
–
–
–
–
–
–
–
–
–
–
0
1
1
0
–
–
–
–
ADC2 quantizer current setting (left and right) = 100% of nominal current
ADC2 quantizer current setting (left and right) = 100% of nominal current
ADC2 quantizer current setting (left and right) = 62.5% of nominal
current
–
–
–
–
–
0
0
1
1
–
–
–
–
–
0
1
0
1
–
0
0
1
1
–
–
–
–
–
0
1
0
1
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC2 third integrator current setting (left and right) = 130% of nominal
current (recommended setting)
ADC2 third integrator current setting (left and right) = 100% of nominal
current
ADC2 third integrator current setting (left and right) = 100% of nominal
current
ADC2 third integrator current setting (left and right) = 70% of nominal
current
ADC2 reference buffer current setting (left and right) = 130% of nominal
current (recommended setting)
ADC2 reference buffer current setting (left and right) = 100% of nominal
current
ADC2 reference buffer current setting (left and right) = 100% of nominal
current
ADC2 reference buffer current setting (left and right) = 70% of nominal
current
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Table 9-14. Current Control Select (0x15/0xE6)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
ADC2 second integrator current setting (left and right) = 130% of
nominal current
–
–
–
–
–
–
0
0
(recommended setting)
ADC2 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
ADC2 second integrator current setting (left and right) = 100% of
nominal current
ADC2 second integrator current setting (left and right) = 70% of
nominal current
ADC2 second integrator current setting (left and right) = 130% of
nominal current
–
–
–
–
0
0
–
–
(recommended setting)
ADC2 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
ADC2 first integrator current setting (left and right) = 100% of nominal
current
ADC2 first integrator current setting (left and right) = 70% of nominal
current
–
–
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC2 current for common mode buffer to integrator 1 = 3.5 µA
ADC2 current for common mode buffer to integrator 1 = 2.0 µA
ADC2 current for common mode buffer to integrator 2 and 3 = 3.5 µA
ADC2 current for common mode buffer to integrator 2 and 3 = 2.0 µA
ADC2 current for the buffer to the ADC sampling switches = 3.5 µA
ADC2 current for the buffer to the ADC sampling switches = 2.0 µA
ADC2 current for the reference buffer to the ADC DAC = 3.5 µA
ADC2 Current for the Reference Buffer to The ADC DAC = 2.0 µA
I2C Register Map
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Table 9-15. Current Control Select (0x17/0xE7)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
ADC1 summer current setting (left and right) = 130% of nominal
–
–
–
–
–
–
0
0
current
(Recommended Setting)
ADC1 summer current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
ADC1 summer current setting (left and right) = 100% of nominal
current
ADC1 summer current setting (left and right) = 70% of nominal
current
ADC1 quantizer current setting (left and right) = 137.5% of nominal
–
–
–
–
0
0
–
–
current
(recommended setting)
ADC1 quantizer current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
ADC1 quantizer current setting (left and right) = 100% of nominal
current
ADC1 quantizer current setting (left and right) = 62.5% of nominal
current
ADC1 third integrator current setting (left and right) = 130% of
nominal current
–
–
0
0
–
–
–
–
(Recommended Setting)
ADC1 third integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
ADC1 third integrator current setting (left and right) = 100% of
nominal current
ADC1 third integrator current setting (left and right) = 70% of nominal
current
ADC1 reference buffer current setting (left and right) = 130% of
nominal current
0
0
–
–
–
–
–
–
(Recommended Setting)
ADC1 reference buffer current setting (left and right) = 100% of
nominal current
0
1
1
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC1 reference buffer current setting (left and right) = 100% of
nominal current
ADC1 reference buffer current setting (left and right) = 70% of
nominal current
I2C Register Map
56
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Table 9-16. Current Control Select (0x18/0xE9)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
ADC1 second integrator current setting (left and right) = 130% of
nominal current
–
–
–
–
–
–
0
0
(recommended setting)
ADC1 second integrator current setting (left and right) = 100% of
nominal current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
ADC1 second integrator current setting (left and right) = 100% of
nominal current
ADC1 second integrator current setting (left and right) = 70% of
nominal current
ADC1 second integrator current setting (left and right) = 130% of
nominal current
–
–
–
–
0
0
–
–
(recommended setting)
ADC1 first integrator current setting (left and right) = 100% of nominal
current
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
ADC1 first integrator current setting (left and right) = 100% of nominal
current
ADC1 first integrator current setting (left and right) = 70% of nominal
current
–
–
–
–
0
0
1
1
–
–
–
–
0
1
0
1
0
0
1
1
–
–
–
–
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC1 current for common mode buffer to integrator 1 = 3.5 µA
ADC1 current for common mode buffer to integrator 1 = 2.0 µA
ADC1 current for common mode buffer to integrator 2 and 3 = 3.5 µA
ADC1 current for common mode buffer to integrator 2 and 3 = 2.0 µA
ADC1 current for the buffer to the ADC sampling switches = 3.5 µA
ADC1 current for the buffer to the ADC sampling switches = 2.0 µA
ADC1 current for the reference buffer to the ADC DAC = 3.5 µA
ADC1 current for the reference buffer to the ADC DAC = 2.0 µA
I2C Register Map
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9.11 DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB, 0xEC, 0xEE)
ESFR 0xEB, 0xEC, and 0xED have the same bit mapping and functions as IC register 0x1A, 0x1B, and
0x1D, respectively.
Table 9-17. DAC Control (0x1A/0xEB)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
DAC1 current control for DAC local reference block and lineout amps
–
–
–
–
–
–
0
0
= default
(recommended setting)
DAC1 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
DAC2 current control for DAC local reference block and lineout amps
–
–
–
–
0
0
–
–
= default
(recommended setting)
DAC2 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C Register Map
58
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Table 9-18. DAC Control (0x1B/0xEC)
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D3
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
D2
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
D1
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
–
D0
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DESCRIPTION
DAC1 chopper stabilization disable
DAC1 chopper stabilization enable
DAC2 chopper stabilization disable
DAC2 chopper stabilization enable
DC offset subtraction in DACs 1 and 2 disable
DC offset subtraction in DACs 1 and 2 enable
Connected to microprocessor SDA2
–
–
–
–
–
–
–
–
Table 9-19. DAC Control (0x1D/0xEE)
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
DAC1 current control for DAC local reference block and lineout amps
–
–
–
–
–
–
0
0
= default
(recommended setting)
DAC1 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
DAC1 current control for DAC local reference block and lineout amps
= 75% bias current
DAC2 current control for DAC local reference block and lineout amps
–
–
–
–
0
0
–
–
= default
(recommended setting)
DAC2 current control for DAC local reference block and lineout amps
= 125% bias current
–
–
–
–
–
–
–
–
–
–
–
–
0
1
1
1
0
1
–
–
–
–
–
–
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
DAC2 current control for DAC local reference block and lineout amps
= 75% bias current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C Register Map
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9.12 ADC and DAC Reset (0x1E), ESFR (0xFB)
ESFR 0xFB has the same bit mapping and functions as IC register 0x1E.
Table 9-20. ADC and DAC Reset (0x1E/0xFB)
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
D6
–
–
–
–
–
–
–
–
–
–
–
–
0
1
–
–
D5
–
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
D4
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
D3
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
D2
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
D1
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
–
D0
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DESCRIPTION
–
ADC reset channel 1
–
ADC reset channel 2
–
ADC reset channel 3
–
ADC reset channel 4
–
DAC reset channel 1
–
DAC reset channel 2
–
DAC reset channel 3
–
DAc reset channel 4
9.13 ADC Input Gain Control (0x1F), ESFR (0xFA)
Table 9-21. ADC Input Gain Control (0x1F/0xFA)
D7
–
–
–
–
–
–
–
–
–
–
–
–
0
0
1
1
D6
–
–
–
–
–
–
–
–
–
–
–
–
0
1
0
1
D5
–
–
–
–
–
–
–
–
0
0
1
1
–
–
–
–
D4
–
–
–
–
–
–
–
–
0
1
0
1
–
–
–
–
D3
–
–
–
–
0
0
1
1
–
–
–
–
–
–
–
–
D2
–
–
–
–
0
1
0
1
–
–
–
–
–
–
–
–
D1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
–
–
D0
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
DESCRIPTION
Channel 1Sinc input gain control = 0 dB
Channel 1Sinc input gain control = +30 dB
Channel 1Sinc input gain control = +600 dB
Channel 1Sinc input gain control = 0 dB
Channel 2Sinc input gain control = 0 dB
Channel 2Sinc input gain control = +30 dB
Channel 2Sinc input gain control = +60 dB
Channel 2Sinc input gain control = 0 dB
Channel 3Sinc input gain control = 0 dB
Channel 3Sinc input gain control = +30 dB
Channel 3Sinc input gain control =+60 dB
Channel 3Sinc input gain control = 0 dB
Channel 4Sinc input gain control = 0 dB
Channel 4Sinc input gain control = +30 dB
Channel 4Sinc input gain control = +60 dB
Channel 4Sinc input gain control = 0 dB
I2C Register Map
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9.14 MCLK_OUT Divider (0x21 and 0x22)
Table 9-22. MCLK_OUT 2 (0x21)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
1
DESCRIPTION
MCLK_OUT2 frequency is 6.144 MHz/(divider+1)
Table 9-23. MCLK_OUT 3 (0x22)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
DESCRIPTION
MCLK_OUT3 frequency is 512 kHz/(divider+1)
9.15 Digital Cross Bar (0x30 to 0x3F)
Table 9-24. Digital Cross Bar (0x30 to 0x3F)
REGISTER
NAME
SUBADDRESS
NO. OF BYTES
CONTENTS
INITIALIZATION VALUE
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x30
CH1 Input Mixer
CH2 Input Mixer
CH3 Input Mixer
CH4 Input Mixer
CH5 Input Mixer
32
Input cross bar mux
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x31
0x32
0x33
0x34
32
32
32
32
Input cross bar mux
Input cross bar mux
Input cross bar mux
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
I2C Register Map
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Table 9-24. Digital Cross Bar (0x30 to 0x3F) (continued)
REGISTER
NAME
SUBADDRESS
NO. OF BYTES
CONTENTS
INITIALIZATION VALUE
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x35
CH6 Input Mixer
CH7 Input Mixer
CH8 Input Mixer
CH1 Output Mixer
CH2 Output Mixer
CH3 Output Mixer
CH4 Output Mixer
CH5 Output Mixer
32
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
32
32
32
32
32
32
32
Input cross bar mux
Input cross bar mux
Input cross bar mux
Input cross bar mux
Input cross bar mux
Input cross bar mux
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
I2C Register Map
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Table 9-24. Digital Cross Bar (0x30 to 0x3F) (continued)
REGISTER
NAME
SUBADDRESS
NO. OF BYTES
CONTENTS
INITIALIZATION VALUE
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
0x00 00 00 00
0x3D
0x3E
0x3F
CH6 Output Mixer
CH7 Output Mixer
CH8 Output Mixer
32
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
0x00 00 00 00
32
32
Input cross bar mux
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x00 00 00 00
0x08 00 00 00
Input cross bar mux
9.16 Extended Special Function Registers (ESFR) Map
See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details on ESFR.
Table 9-25. Extended Special Fucntion Registers (ESFR)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
8-bit asynchronous rstz
positive edge triggered
Reset low
Data to be transferred from microprocessor
to I2C
I2C
84
di_o
8
OUT
Data to be transferred from I2C to
microprocessor during slave write in I2C
slave-write mode if the MCU controls I2C
interface
I2C
85
86
da_i
8
IN
IN
NO REG - direct input
NO REG – direct input
Indicates the type of information being
relayed to the microprocessor. This affects
how the microprocessor changes the data
that follows the subaddress.
I2C
sub_addr_i
8
I2C
I2C
I2C
I2C
91
92
93
94
data_out1_i
data_out2_i
data_out3_i
data_out4_i
8
8
8
8
IN
IN
IN
IN
NO REG – direct input
NO REG – direct input
NO REG – direct input
NO REG – direct input
These registers are used to deliver data
from the I2C block to the microprocessor.
8-bit asynchronous rstz
positive edge triggered
Reset Low
Address of I2C internal registers. See Mentor
I2C product specification.
I2C
SAP
95
96
97
A1
A_o
3
8
8
5
OUT
OUT
OUT
OUT
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SAP WORD byte
i2s_word_byte_t
i2s_mode_byte_t
MLRCLK_t
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SAP mode byte
SAP
5-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification MLRCLK field
CLOCK
I2C Register Map
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Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
A2
MAPPED_TO
SCLK_t
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
8-bit asynchronous rstz
positive edge triggered
Reset Low
Bit definition follows functional spec
definition for specification SCLK field
8
4
8
5
2
3
8
8
8
4
OUT
CLOCK
DELAY_MEM
DELAY_MEM
DELAY_MEM
VOLUME
4-bit asynchronous rstz
positive edge triggered
Reset Low
A3
addr_sel_t
addr_t
OUT
Delay memory select lines
8-bit asynchronous rstz
positive edge triggered
Reset Low
A4
OUT
Delay memory address bus
5-bit asynchronous rstz
positive edge triggered
Reset Low
A5
addr_t
OUT
Delay memory address bus high bits
Specify slew rate 0, 1, 2 (2048, 4096, 8192)
Host control channel specification
2-bit asynchronous rstz
positive edge triggered
Reset Low
A6
vol_mode_i_t
volume_index_i_t
OUT
3-bit asynchronous rstz
positive edge triggered
Reset Low
A7
OUT
VOLUME
8-bit asynchronous rstz
positive edge triggered
Reset Low
A9
OUT
VOLUME
8-bit asynchronous rstz
positive edge triggered
Reset Low
AA
AB
AC
vol_data_i_t
vol_data_i_t
vol_data_i_t
OUT
VOLUME
Volume coefficient
8-bit asynchronous rstz
positive edge triggered
Reset Low
OUT
VOLUME
4-bit asynchronous rstz
positive edge triggered
Reset Low
OUT
VOLUME
AD
AE
AF
B1
B2
D6
D7
To_micro_i[7:0]
To_micro_i[15:8]
To_micro_i[23:16]
To_micro_i[31:24]
To_micro_i[39:32]
To_micro_i[47:40]
To_micro_i[53:48]
8
8
8
8
8
8
8
IN
IN
IN
IN
IN
IN
IN
DSP
DSP
DSP
DSP
DSP
DSP
DSP
NO REG – direct input
NO REG – direct input
NO REG – direct input
NO REG – direct input
NO REG – direct input
NO REG – direct input
NO REG – direct input
Data bus from DSP to the microprocessor
8-bit asynchronous rstz
positive edge triggered
Reset Low
B3
Data_to_DSP_o[7:0]
8
OUT
DSP
8-bit asynchronous rstz
positive edge triggered
B4
B5
Data_to_DSP_o[15:0]
Data_to_DSP_o[23:16]
8
8
OUT
OUT
DSP
DSP
8-bit asynchronous rstz
positive edge triggered
8-bit asynchronous rstz
positive edge triggered
Reset Low
B6
B7
B9
BA
BB
Data_to_DSP_o[31:24]
Data_to_DSP_o[39:32
Data_to_DSP_o[47:40]
Data_to_DSP_o[53:48]
micro_addr_o[7:0]
8
8
8
8
8
OUT
OUT
OUT
OUT
OUT
DSP
DSP
DSP
DSP
DSP
Data bus from microprocessor to the DSP
8-bit asynchronous rstz
positive edge triggered
Reset Low
8-bit asynchronous rstz
positive edge triggered
Reset Low
8-bit asynchronous rstz
positive edge triggered
Reset Low
8-bit asynchronous rstz
positive edge triggered
Reset Low
Microprocessor uses these 16 bits to set
DSP RAM and Micro I addresses
I2C Register Map
64
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AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
Microprocessor uses these 16 bits to set
DSP RAM and Micro I addresses
Bit 10 of the address selects between audio
DSP coefficient and audio DSP data
memory
8-bit asynchronous rstz
positive edge triggered
Reset Low
BC
micro_addr_o[13:8]
8
OUT
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
BD
BE
BF
C1
C2
C3
C4
C5
C6
C7
C9
CA
Mode0_o
Mode3_o
1
1
1
1
1
1
1
1
1
1
1
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
DSP
DSP
Miscellaneous signal for
microprocessor-DSP communication.
This is not a bit-addressable register, but
contains bit data. The firmware must read in
the data, mask the change, and write it back
out.
1-bit asynchronous rstz
positive edge triggered,
Reset low
1-bit asynchronous rstz
positive edge triggered
Reset low
Mode4_o
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C1 Mode5_o
Mode6_o
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
Miscellaneous signal for
DSP
microprocessor-DSP communication.
This is not a bit-addressable register, but
contains bit data. The firmware must read in
the data, mask the change, and write it back
out.
1-bit asynchronous rstz
positive edge triggered
Reset low
Mode7_o
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
Mode8_o
DSP
1-bit asynchronous rstz
positive edge triggered
Reset Low
GPIO_IN_t
gpio_enz_t
gpio_out_t
cs1
DSP
Registered input GPIO sense line
4-bit asynchronous rstz
positive edge triggered
Reset Low
GPIO bidirect configuration—low → output,
high → input
OUT
OUT
IN
GPIO
GPIO
CHIP_SEL
TONE
1-bit asynchronous rstz
positive edge triggered
Reset Low
Drive value on GPIO line when configured
as output
1-bit asynchronous rstz
positive edge triggered
Reset Low
Reset-low sense lines for chip-select
input/output
8-bit asynchronous rstz
positive edge triggered
Reset Low
tb_loop_count_t
OUT
Tone slew rate counter configuration
CB
CC
CD
dlymemif_out
dlymemif_out
dlymemif_out
8
8
8
IN
IN
IN
DLY_MEM
DLY_MEM
DLY_MEM
NO REG – direct input
NO REG – direct input
NO REG – direct input
Low-byte delay interface date port
High-byte delay interface date port
High-byte delay interface date port
1-bit asynchronous rstz
positive edge triggered
Reset low
CE
CF
D0
D1
D2
D3
D4
cntrl1_treb_active_t
cntrl2_treb_active_t
cntrl3_treb_active_t
cntrl4_treb_active_t
cntrl1_bass_active_t
cntrl2_bass_active_t
cntrl3_bass_active_t
1
1
1
1
1
1
1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TONE
TONE
TONE
TONE
TONE
TONE
TONE
1-bit asynchronous rstz
positive edge triggered
Reset low
1-bit asynchronous rstz
positive edge triggered
Reset low
Schedule tone coefficient calculations in the
audio DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
1-bit asynchronous rstz
positive edge triggered
Reset low
1-bit asynchronous rstz
positive edge triggered
Reset low
1-bit asynchronous rstz
positive edge triggered
Reset low
Schedule tone coefficient calculations in the
audio DSP
I2C Register Map
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
1-bit asynchronous rstz
positive edge triggered
Reset low
Schedule tone coefficient calculations in the
audio DSP
D5
cnrtrl4_bass_active_t
1
1
OUT
TONE
PULSE REGISTER
Slave read: set high when MCU recognizes
that the SLAVE_READ bit on the I2C has
been set high.
Slave write: if the RCVD_DATA_STAT bit is
set high by the I2C, microprocessor sets IRG
high in response.
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
Reset low
I2C
C0(0)
C0(1)
I2c_irg_o
OUT
OUT
PULSE REGISTER
I2C_MCU is set to 1 MCU assumes control
over the I2C interface. If it is set to 0, the I2C
block has control. If the microprocessor
reads a 1 on slave_read, it sends an ACK to
the I2C and sets I2C_MCU high.
1-bit asynchronous rstz
positive edge triggered
RESET HI
I2C
I2c_mcu_o
1
1-bit asynchronous rstz
positive edge triggered
Reset low
Signoff assertion that volume coefficients to
volume block are updated and execution is
commanded
C0(2)
C0(3)
C0(4)
C0(5)
update_volume_t
clr_dly_RAM_t
wr_t
1
1
1
1
OUT
OUT
OUT
OUT
VOLUME
DLY_MEM
I2C
1-bit asynchronous rstz
positive edge triggered
Reset low
Used during initialization to inspire
self-clearing logic activation to the delay
RAM
PULSE REGISTER
I2C write pulse for slave transmit and master
transmit
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
The I2C has two registers to which the
microprocessor can write. This signal selects
one of them.
1-bit asynchronous rstz
positive edge triggered
I2C
I2c_sel_o
PULSE REGISTER
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
When DSP_HOST = 1, the microprocessor
has direct control of the RAMs and pulses
this signal to write to them.
C0(6)
C0(7)
micro_RAM_we_req_o
micro_rd_req_o
1
1
OUT
OUT
DSP
DSP
When DSP_HOST is high and the
microprocessor has complete control of the
DSP RAMS, this bit is N/A. When
DSP_HOST is low, the microprocessor uses
this bit to submit a read request to the DSP.
1-bit asynchronous rstz
positive edge triggered
ONE SHOT (PULSE)
C8(0)
C8(2)
power_down_in
vol_busy_o
1
1
IN
IN
CNTL
VOL
NO REG – direct input
Power-down pin sense
1-bit asynchronous rstz
positive edge triggered
Reset High
Volume busy flag
C8(3)
C8(4)
mem_bist_i
intr
1
1
IN
IN
membist
CNTL
Direct input
Direct input
Indicates chip is in firmware BIST mode
Indicates status warp IFLAG
1-bit asynchronous rstz
positive edge triggered
Reset low
DSP sets this bit to notify microprocessor it
has captured data
C8(5)
micro_ack_I
1
IN
DSP
1-bit asynchronous rstz
positive edge triggered
Reset low
C8(6)
C8(7)
D8(0)
clearing_dly_RAM_t
dsp_rom_bist_I
1
1
1
IN
IN
DSP
DSP
Busy flag from Delay RAM Init clear process
Set HIGH to signal that DSP ROM BIST
completed successfully
NO REG – direct input
1-bit asynchronous rstz
positive edge triggered
Reset low
Set HIGH by the microprocessor. (Need
more info)
power_down_o
OUT
Multiple blks
1-bit asynchronous rstz
positive edge triggered
Reset low
D8(1)
D8(2)
D8(3)
watchdog_clr_t
slave_mode_t
addr_wr_t
1
1
1
OUT
OUT
OUT
CNTL
Strobe to the watchdog timer logic
1-bit asynchronous rstz
positive edge triggered
Reset low
Asserted to provide direct delay memory
access to the host (microprocessor)
DLY_MEM
DLY_MEM
1-bit asynchronous rstz
positive edge triggered
Reset low
Write assertion to delay memory during host
control configuration
I2C Register Map
66
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AUDIO DSP
WITH ANALOG INTERFACE
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SLES197–APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR
MAPPED_TO
micro_wr_en_i_t
host_DSP_o
NO. OF
BITS
DIRECTION
CONNECTING
BLOCK
REGISTER TYPE
DESCRIPTION
1-bit asynchronous rstz
positive edge triggered
Reset low
Write enable signal to the audio DSP
coefficients and DATA RAMs
D8(4)
D8(5)
D8(6)
D8(7)
1
1
1
1
OUT
DSP
DSP
T/B
1-bit asynchronous rstz
positive edge triggered
Reset high
Sets the DSP in host mode. Microprocessor
is in control
OUT
1-bit asynchronous rstz
positive edge triggered
Reset low
Microprocessor notifies T/B block that bass
data has been processed and is ready.
bass_data_ready_o
treble_data_ready_o
OUT
1-bit asynchronous rstz
positive edge triggered
Reset low
Microprocessor notifies T/B block that treble
data has been processed and is ready.
OUT
T/B
Audio DSP coefficient/data
00
(Depending on address bit 10)
2-bit asynchronous rstz
positive edge triggered
Reset low
01
10
11
Audio DSP instruction
Microprocessor instruction
Reserved
D9
MEM_SEL
2
OUT
MICRO DAP
1-bit asynchronous rstz
positive edge triggered
Reset low
Select Master or Slave mode by switching
mux
I2C
FC
FD
FE
i2c_ms_ctl
pc_source
sap_en_t
1
1
1
OUT
OUT
OUT
1-bit asynchronous rstz
positive edge triggered
Reset low
Changes source from microprocessor
program ROM to microprocessor program
RAM
1-bit asynchronous rstz
positive edge triggered
Reset Low
Expected to toggle high, then low, to inspire
a recent SAP change to activate.
SAP
I2C Register Map
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67
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
10 Application Information
10.1 Schematics
Figure 10-1 shows a typical TAS3204 application. In this application the following conditions apply:
•
TAS3204 is in clock-master mode. The TAS3204 generates MCLK_OUT1, SCLK_OUT, and
LRCLOK_OUT.
•
•
XTAL_IN = 24.576 MHz
I2C register 0x00 contains the default settings, which means:
–
–
–
–
Audio data word size is 24-bit input and 24-bit output.
Serial data format is 2-channel, I2S for input and output.
I2C data transfer is approximately 400 kbps for both master and slave I2C interfaces.
Sample frequency (fS) is 48 kHz, which means that fLRCLK = 48 kHz and fSCLKIN = 3.072 MHz.
•
•
Application code and data are loaded from an external EEPROM using the master I2C interface.
Application commands come from the system microprocessor to the TAS3204 using the slave I2C
interface.
Good design practice requires isolation between the digital and analog power as shown. Power supply
capacitors of 10 µF and 0.1 µF should be placed near the power supply pins AVDD (AVSS) and DVDD
(DVSS).
The TAS3204 reset needs external glitch protection. Also, reset going HIGH should be delayed until
TAS3204 internal power is good (~200 µs after power up). This is provided by the 1-kΩ resistor, 1-µF
capacitor, and diode placed near the RESET pin.
It is recommended that a 4.7-µF capacitor (fast ceramic type) be placed near pin 28 (VR_DIG). This pin
must not be used to source external components.
68
Application Information
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TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
www.ti.com
SLES197–APRIL 2007
I2S Master Mode Application
3.3 W
3.3 V
I2S Input
4.7 µF
0.1 µF
0.1 µF
EEPROM
I2S Output
I2C1_SCL
MCLK_OUT1
MCLK_OUT2
MCLK_OUT3
DVDD2
1
2
48
47
I2C1_SDA
GPIO2
GPIO1
MUTE
External
3
4
5
46
45
44
3.3 V
Controller
3.3 W
DVSS2
24.576 MHz
33 pF
CS0
MCLK_IN
XTAL_OUT
XTAL_IN
6
7
8
9
43
42
41
40
39
38
37
10 kW
PDN
DVSS1
DVDD1
VR_PLL
AVSS1
AIN1LP
AIN1LM
AIN1RP
AIN1RM
AIN2LP
3.3 W
AVDD3
33 pF
3.3 V
VR_ANA
10
11
12
0.1uF
AVSS3
3.3 V
AVSS2
3.3 W
AOUT1RP
AOUT1RM
AOUT1LP
AOUT2LM
36
35
34
13
14
15
33
16
Three Differential
Stereo Analog
Input
Two Differential
Stereo Analog
Output
3.3 V
3.3 W
0.1 µF
0.1 µF
A. Capacitors should be placed as close as possible to the power supply pins.
Figure 10-1. Typical Application Diagram
10.2 Recommended Oscillator Circuit
TAS3204
Oscillator
Circuit
C
1
r
d
XO
C
2
XI
AVSS
•
•
•
•
Crystal type = parallel-mode, fundamental-mode crystal
rd = drive-level control resistor – vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1× C2)/(C1 + C2) + CS (where CS = board stray capacitance, ~2 pF)
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Application Information
69
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2007
PACKAGING INFORMATION
Orderable Device
TAS3204PAG
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PAG
64
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS3204PAGR
TQFP
PAG
64
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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