TAS3108IADCP [TI]

数字音频处理器 | DCP | 38 | -40 to 105;


型号：	TAS3108IADCP
厂家：	TEXAS INSTRUMENTS
描述：	数字音频处理器 \| DCP \| 38 \| -40 to 105 时钟控制器微控制器微控制器和处理器光电二极管外围集成电路数字信号处理器
文件：	总63页 (文件大小：1321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Not Recommended for New Designs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

www.ti.com

SLES152B–OCTOBER 2005–REVISED NOVEMBER 2007

1 Introduction

1.1 Features

•

16-, 20-, 24-, and 32-Bit Word Sizes

•

8 channel Programmable Audio Digital Signal

Processor (DSP)

64-f_S, 128-f_S, 192-f_S, and 256-f_SSCLK to

Support Discrete 4 channel TDM, 6 channel

TDM, and 8 channel TDM Data-Transfer

Formats

•

135-MHz Maximum Speed, >2800 Processing

Cycles Per Sample at 48 kHz

•

Sample Rates of 32 kHz to 192 kHz

•

Two I²C Ports for Slave or Master Download

48-Bit Data Path and 28-Bit Coefficients

Single-Cycle, 76-Bit Multiply Accumulate

Five Simultaneous Operations Per Clock Cycle

1022 Words of 48-Bit Data Memory

Soft Volume Controller

Dither Generator

Efficient log²/2^xEstimator

Single 3.3-V Power Supply

1022 Words of 28-Bit Coefficient Memory

3K Words of 54-Bit Program RAM

38-Pin Thin Shrink Small-Outline Package

(TSSOP) (DCP)

5.88K Words of 24-Bit Delay Memory

(122.5 ms at 48 kHz)

15 Stereo/TDM Data Formats

•

AEC-Q100 (Grade 2: –40°C to 105°C)

Compliant for Automotive Applications

(TAS3108IA)

•

Independent Input/Output Data Formats

1.2 Applications

•

Automotive Sound Systems

Digital Televisions

Home Theater Systems

Mini-Component Audio

TAS3108/TAS3108IA

Audio DSP Core

SDIN1

SDIN2

SDIN3

SDIN4

SDOUT1

SDOUT2

SDOUT3

SDOUT4

Serial

Audio

Input

Port

Serial

Audio

Output

Port

48-Bit Data Path

28-Bit Coefficients

76-Bit MAC

3K Code RAM

1K Data RAM

1K Coeff. RAM

5.8K Delay RAM

Boot ROM

MCLK

LRCLK

SCLKIN

PLL

and

Clock

Control

SCLKOUT1

SCLKOUT2

Volume

Update

8051 MCU

8-Bit Microprocessor

256 IRAM

I C Port #1

I C

Interface

I C Port #2

2K ERAM

12K Code RAM

B0074-01

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Not Recommended for New Designs

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Contents

Introduction ............................................... 1

I²C Register Map........................................ 37

7.1 Clock Control Register (0x00) ...................... 38

7.2 Status Register (0x02) .............................. 41

1.1 Features .............................................. 1

1.2 Applications........................................... 1

Functional Description ................................. 3

2.1 Device Description.................................... 3

2.2 Power Supply......................................... 4

2.3 Clock Control ......................................... 4

2.4 Serial Audio Ports (SAPs) ............................ 4

2.5 M8051Warp Microprocessor.......................... 4

2.6 I²C Control Interface.................................. 4

2.7 Audio DSP Core ...................................... 5

Physical Characteristics ............................... 6

3.1 Terminal Assignments ................................ 6

3.2 Terminal Descriptions ................................ 7

3.3 Reset (RESET) ....................................... 7

3.4 Power-On Reset (RESET)............................ 8

3.5 Power Down (PDN)................................... 8

3.6 I²C Bus Control (CS0) ................................ 8

7.3

I²C Memory Load Control and Data Registers (0x04

and 0x05)............................................ 42

7.4

Memory Access Registers (0x06 and 0x07) ........ 43

Electrical Specifications .............................. 44

8.1

8.2

8.3

8.4

Absolute Maximum Ratings Over Operating

Temperature Range (unless otherwise noted) ...... 44

Package Dissipation Ratings

(TAS3108/TAS3108IA).............................. 44

Recommended Operating Conditions

(TAS3108/TAS3108IA).............................. 44

Electrical Characteristics (TAS3108/TAS3108IA)... 45

8.5 Timing Characteristics............................... 46

8.5.1 Master Clock Signals (TAS3108/TAS3108IA) ..... 46

8.5.2 Serial Audio Port Slave Mode Signals

(TAS3108/TAS3108IA).............................. 47

8.5.3 Serial Audio Port Master Mode Signals

(TAS3108/TAS3108IA).............................. 48

3.7

Programmable General Purpose I/O (GPIO)......... 8

8.5.4 Pin-Related Characteristics of the SDA and SCL

I/O Stages for F/S-Mode I²C-Bus Devices.......... 49

3.8 Input and Output Serial Audio Ports.................. 9

Algorithm and Software Development Tools for

8.5.6 Reset Timing (TAS3108/TAS3108IA) .............. 51

Application Information............................... 53

9.1 Schematics .......................................... 53

9.2 Recommended Oscillator Circuit.................... 55

TAS3108/TAS3108IA ................................... 18

Clock Controls .......................................... 19

Microprocessor Controller .......................... 27

6.1 General I²C Operations ............................. 28

6.2 Detailed I²C Operation .............................. 29

6.3 I²C Master-Mode Device Initialization .............. 31

9.3

Recommended PCB Design for TAS3108IA

Applications ......................................... 55

Contents

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2 Functional Description

2.1 Device Description

The TAS3108 and TAS3108IA are fully programmable high-performance audio processors. The devices

use an efficient, custom, multi-instruction programming environment optimized for digital audio processing

algorithms. The TAS3108/TAS3108IA architecture provides high-quality audio processing by using a 48-bit

data path, 28-bit filter coefficients, and a single-cycle 28 × 48-bit multiplier with a 76-bit accumulator. An

embedded 8051 microprocessor provides algorithm and data control for the TAS3108/TAS3108IA. The

TAS3108 is the commercial version intended for home audio and other commercial applications. The

TAS3108IA is the automotive version that is qualified for use in automotive applications.

Audio DSP Core

8 Channels

Coef.

RAM

(1022 y 28)

SDIN1

SDIN2

SDIN3

SDIN4

Serial

Audio

Port

Data

Path

SDOUT1

SDOUT2

SDOUT3

SDOUT4

Data

RAM

(1022 y 48)

8 Channels

MCLK

LRCLK

Memory

Interface

Code

RAM

(3K y 54)

Clock

Control

SCLKIN

Controller

SCLKOUT1

SCLKOUT2

Microprocessor Core

Delay

Memory

(5.8K y 24)

Internal

Data RAM

(256 y 8)

8-Bit

MCU

(8051)

Volume

Update

External

Data RAM

(2048 y 8)

Control

Registers

2ySDA

2ySCL

CSO

I C

Control

Interface

GPIO

Code

RAM

(12K y 8)

Code

ROM

AVDD

DVDD

Power Supply

B0075-01

Figure 2-1. Expanded TAS3108/TAS3108IA Functional Block Diagram

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2.2 Power Supply

The power supply contains supply regulators that provide analog and digital regulated power for various

sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are

generated on-chip from the external 3.3-V supply.

2.3 Clock Control

The TAS3108/TAS3108IA can be an audio data clock-master or clock-slave device. In clock-master mode,

it generates MCLK, SCLK, and LRCLK. In clock-slave mode, it accepts MCLK, SCLK, and LRCLK. It can

generate or accept master clocks from 6 MHz to 24.576 MHz. Master or slave operation is set via I²C

3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave

mode, the master clock frequency does not need to be an integer multiple of the sample rate.

The TAS3108/TAS3108IA does not support clock error detection. If a clock error occurs, the

TAS3108/TAS3108IA does not prevent invalid data or clocks from being output. This means that the

application system must be designed to handle clock errors.

2.4 Serial Audio Ports (SAPs)

Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins

SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-,

96-, 176.4-, or 192-kHz serial data as 16-, 20-, 24-, or 32-bit data in left justified, right justified, or I²S serial

data formats. All four ports accommodate these three 2 channel data formats.

In addition to supporting the 2 channel formats, SDIN1 and SDOUT1 also provide support for time-division

multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I²C register 0x00.

All input channels must use the same data format. All output channels must use the same data format.

However, the input and output formats can be different.

2.5 M8051Warp Microprocessor

The M8051Warp (8051) microprocessor controls I²C reads and writes and participates in some audio

processing tasks requiring multiframe (f_Speriod) processing cycles. The 8051 processor performs some

control calculations and exchanges data between the audio DSP core and the I²C interface. It also

provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin

for post-boot-up operation to be an input or an output. For more information, see the TAS3108/TAS3108IA

Firmware Programmer's Guide (SLEU067).

2.6 I²C Control Interface

The TAS3108/TAS3108IA has an I²C slave-only interface (SDA1 and SCL1) for receiving commands and

providing status to the system controller, and a separate master I²C interface (SDA2 and SCL2) to

download programs and data from external memory such as an EEPROM. See Section 6 for more

information.

Functional Description

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2.7 Audio DSP Core

The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit

and data and coefficient memory blocks. The primary features of the audio DSP core are:

•

48-bit data path with 76-bit accumulator

Hardware multiplier (28 bit × 48bit)

Read/write single-cycle memory access

Input is 48-bit 2s-complement data multiplexed in from the SAP immediately following an LRCLK pulse.

Output is 32-bit 2s-complement data on four buses.

Separate control for writing to delay memory

Separate coefficient memory (28 bit) and data memory (48 bit)

Linear feedback shift register (LFSR) is a random-number generator that can be used to dither the

audio.

•

Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into

the same 5.88K memory space for convenient addressing by the microprocessor.

Memory interface block contains four pointers – two for data memory and two for coefficient memory.

The audio DSP core is used to implement all audio processing functions.

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3 Physical Characteristics

3.1 Terminal Assignments

DCP PACKAGE

(TOP VIEW)

AVSS

VR_PLL

XTALI

AVDD

RESERVED

PLL2

PLL1

PLL0

RESERVED

RESET

PDN

DVDD

DVSS

VR_DIG

SDOUT1

SDOUT2

SDOUT3

SDOUT4

SCLKOUT2

SCLKOUT1

MCLKO

SCLKIN

XTALO

MCLKI

MICROCLK_DIV

CS0

GPIO

DVDD

DVSS

SDIN1

SDIN2

SDIN3

SDIN4

SDA1

SCL1

SDA2

SCL2

LRCLK

P0033-01

Physical Characteristics

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3.2 Terminal Descriptions

TERMINAL

NAME

PULLUP/

INPUT/

PULLDOWN⁽²⁾

DESCRIPTION

OUTPUT⁽¹⁾

NO.

AVDD

AVSS

Analog power supply (3.3 V)

Analog ground

CS0

Pulldown

Chip select

DVDD

9, 30

10, 29

Digital power supply input (3.3 V)

Digital ground

DVSS

GPIO

I/O

Pullup

GPIO control (user programmable)

Sample rate clock (f_S)

LRCLK

Pulldown

MCLKIN

MCLKO

MICROCLK_DIV

Master clock input (connect to ground when not in use)

Master clock output

Pulldown

Pullup

Internal microprocessor clock divide control

Power down. Powers down all logic and stops all clocks, active low.

Coefficient memory remains stable through the power-down cycle.

PDN

PLL0

PLL1

33, 37

Pullup

Pulldown

Pullup

PLL control 0

PLL control 1

PLL2

PLL control 2

RESERVED

RESET

SCL1

Reserved. Connect to ground

Reset, active low

I²C port 1 clock (always a slave)

I²C port 2 clock (always a master)

Bit clock input

I/O

Pullup

SCL2

SCLKIN

SCLKOUT1

SCLKOUT2

SDA1

Pulldown

I/O

Bit clock 1 out. Used to receive input serial data.

Bit clock 2 out. Used to clock output serial data.

I²C port 1 data (always a slave)

I²C port 2 data (always a master)

Serial data input 1

SDA2

SDIN1

Pulldown

SDIN2

Serial data input 2

SDIN3

Serial data input 3

SDIN4

Serial data input 4

SDOUT1

SDOUT2

SDOUT3

SDOUT4

VR_PLL

XTALI

Serial data output 1

Serial data output 2

Serial data output 3

Serial data output 4

Internal regulator. This pin must not be used to power external devices.

Oscillator input (connect to ground when not in use)

Oscillator output

XTALO

VR_DIG

Internal regulator. This pin must not be used to power external devices.

(1) I = input, O = output

(2) All pullups are 20-µA weak pullups, and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive

inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be

able to source 20 µA while maintaining a logic-1 drive level.

3.3 Reset (RESET)

The RESET pin is an asynchronous control signal that restores all TAS3108/TAS3108IA components to

the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051

starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a

device reset. A reset can be initiated by applying a logic 0 on RESET. A reset can also be issued at power

turnon by the three internal power supplies.

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As long as RESET is held LOW, the device is in the reset state. During reset, all I²C and serial data bus

operations are ignored. The I²C interface SCL and SDA lines go into a high-impedance state and remain

in that state until device initialization has completed.

The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and

setting the default register values. Once these are complete, the TAS3108/TAS3108IA enables its master

I²C interface and disables its slave I²C interface.

Then the TAS3108/TAS3108IA looks for an EEPROM as described in Section 2.6, I²C Control Interface.

3.4 Power-On Reset (RESET)

On power up, it is recommended that the TAS3108/TAS3108IA RESET be held LOW until DVDD has

reached 3.3 V. This can be done by programming the system controller or by using an external RC delay

circuit. The 1-kΩ and 1-µF values provide a delay of approximately 200 µs. The values of R and C can be

adjusted to provide other delay values as necessary.

3.5 Power Down (PDN)

PDN is a user-firmware-definable pin that is programmed in the default TAS3108 and TAS3108IA

configuration to stop all clocks in the TAS3108/TAS3108IA, while preserving the state of the device. For

more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

3.6 I²C Bus Control (CS0)

The TAS3108/TAS3108IA has a control to specify the slave and master I²C address. This control permits

up to two TAS3108/TAS3108IA devices to be placed in a system without external logic.

See Section 6.2 for a complete description of this pin.

3.7 Programmable General Purpose I/O (GPIO)

The TAS3108/TAS3108IA has one GPIO pin that is 8051 firmware programmable.

On power up or following a reset, the GPIO pin becomes an input. Afterwards, the microprocessor can

program the GPIO as an input or an output.

For more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

3.7.1 No EEPROM is Present or a Memory Error Occurs

Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the

TAS3108/TAS3108IA is in one of two modes, depending on the setting of the GPIO pin.

•

GPIO pin is logic HIGH (through a 20-kΩ resistor)

With the GPIO pin held HIGH during initialization, the TAS3108/TAS3108IA comes up in the default

configuration with the serial data outputs not active. Once the TAS3108/TAS3108IA has completed

the default initialization procedure and after the status register is updated and the I²C slave

interface is enabled, the GPIO pin is an output and is driven LOW. Following the HIGH-to-LOW

transition of the GPIO pin, the system controller can access the TAS3108/TAS3108IA through the

I²C interface and read the status register to determine the load status.

If a memory-read error occurs, the TAS3108/TAS3108IA reports the error in the status register (I²C

subaddress 0x02).

•

GPIO pin is logic LOW (through a 20-kΩ resistor)

With GPIO pin held LOW during initialization, the TAS3108/TAS3108IA comes up in an I/O test

configuration. In this case, once the TAS3108/TAS3108IA completes its default test initialization

procedure, the status register is updated, the I²C slave interface is enabled, and the

TAS3108/TAS3108IA streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to

SDOUT2, etc.

In this configuration, the GPIO pin is an output signal that is driven LOW. If the external logic is no

Physical Characteristics

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longer driving the GPIO pin low after the load has completed (~100 ms following a reset if no EEPROM

is present), the state of the GPIO pin can be observed.

Then the system controller can access the TAS3108/TAS3108IA through the I²C interface and read the

status register to determine the load status.

If the GPIO pin state is not observed, the only indication that the device has completed its initialization

procedure is that the TAS3108/TAS3108IA streams audio and the I²C slave interface has been enabled.

3.7.2 GPIO Pin Function After Device Is Programmed

Once the TAS3108/TAS3108IA has been programmed, either through a successful boot load or via slave

I²C download, the operation of GPIO can be programmed to be an input and/or output.

3.8 Input and Output Serial Audio Ports

The TAS3108/TAS3108IA supports system architectures that require data format conversions between

TDM and non-TDM of the same format type without the need for additional glue logic. In addition, the

TAS3108/TAS3108IA supports data format conversions between right justified and I²S and between left

justified and I²S. All the supported conversions are listed in Table 3-1. If the input port is configured for a

TDM format, only SDIN1 is active. If a TDM format is selected for the output port, only SDOUT1 is active.

Table 3-1. Supported Conversions

INPUT SAP

OUTPUT SAP

(SDIN1, SDIN2, SDIN3, SDIN4)

(SDOUT1, SDOUT2, SDOUT3, SDOUT4)

2 channel left justified

TDM left justified

2 channel I²S

TDM left justified

2 channel I²S

2 channel left justified

TDM I²S

2 channel I²S

2 channel leftjustified

2 channel right justified

2 channel I²S

2 channel right justified

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Table 3-2. Serial Data Input and Output Formats

INPUT

CONTROL CONTROL

OUTPUT

WORD

LENGTHS

DATA RATES

(kHz)

MAX

SCLK

MODE

SERIAL FORMAT

IM[3:0]

0000

0001

0010

0011

0110

0100

0111

0101

1000

OM[3:0]

0000

0001

0010

0011

0110

0100

0111

0101

1000

Left justified

Right justified

16, 20, 24, 32

16, 20, 24

2 channel

32–192

12.288

I²S

8 channel left justified

8 channel I²S

16, 20, 24, 32

16, 20, 24

32–96 MCLK

32–48 crystal

24.576 MCLK

12.288 crystal

Time-division

multiplexed (4,

6, or 8

6 channel left justified

6 channel I²S

16, 20, 24, 32

16, 20, 24

32–96

18.432

channel)

4 channel left justified

4 channel I²S

16, 20, 24, 32

16, 20, 24

32–192 MCLK

32–96 crystal

24.576 MCLK

12.288 crystal

Input Port

Word Size

Output Port

Word Size

14 13

11 10

0x00

XX IW[2:0] OW[2:0] DWFMT (Data Word Format)

Slave Addr Ack

Subaddr

Ack

xxxxxxxx

Ack

xxxxxxxx

Ack

DWFMT

Ack

IOM

Ack

IM[3:0]

OM[3:0]

Input Port

Format

Output Port

Format

R0003-01

Figure 3-1. Serial Data Controls

Table 3-3. Serial Data Input and Output Data Word

Sizes

IW1, OW1

IW0, OW0

FORMAT

32-bit data

16-bit data

20-bit data

24-bit data

Physical Characteristics

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Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass

updates.

Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet

operation. However, care must be taken to ensure that the mute command has completed before the SAP

is commanded to reconfigure. Similarly, the TAS3108/TAS3108IA should not be commanded to unmute

until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration

change while a volume or bass or treble update is taking place can cause the update not to be completed

properly.

When the TAS3108/TAS3108IA is transmitting serial data, it uses the negative edge of SCLK to output a

new data bit. The TAS3108/TAS3108IA samples incoming serial data on the rising edge of SCLK. The

TAS3108/TAS3108IA only supports TDM, left justified, right justified, and I²S formats.

3.8.1 2 channel I²S Timing

In 2 channel I²S timing, LRCLK is LOW when left channel data is transmitted and HIGH when right

channel data is transmitted. SCLK is a bit clock running at 64 × f_S, which clocks in each bit of the data.

There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on

the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The

TAS3108/TAS3108IA masks unused trailing data-bit positions.

2-Channel I S (Philips Format) Stereo Input/Output

32 Clks

LRCLK (Note Reversed Phase)

Left Channel

Right Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22

20-Bit Mode

19 18

16-Bit Mode

15 14

T0034-04

Figure 3-2. I²S 64-f_SFormat

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3.8.2 2 Channel Left Justified Timing

In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when

right channel data is transmitted. SCLK is a bit clock running at 64 × f_Swhich clocks in each bit of the

data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written

MSB first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing

data-bit positions.

2-Channel Left-Justified Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

23 22

LSB

24-Bit Mode

23 22

20-Bit Mode

19 18

15 14

16-Bit Mode

15 14

T0034-02

Figure 3-3. Left justified 64-f_SFormat

Physical Characteristics

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3.8.3 2 Channel Right Justified Timing

In 2-channel right-justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when

right channel data is transmitted. SCLK is a bit clock running at 64 × f_S, which clocks in each bit of the

data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK

toggles. In the right-justified mode, the last bit clock before LRCLK transitions always clocks the LSB of

data. The data is written MSB first and is valid on the rising edge of the bit clock. The

TAS3108/TAS3108IA masks unused leading data-bit positions.

2-Channel Right-Justified (Sony Format) Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22

19 18

15 14

23 22

19 18

15 14

20-Bit Mode

16-Bit Mode

T0034-03

Figure 3-4. Right justified 64-f_SFormat

3.8.4 TDM Modes

The TDM modes on the TAS3108/TAS3108IA provide left justified and I²S formats. Each word in the TDM

data stream adheres to the bit placement shown in Figure 3-5 and Figure 3-6. Two cases are

illustrated—an I²S data format and a left-justified data format.

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128 Clks

LRCLK

Right Channels

Left Channels

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC5)

32-Bit Word (DAC7)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

32-Bit Word (DAC6)

32-Bit Word (DAC8)

96 Clks

LRCLK

Right Channels

Left Channels

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC5)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

32-Bit Word (DAC6)

64 Clks

LRCLK

Right Channels

Left Channels

1-Chip, 8-, 6-, 4-Channel

and Multiplexed 6-Channel Operation

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

Left-Justified Format

SCLK

LRCLK

MSB

LSB

32-Bit Mode

SCLK

31 30 29

17 16

13 12

32 Bit

24-Bit Mode

23 22 21

31 30 29 28 w w w

23 22 21 20 w w w

24 Bit

(Example)

20-Bit Mode

19 18 17

16-Bit Mode

15 14 13

T0085-01

Figure 3-5. Left-Justified TDM Formats

Physical Characteristics

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128 Clks

LRCLK

Left Channels

Right Channels

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC5)

32-Bit Word (DAC7)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

32-Bit Word (DAC6)

32-Bit Word (DAC8)

96 Clks

LRCLK

Left Channels

Right Channels

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC5)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

32-Bit Word (DAC6)

64 Clks

LRCLK

Left Channels

Right Channels

1-Chip, 8-, 6-, 4-Channel

and Multiplexed 6-Channel Operation

32-Bit Word (DAC1)

32-Bit Word (DAC3)

32-Bit Word (DAC2)

32-Bit Word (DAC4)

I2S Format

SCLK

LRCLK

MSB

LSB

24-Bit Mode

SCLK

23 22

24 Bit

(Example)

20-Bit Mode

19 18

23 22 21 w w w

16-Bit Mode

15 14

T0085-02

Figure 3-6. I²S TDM Formats

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3.8.5 SAP Input to SAP Output—Processing Flow

All SAP data format options other than I²S result in a two-sample delay from input to output, as shown in

Figure 3-7. If I²S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK in

Figure 3-7 must be inverted. However, if I²S format conversions are performed between input and output,

the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock frequency

selected for the audio DSP core relative to the sample rate of the incoming data.

The I²S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use

the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core

operate on sample windows that are 180° out of phase, with respect to the sample window used by the

output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint

of the sample period used by the audio DSP core to process the data. If the processing cycle completes

all processing tasks before the midpoint of the processing sample period, the output SAP outputs this

processed data. However, if the processing time extends past the midpoint of the processing sample

period, the output SAP outputs the data processed during the previous processing sample period. In the

former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output

is 2.5 samples.

Therefore, delay from input to output can be either 1.5 or 2.5 sample times when data format conversions

are performed that involve the I²S format. However, which delay time is obtained for a particular

application is determinable and fixed for that application, providing care is taken in the selection of

MCLKI/XTALI with respect to the incoming sample clock, LRCLK.

Physical Characteristics

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Figure 3-7. SAP Input-to-Output Latency

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4 Algorithm and Software Development Tools for TAS3108/TAS3108IA

The TAS3108/TAS3108IA algorithm and software development tool set is a combination of classical

development tools and graphical development tools. The tool set is used to build, debug, and execute

programs in both the audio DSP and 8051 sections of the TAS3108/TAS3108IA.

Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level

debuggers. The 8051 can be programmed exclusively in ANSI C.

The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051

tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator.

The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete

environment with an IDE, context-sensitive editor, assembler, and simulator/debugger.

Graphical development tooling provides a means of programming the audio DSP core and 8051 through a

graphical drag-and-drop interface using modular audio software components from a component library.

The graphical tooling produces audio DSP assembly and 8051 ANSI C code, as well as coefficients and

data. The classical tools can also be used to produce the executable code.

In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051

code on both simulators and EVM hardware.

Algorithm and Software Development Tools for TAS3108/TAS3108IA

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5 Clock Controls

Clock management for the TAS3108/TAS3108IA consists of two control structures:

• Master clock management

–

Oversees the selection of the clock frequencies for the 8051 microprocessor, the I²C controller, and

the audio DSP core

–

The master clock (MCLKI or XTALI) is the source for these clocks.

In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the

DPLL output drives the microprocessor and audio DSP clocks.

–

Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the

microprocessor and audio DSP clocks.

•

Serial audio port (SAP) clock management

–

Oversees SAP master/slave mode

Controls output of SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode

Figure 5-2 shows the clock circuitry in the TAS3108/TAS3108IA. Input pin MCLKI or XTALI provides the

master clock for the TAS3108/TAS3108IA. Within the TAS3108/TAS3108IA, these two inputs are

combined by an OR gate and, thus, only one of these two sources can be active at any one time. The

source that is not active must be logic 0.

In normal operation, 1, 2, or 4 (as determined by the logic levels set at input pins PLL0 and PLL1) divides

the master clock. The DPLL then multiplies this signal by 11 in frequency (PLL2 = LOW). The multiplier

ratio is always 11 (pin PLL2 = LOW). The DPLL output is the processing clock used by the audio DSP

core.

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Table 5-1. PLL2, PLL1, and PLL0 Pin Configuration Controls

PLL2

PLL1

PLL0

AUDIO DSP CLOCK

11 × MCLK/1

11 × MCLK/2

11 × MCLK/4

Reserved

Audio DSP clock or audio DSP clock/4 is used to clock the on-chip microprocessor. The input pin

MICROCLK_DIV makes this clock choice. A logic-1 input level on this pin selects the audio DSP clock for

the microprocessor clock; a logic-0 input level on this pin selects the audio DSP clock/4 for the

microprocessor clock. The microprocessor clock must be ≤ 34 MHz.

Table 5-2. MICROCLK_DIV Pin Configuration Control

MICROCLK_DIV

MICROPROCESSOR CLOCK

Audio DSP clock/4

Audio DSP clock

NOTE

The state of PLL0, PLL1, PLL2, and MICROCLK_DIV can only be changed while the

TAS3108 or TAS3108IA RESET pin is held low.

The TAS3108/TAS3108IA only supports dynamic sample-rate changes between any of the supported

sample frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate

changes, the TAS3108/TAS3108IA remains in normal operation and the register contents are preserved.

To avoid producing audio artifacts during the sample-rate changes, a volume or mute control can be

included in the application firmware that mutes the output signal during the sample-rate change. The

fixed-frequency clock can be provided by a crystal, attached to XTLI and XTLO, or an external 3.3-V

fixed-frequency TTL source attached to MCLKI.

When the TAS3108/TAS3108IA is used in a system in which the master clock frequency (f_MCLK) can

change, the TAS3108/TAS3108IA must be reset during the frequency change. In these cases, the

procedure shown in Figure 5-1 should be used.

Clock Controls

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Enable Mute and

Wait for Completion

RESET Pin = Low

Change f

MCLK

Are

Clocks

Stable?

Yes

RESET Pin = High

After

TAS3108/TAS3108IA

Initializes,

Re-initialize

I C Registers

F0007-01

Figure 5-1. Master Clock Frequency (f_MCLK) Change Procedure

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SCLKIN

MCLKI

XTALI

XTALO

MCLKO

PLL2

PLL1 PLL0

SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2

÷2

MCLK

÷2

OSC

PLL

× 11

÷2

÷ Z = 2

DEFAULT

÷4

÷ X = 1

DEFAULT

÷Y = 64

DEFAULT

PLL and Clock Management

Input

SAP

Audio DSP Core

Output

SAP

Microprocessor

and

I C Bus Controller

N = 0 (Default)

Oversample Clock

1/2

I C

Master/Slave

Controller

Master

SCL

8-Bit

WARP

÷10

1/(M+1)

8051 Microprocessor

M = 8 (Default)

2xSCL

2xSDA

B0078-01

Figure 5-2. DPLL and Clock Management Block Diagram

Clock Controls

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CRYST

LKO

PLL

L1 PLL0

g two TAS

slots fo

r those

3108s. Fo

TDM tim

AB assign

uts involvin

TDM outp

MCLKI

AS3108

ne of the T

’. The

as AB = ‘0

t formats, o

e defined

these outpu

chips must b

XTALO

OSC

ed as

st be defin

108 chip mu

XTA

other TAS3

AB = ‘1’.

MUX

SCL SDA

PLL [1:0]

Code

Word Size

32-bit

÷2

÷4

IW0/OW0

IW1/OW1

IW2/OW2

AUDIO

DIGITAL

PROCESSOR

CLOCK

6-bit

x 1

20-bit

24-bit

÷2

÷4

PLL

MUX

MICROPROCESSOR

CLOCK

ord Format (DWMFT)

Data W

11 10

15 14 13

I²C SAMPLING

CLOCK N = 0

IW[2:0]

÷4

OW[2:0]

÷2N

MUX

are

ord sizes

nd output w

NOTE: Input a

independent.

I²C

MODULE

0x00

21 1918 16

27 26 24

31 29 28

1/(M+1)

÷10

Ack

Ack IOM

x[2:0]

z[2:0]

y[2:0]

Ack DWMFT

w[1:0]

IMS

Ack ICS

000

Ack

N[2:0]

M[3:0]

Ack Sub-Addr

Slave

Addr

I²C MASTER

SCL M = 8

0x01

Ack

0xxxxxxx

Ack

Ack 00000000

0 1000 010

00000000

Ack

00000000

Ack

Ack Sub-Addr

Slave

Addr

IM[3:0] OM[3:0]

÷2

÷32

÷64

÷3

Audio Port (AP) Mode Code

IM1/OM1 IM0/OM0

Serial

Mode

IM3/OM3 IM2/OM2

÷2

÷4

Discrete, left justified

÷128

÷3

Discrete, right justified

Discrete, I2S

TDM_LJ_8

÷6

÷192

÷256

÷384

÷512

÷32

÷4

÷8

TDM_LJ_6

÷6

÷16

÷32

TDM_LJ_4

TDM_I2S_8

TDM_I2S_6

TDM_I2S_4

Discrete, I2S

÷8

MUX

÷16

÷32

MUX

SCLKIN

SCLKOUT1

SCLKOUT2

Figure 5-3. Serial Data Format, Clock Management, and I²C M&N Assignments

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When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock

to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode,

LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 5-2,

SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct

clocks are required to support TDM-to-discrete and discrete-to-TDM data-format conversions. Such format

conversions also require that SCLKIN be the higher-valued bit-clock frequency. For TDM-in/discrete-out

format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/TDM-out format

conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1,

SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are

all controlled by I²C commands. Table 5-3 lists the default settings at power turnon or after a received

reset.

Table 5-3. TAS3108/TAS3108IA Clock Default Settings

CLOCK

SCLKOUT1

DEFAULT SETTING

SCLKIN

SCLKOUT2

SCLKIN

MCLKO

MCLKI or XTALI

LRCLK

Input

Audio DSP clock

Microprocessor clock

PLL multiply ratio

I²C sampling clock

I²C master SCL

Set by pins PLL0 and PLL1

Set by pin MICROCLK_DIV

N = 0

M = 8

The selections provided by the dedicated TAS3108/TAS3108IA input pins and the programmable settings

provided by I²C subaddress commands give the TAS3108/TAS3108IA a variety of clocking options.

However, the following clocking restrictions must be adhered to:

•

MCLKI or XTALI ≥128 f_S

NOTE

For some TDM modes, MCLKI or XTALI must be ≥256 f_S

•

Audio DSP clock <136 MHz

Microprocessor clock/20 ≥ I²C SCL clock

Microprocessor clock ≤34 MHz

I²C oversample clock/20 ≥ I²C SCL clock

XTALI ≤20 MHz

MCLKI ≤25 MHz

As long as these restrictions are met, all other clocking options are allowed.

See Section 7.1 for information on programming the clock register.

Clock Controls

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Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz)

Input

LRCLK f_S

Rate 32,

64, 128,

192, 256,

384, 512

PLL

Multi-

plier

11 (pin 135.2 MHz

PLL2)

f_S

MCLK/

LRCLK MCLK Freq

Ratio

(× f_S)

MCLK/

SCLK 1,

2, 3, 4, 6,

8, 16, 32

SCLK

OUT1

Rate

SCLK

OUT2

Rate

Divider

1, 2, 4

(pins

PLL0,

PLL1)

per

SDIN

SCLKIN

Rate

(× f_S)

SCLKIN

Freq

(MHz)

X Mux 1, 2,

3, 4, 6, 8,

16, 32

f_DSPCLK

(MHz) Max

Sample

Rate

(kHz)

Ch per

SDOUT

f_DSPCLK/f_S

(MHz)

(× f_S)

Slave Mode, 2 Channels In, 2 Channels Out

44.1

384

256

128

12.288

11.2896

12.288

11.2896

12.288

11.2896

12.288

2.048

2.822

3.072

5.645

6.144

11.290

12.288

N/A

135.2

124.2

135.2

124.2

135.2

124.2

135.2

4224

2816

1408

704

88.2

176.4

192

704

Slave Mode, 2 Channels In, TDM Out

44.1

256

128

11.2896

12.288

11.2896

12.288

256

128

11.290

12.288

11.290

6.144

N/A

256

128

124.2

135.2

124.2

135.2

2816

1408

88.2

Slave Mode, TDM In, 2 Channels Out

44.1

256

128

11.2896

12.288

11.2896

12.288

256

128

11.290

12.288

11.290

12.288

N/A

256

128

124.2

135.2

124.2

135.2

2816

1408

88.2

Slave Mode, TDM In, TDM Out

44.1

256

128

11.2896

12.288

11.2896

12.288

256

128

11.290

12.288

11.290

12.288

N/A

256

128

256

128

256

128

124.2

135.2

124.2

135.2

2816

1408

88.2

Master Mode, 2 Channels In, 2 Channels Out

44.1

384

256

128

12.288

11.2896

12.288

N/A

135.2

124.2

135.2

124.2

135.2

124.2

4224

2816

1408

704

88.2

11.2896

12.288

176.4

11.2896

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Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) (continued)

Input

LRCLK f_S

Rate 32,

64, 128,

192, 256,

384, 512

PLL

Multi-

plier

11 (pin 135.2 MHz

PLL2)

f_S

MCLK/

LRCLK MCLK Freq

Ratio

(× f_S)

MCLK/

SCLK 1,

2, 3, 4, 6,

8, 16, 32

SCLK

OUT1

Rate

SCLK

OUT2

Rate

Divider

1, 2, 4

(pins

PLL0,

PLL1)

per

SDIN

SCLKIN

Rate

(× f_S)

SCLKIN

Freq

(MHz)

X Mux 1, 2,

3, 4, 6, 8,

16, 32

f_DSPCLK

(MHz) Max

Sample

Rate

(kHz)

Ch per

SDOUT

f_DSPCLK/f_S

(MHz)

(× f_S)

192

12.288

N/A

135.2

704

Master Mode, 2 Channels In, TDM Out

44.1

256

128

384

256

384

11.2896

12.288

11.2896

12.288

11.2896

12.288

N/A

256

128

192

128

384

124.2

135.2

124.2

135.2

124.2

135.2

2816

1408

4224

2816

4224

88.2

44.1

Master Mode, TDM In, 2 Channels Out

44.1

256

128

384

256

384

11.2896

12.288

11.2896

12.288

11.2896

12.288

N/A

256

128

192

128

384

124.2

135.2

124.2

135.2

124.2

135.2

2816

1408

4224

2816

4224

88.2

44.1

Master Mode, TDM In, TDM Out

44.1

256

128

384

256

384

11.2896

12.288

11.2896

12.288

11.2896

12.288

N/A

256

128

192

128

384

256

128

192

128

384

256

128

192

128

384

124.2

135.2

124.2

135.2

124.2

135.2

2816

1408

4224

2816

4224

88.2

44.1

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6 Microprocessor Controller

The 8051 microprocessor receives and distributes I²C write data, retrieves and outputs to the I²C bus

controllers the required I²C read data, and participates in most processing tasks requiring multiframe

processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing

I²C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program

cannot be altered. The microprocessor controller has specialized hardware for master and slave interface

operation, volume updates, and a programmable interval timer interrupt. For more information, see the

TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

The TAS3108/TAS3108IA has a slave-only I²C interface that is compatible with the inter-IC (I²C) bus

protocol and supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read

operations (maximum is 20 bytes). The slave I²C control interface is used to program the registers of the

device and to read device status.

The TAS3108/TAS3108IA also has a master-only I²C interface that is compatible with the I²C bus protocol

and supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20

bytes). The master I²C interface is used to load program and data from an external I²C EEPROM.

On power up of the TAS3108/TAS3108IA, the slave interface is disabled and the master interface is

enabled. Following a reset, the TAS3108/TAS3108IA disables the slave interface and enables the master

interface. Using the master interface, the TAS3108/TAS3108IA automatically tests to see if an I²C

EEPROM is at address 1010xxx. The value xxx can be chip select, other information, or don’t cares,

depending on the EEPROM selected. If a memory is present and it contains the correct header

information and one or more blocks of program/memory data, the TAS3108/TAS3108IA loads the

program, coefficient, and/or data memories from the EEPROM. If a memory is present, the download is

complete when

a header is read that has a zero-length data segment. At this point, the

TAS3108/TAS3108IA disables the master I²C interface, enables the slave I²C interface, and starts normal

operation.

If no memory is present or if an error occurred during the EEPROM read, TAS3108/TAS3108IA disables

the master I²C interface, enables the slave I²C interface, and loads the unprogrammed default

configuration. In this default configuration, the TAS3108/TAS3108IA streams eight channels of audio from

input to output if the GPIO pin is LOW. The master and slave interfaces do not operate simultaneously.

In the slave mode, the I²C bus is used to:

•

Load the program and coefficient data

–

Microprocessor program memory

Microprocessor extended memory

Audio DSP core program memory

Audio DSP core coefficient memory

Audio DSP core data memory

•

Update coefficient and other control values

Read status flags

Once the microprocessor program memory has been loaded, it cannot be updated until the

TAS3108/TAS3108IA has been reset.

The master and slave modes do not operate simultaneously.

When acting as an I²C master, the data transfer rate is fixed at 375 kHz, assuming MCLKI or

XTALI = 12.288 MHz, PLL0 = PLL1 = 0, and MICROCLK_DIV = 0.

When acting as an I²C slave, the data transfer rate is determined by the master device on the bus. The

I²C communication protocol for the I²C slave mode is shown in Figure 6-1.

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Start

(By Master)

Read or Write

(By Master)

Stop

(By Master)

Slave Address

(By Master)

Data Byte

(By Transmitter)

Data Byte

(By Transmitter)

(1)

Acknowledge

(By TAS3108/TAS3108IA)

Acknowledge

(By Receiver)

Acknowledge

(By Receiver)

MSB MSB−1 MSB−2

LSB

SDA

SCL

Start Condition

SDA ↓ While SCL = 1

Stop Condition

SDA ↑ While SCL = 1

T0087−01

Figure 6-1. I²C Slave-Mode Communication Protocol

6.1 General I²C Operations

As shown in Figure 6-2, an I²C read transaction requires that the master device first issue a write

transaction to give the TAS3108/TAS3108IA the subaddress to be used in the read transaction that

follows. This subaddress assignment write transaction is then followed by the read transaction. For write

transactions, the subaddress is supplied in the first byte of data written, and this byte is followed by the

data to be written. For I²C write transactions, the subaddress must always be included in the data written.

There cannot be a separate write transaction to supply the subaddress, as was required for read

transactions. If a subaddress assignment-only write transaction is followed by a second write transaction

supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted

by the TAS3108/TAS3108IA as another subaddress replacing the one previously written.

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I²C Read Transaction

TAS3108/

TAS3108IA

Subaddress

(By Master)

Data

(By TAS3108/

TAS3108IA)

Data

(By TAS3108/

TAS3108IA)

Start

(By Master)

Write

(By Master)

Stop

Start

Read

(By Master)

Stop

(By Master)

(By Master) (By Master)

TAS3108/

ACK Subaddress ACK

ACK

Data

ACK

Data

ACK

NAK

TAS3108IA

Address

TAS3108IA

Address

7-Bit Slave

Address

(By Master)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By TAS3108/

TAS3108IA)

7-Bit Slave

Address

(By Master)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By Master)

Acknowledge

(By Master)

No Acknowledge

(By Master)

I²C Write Transaction

TAS3108/

TAS3108IA

Subaddress

(By Master)

Start

(By Master)

Write

(By Master)

Stop

(By Master)

Data

(By Master)

Data

(By Master)

TAS3108/

ACK Subaddress ACK

Data

ACK

Data

ACK

TAS3108IA

Address

7-Bit Slave

Address

(By Master)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By TAS3108/

TAS3108IA)

Acknowledge

(By TAS3108/

TAS3108IA)

R0006−01

Figure 6-2. I²C Subaddress Access Protocol

6.2 Detailed I²C Operation

The I²C slave mode is the mode that is used to change configuration parameters during operation and to

perform program and coefficient downloads from a master device. The latter can be used to replace the

I²C master-mode EEPROM download. The TAS3108/TAS3108IA supports both random and sequential

I²C transactions. The TAS3108/TAS3108IA I²C slave address is 011010xy, where the first six bits are the

TAS3108/TAS3108IA device address and bit x is CS0, which is set by the TAS3108/TAS3108IA internal

microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00

address when no connection is made to the pin. Table 6-1 and Table 6-2 show all the legal addresses for

I²C slave and master modes.

The TAS3108/TAS3108IA I²C block does respond to the broadcast address (00h).

Table 6-1. Slave Addresses

BASE ADDRESS

0110 10

CS0

R/W

SLAVE ADDRESS

0x68

0x69

0x6A

0x6B

0110 10

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Table 6-2. Master Addresses

BASE ADDRESS

1010 00

CS0

R/W

MASTER ADDRESS

0xA0

0xA1

0xA2

0xA3

1010 00

The following is an example use of the I²C master address to access an external EEPROM. The

TAS3108/TAS3108IA can address up to two EEPROMs depending on the state of CS0. Initially, the

TAS3108/TAS3108IA comes up in I²C master mode. If it finds a memory such as the 24C512 EEPROM, it

reads the headers and data as previously described. In this I²C master mode, the TAS3108/TAS3108IA

addresses the EEPROMs as shown in Table 6-3 and Table 6-4.

Table 6-3. EEPROM Address I²C TAS3108/TAS3108IA Master Mode = 0xA1/A0

(EEPROM)

MSB

CS0

R/W

1/0

Table 6-4. EEPROM Address I²C TAS3108/TAS3108IA Master Mode = 0xA3/A2

(EEPROM)

MSB

CS0

R/W

1/0

Random I²C Transactions

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. For

random I²C read commands, the TAS3108/TAS3108IA responds with data, a byte at a time, starting at the

subaddress assigned, as long as the master device continues to respond with acknowledges. If a given

subaddress does not use all 32 bits, the unused bits are read as logic 0. I²C write commands, however,

are treated in accordance with the data assignment for that address space. If a write command is received

for a biquad subaddress, for example, the TAS3108/TAS3108IA expects to see five 32-bit words. If fewer

than five data words have been received when a stop command (or another start command) is received,

the data received is discarded.

Sequential I²C Transactions

The TAS3108/TAS3108IA also supports sequential I²C addressing. For write transactions, if a subaddress

is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write

transaction has taken place, and the data for all 16 subaddresses is successfully received by the

TAS3108/TAS3108IA. For I²C sequential write transactions, the subaddress then serves as the start

address, and the amount of data subsequently transmitted before a stop or start is transmitted determines

how many subaddresses are written to. As was true for random addressing, sequential addressing

requires that a complete set of data be transmitted. If only a partial set of data is written to the last

subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just

the incomplete data is discarded.

Sequential read transactions do not have restrictions on outputting only complete subaddress data sets.

If the master does not issue enough data-received acknowledges to receive all the data for a given

subaddress, the master device does not receive all the data.

If the master device issues more data-received acknowledges than required to receive the data for a given

subaddress, the master device simply receives complete or partial sets of data, depending on how many

data-received acknowledges are issued from the subaddress(es) that follow. I²C read transactions, both

sequential and random, can impose wait states.

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For the standard I²C mode (SCL = 100 kHz), worst-case wait state time for an 8-MHz microprocessor

clock is on the order of 2 µs. Nominal wait-state time for the same 8-MHz microprocessor clock is on the

order of 1 µs. For the fast I²C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock,

worst-case wait-state time can extend up to 10.5 µs in duration. Nominal wait-state time for this same

case lies in a range from 2 µs to 4.6 µs. Increasing the microprocessor clock frequency lowers the

wait-state time and for the standard I²C mode, a faster microprocessor clock can totally eliminate the

presence of wait states.

For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I²C

mode, faster microprocessor clocks shorten the wait-state time encountered, but do not totally eliminate

wait states.

6.2.1 Multiple-Byte Write

Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-3. After receiving

each data byte, the TAS3108/TAS3108IA responds with an acknowledge bit.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

Figure 6-3. Multiple-Byte Write Transfer

6.2.2 Multiple-Byte Read

Multiple data bytes are transmitted by the TAS3108/TAS3108IA to the master device as shown in

Figure 6-4. Except for the last data byte, the master device responds with an acknowledge bit after

receiving each data byte.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A0 ACK

Acknowledge

D0 ACK D7

A0 R/W ACK A7 A6 A5

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

Figure 6-4. Multiple-Byte Read Transfer

6.3 I²C Master-Mode Device Initialization

I²C master-mode operation is enabled following a reset or power-on reset. Master-mode I²C transactions

do not start until the I²C bus is idle.

The TAS3108/TAS3108IA uses the master mode to download from EEPROM the memory contents for the

microprocessor program memory, microprocessor extended memory, audio DSP core program memory,

audio DSP core coefficient memory, and audio DSP core data memory.

The TAS3108/TAS3108IA, when operating as an I²C master, can execute a complete download of any

internal memory or any section of any internal memory without requiring any wait states.

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When the TAS3108/TAS3108IA operates as an I²C master, the TAS3108/TAS3108IA generates a

repeated start without an intervening stop command while downloading program and memory data from

EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential

read mode to transfer large blocks of data quickly.

The TAS3108/TAS3108IA queries the bus for an I²C EEPROM at address 1010xxx. The value xxx can be

chip select, other information, or don’t cares, depending on the EEPROM selected.

The first action of the TAS3108/TAS3108IA as master is to transmit a start condition along with the device

address of the I²C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM

acknowledges the address byte, and the TAS3108/TAS3108IA sends a subaddress byte, which the

EEPROM acknowledges. Most EEPROMs have at least 2-byte addresses and acknowledge as many as

are appropriate. At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter.

The TAS3108/TAS3108IA acknowledges each byte repeatedly to continue reading each data byte that is

stored in memory.

The memory load information starts with reading the header and data information that starts at

subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with

no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header

locations.

The TAS3108/TAS3108IA memory data can be stored and loaded in (almost) any order. Additionally, this

addressing scheme permits portions of the TAS3108/TAS3108IA internal memories to be loaded.

I²C EEPROM Memory Map

Block Header 1

Data Block 1

Block Header 2

Data Block 2

Block Header N

Data Block N

M0040−01

Figure 6-5. EEPROM Address Map

The TAS3108/TAS3108IA sequentially reads EEPROM memory and loads its internal memory unless it

does not find a valid memory header block, is not able to read the next memory location because the end

of memory was reached, detects a checksum error, or reads an end-of-program header block. When it

encounters an invalid header or read error, the TAS3108/TAS3108IA attempts to read the header or

memory location three times before it determines that it has an error. If the TAS3108/TAS3108IA

encounters a checksum error it attempts to reread the entire block of memory two more times before it

determines that it has an error.

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Once the microprocessor program memory has been loaded, it cannot be reloaded until the

TAS3108/TAS3108IA has been reset.

If an error is encountered, TAS3108/TAS3108IA terminates its memory-load operation, loads the default

configuration, and disables further master I²C bus operations.

If an end-of-program data block is read, the TAS3108/TAS3108IA has completed the initial program load.

The I²C master mode uses the starting and ending I²C checksums to verify a proper EEPROM download.

The first 16-bit data word received from the EEPROM, the I²C checksum at subaddress 0x00, is stored

and compared against the 16-bit data word received for the last subaddress, the ending I²C checksum,

and the checksum that is computed during the download. These three values must be equal. If the read

and computed values do not match, the TAS3108/TAS3108IA sets the memory read error bits in the

status register and repeats the download from the EEPROM two more times. If the comparison check fails

the third time, the TAS3108/TAS3108IA sets the microprocessor program to the default value.

Table 6-5 shows the format of the EEPROM or other external memory load file. Each line of the file is a

byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending

checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four

bytes of the checksum.

Example:

Given the following example 8051 data or program block (must be a multiple of 4 bytes for these blocks):

10h

20h

30h

40h

50h

60h

70h

80h

The checksum = 10h + 20h + 30h + 30h + 40h + 50h + 60h + 70h + 80h = 240h, so

the values put in the checksum fields are MS byte = 02h and LS byte = 40h.

If the checksum is > FFFFh, the 2-byte checksum field is the least-significant two bytes.

For example, if the checksum is 1D 45B6h, the checksum field is MS byte = 45h and LS byte = B6h.

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Table 6-5. TAS3108/TAS3108IA Memory Block Structures

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

12-Byte Header Block

Checksum code MS byte

Checksum code LS byte

Header ID byte 1 = 0x00

Header ID byte 2 = 0x1F

Memory to be loaded

2 bytes

Checksum of bytes 2 through N + 12

2 bytes

1 byte

Must be 0x001F for the TAS3108/TAS3108IA to load

0x00 Microprocessor program memory or termination

header

0x01 Microprocessor external data memory

0x02 Audio DSP core program memory

0x03 Audio DSP core coefficient memory

0x04 Audio DSP core data memory

0x05–0x0F Reserved for future expansion

0x00

1 byte

Unused

Start TAS3108/TAS3108IA memory address MS

byte

2 bytes

If this is a termination header, this value is 0000.

Start TAS3108/TAS3108IA memory address LS byte

Total number of bytes transferred MS byte

2 bytes

12 + data bytes + last checksum bytes. If this is a

termination header, this value is 0000.

Total number of bytes transferred LS byte

0x00

1 bytes

Unused

Data Block for Microprocessor Program or Data Memory (Following 12-Byte Header)

Data byte 1 (LS byte)

Data byte 2

4 bytes

1–4 microprocessor bytes

Data byte 3

Data byte 4 (MS byte)

Data byte 5

4 bytes

5–8 microprocessor bytes

Data byte 6

Data byte 7

Data byte 8

•

N + 8

Data byte 4*(Z – 1) + 1

Data byte 4*(Z – 1) + 2

Data byte 4*(Z – 1) + 3

Data byte 4*(Z – 1) + 4 = N

0x00

4 bytes

N + 12

Repeated checksum bytes 2 through N + 11

0x00

Checksum code MS byte

Checksum code LS byte

Data Block for Audio DSP Core Coefficient Memory (Following 12-Byte Header)

Data byte 1 (LS byte)

Data byte 2

4 bytes

Coefficient word 1 (valid data in D27–D0) D7–D0

D15–D8

Data byte 3

D23–D16

D31–D24

Data byte 4 (MS byte)

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Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued)

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

Data byte 5

4 bytes

Coefficient word 2

Data byte 6

Data byte 7

Data byte 8

•

N + 8

Data byte 4*(Z – 1) + 1

Data byte 4*(Z – 1) + 2

Data byte 4*(Z – 1) + 3

Data byte 4*(Z – 1) + 4 = N

0x00

4 bytes

Coefficient word Z

N + 12

Repeated checksum bytes 2 through N + 11

0x00

Checksum code MS byte

Checksum code LS byte

Data Block for Audio DSP Core Data Memory (Following 12-Byte Header)

Data byte 1 (LS byte)

Data byte 2

6 bytes

Data word 1 D7–D0

D15–D8

Data byte 3

D23–D16

Data byte 4

D31–D24

Data byte 5

D39–D32

Data byte 6 (MS byte)

Data byte 7

D47–D40

6 bytes

Data 2

Data byte 8

Data byte 9

Data byte 10

Data byte 11

Data byte 12

•

N + 6

Data byte 6*(Z – 1) + 1

Data byte 6*(Z – 1) + 2

Data byte 6*(Z – 1) + 3

Data byte 6*(Z – 1) + 4

Data byte 6*(Z – 1) + 5

Data byte 6*(Z – 1) + 6 = N

0x00

6 bytes

Data Z

N + 12

6 bytes

Repeated checksum bytes 2 through N + 11

0x00

Checksum code MS byte

Checksum code LS byte

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Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued)

STARTING

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

Data Block for Audio DSP Core Program Memory (Following 12-Byte Header)

7 bytes Program word 1 (valid data in D53–D0) D7–D0

Program byte 1 (LS byte)

Program byte 2

Program byte 3

Program byte 4

Program byte 5

Program byte 6

Program byte 7 (MS byte)

Program byte 8

Program byte 9

Program byte 10

Program byte 11

Program byte 12

Program byte 14

Program byte 15

•

D15–D8

D23–D16

D31–D24

D39–D32

D47–D40

D55–D48

Program word 2

7 bytes

•

N + 5

Program byte 7*(Z – 1) + 1

Program byte 7*(Z – 1) + 2

Program byte 7*(Z – 1) + 3

Program byte 7*(Z – 1) + 4

Program byte 7*(Z – 1) + 5

Program byte 7*(Z – 1) + 6

Program byte 7*(Z – 1) + 7 = N

0x00

7 bytes

Program word Z

N + 12

7 bytes

Repeated checksum bytes 2 through N + 11

0x00

Checksum code MS byte

Checksum code LS byte

20-Byte Termination Block (Last Block of Entire Load Block)

B_LAST– 19

B_LAST– 17

0x00

0x1F

0x00

•

2 bytes

First two bytes of termination block are always 0x0000.

2 bytes

Second two bytes are always 0x001F.

B_LAST– 15

B_LAST– 14

1 byte

Last 16 bytes must each be 0x00.

B_LAST

0x00

1 byte

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7 I²C Register Map

NO. OF

BYTES

INITIALIZATION

SUBADDRESS

CONTENTS

VALUE

0x00

0x01

0x02

0x03

0x04

0x05

0x06

Clock and SAP control register

Reserved

Description shown in Section 7.1

0x01, 0x00, 0x1B, 0x22

0x00, 0x00, 0x00, 0x40

0x00, 0x00, 0x00, 0x00

Reserved

Status register

Description shown in Section 7.2

Unused

I²C memory load control register

I²C memory load data register

PEEK/POKE address

Description shown in Section 7.3

u(31:24)⁽¹⁾, MemSelect(23:16),

Addr(15:8), Addr(7:0)

0x00, 0x00, 0x00, 0x00

0x07

PEEK/POKE data

D(63:56), D(55:48), D(47:40), D(39:32), 0x00, 0x00, 0x00, 0x00

D(31:24), D(23:16), D(15:8), D(7:0)

0x08

0x09

Version number

User-defined

TAS3108/TAS3108IA version

User-defined register 1

0x00, 0x00, 0x00, 0x01

User-defined

4, 8, 12, 16, or

0x0A

User-defined

4, 8, 12, 16, or

User-defined register 2

User-defined

•

0xFE

User-defined

4, 8, 12, 16, or

User-defined register 246

User-defined

0xFF

4, 8, 12, 16, or

User-defined register 247

(1) u indicates unused bits.

In the following sections, BOLD indicates the default state of the bit fields.

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7.1 Clock Control Register (0x00)

size, and serial audio port modes. Register 0x00 default = 0x0100 1B22.

Table 7-1. Clock Control Register (0x00)

D31

D30

D29

D28

D27

D26

D25

D24

DESCRIPTION

Not Used

Master clock output divider

Master mode LRCLK divider

DESCRIPTION

D23

D22

D21

D20

D19

D18

D17

D16

ICS

SCLKOUT select (default = 0)

IMS

SAP master/slave mux select (1 = master mode, 0 = slave mode)

SCLKIN and SCLKOUT clock divide

MCLK, SCLK ratio (master mode only)

D15

D14

D13

D12

D11

D10

DESCRIPTION

Don't care

IW1

IW0

Input audio data word size

Don't care

OW1

OW0 Output audio data word size

D0 DESCRIPTION

IM3

IM2

IM1

IM0

Input data format

OM0 Output data format

OM3

OM2

OM1

7.1.1 Master Clock Output Divider

Bits 28–27 (W1 and W0) define the ratio between MCLKI (or the crystal frequency) and MCLKO. This

allows the accommodation of devices that require an MCLK = 128 LRCLK and devices that require an

MCLK = 256 LRCLK, without having to use glue logic to divide that clock down. This bit has meaning

whether in clock-master or clock-slave mode.

DESCRIPTION

MCLKO = MCLKI

MCLKO = MCLKI/2

MCLKO = MCLKI/4

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7.1.2 Master Mode LRCLK Divider

Bits 26–24 (Y2, Y1, and Y0) define the ratio between SCLK and LRCLK, but only have meaning in the

clock-master mode where LRCLK is an output. In the clock-slave mode, LRCLK is an input.

DESCRIPTION

LRCLK out = SCLK/32

LRCLK out = SCLK/64

LRCLK out = SCLK/128

LRCLK out = SCLK/192

LRCLK out = SCLK/256

LRCLK out = SCLK/384

LRCLK out = SCLK/512

LRCLK out = SCLK/32

7.1.3 SCLKIN and SCLKOUT Clock Divide

Bits 21–19 (X2, X1, and X0) define the ratio between SCLKIN and SCLKOUT. These control bits are only

used when the input and output rates are different, which can happen if TDM and discrete modes are both

used (for example, input is TDM and output is discrete). Normally, these bits are set to 000, so that

SCLKOUT1 (input SCLK) and SLCKOUT2 (output SCLK) are the same. (Note that SCLKIN is not the

input SCLK, but is used in clock-slave mode to derive SCLKOUT1.)

DESCRIPTION

X MUX out = IMS_MUX (master/slave SCLK)

X MUX out = IMS_MUX/2

X MUX out = IMS_MUX/3

X MUX out = IMS_MUX/4

X MUX out = IMS_MUX/6

X MUX out = IMS_MUX/8

X MUX out = IMS_MUX/16

X MUX out = IMS_MUX/32

7.1.4 MCLK, SCLK Ratio (Master Mode Only)

Bits 18–16 (Z2, Z1, and Z0) define the ratio between MCLK and SCLK when the TAS3108/TAS3108IA is

the clock master. In clock-slave mode, these bits are don't care.

DESCRIPTION

Z MUX out = MCLK (MCLKI or crystal oscillator)

Z MUX out = MCLK/2

Z MUX out = MCLK/3

Z MUX out = MCLK/4

Z MUX out = MCLK/6

Z MUX out = MCLK/8

Z MUX out = MCLK/16

Z MUX out = MCLK/32

I²C Register Map

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7.1.5 Audio Data Word Size

Bits 12–11 (IW1 and IW0) define the data word size for the input SAP. Bits 9–8 (OW1 and OW0) define

the data word size for the output SAP.

IW1/OW1

IW0/OW0

DESCRIPTION

32-bit audio data

16-bit audio data

20-bit audio data

24-bit audio data

7.1.6 Input and Output Data Format

Bits 7–4 (IM3, IM2, IM1, and IM0) define the input data format. Bits 3–0 (OM3, OM2, OM1, and OM0)

define the output data format. The two formats need not be the same, only compatible.

IM3/OM3

IM2/OM2

IM1/OM1

IM0/OM0

DESCRIPTION

2 channel, left justified

2 channel, right justified

2 channel, I²S

TDM, left justified (8 channels)

TDM, left justified (6 channels)

TDM, left justified (4 channels)

TDM, I²S (8 channels)

TDM, I²S (6 channels)

TDM, I²S (4 channels)

2 channel, I²S

I²C Register Map

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7.2 Status Register (0x02)

During I²C download, the write operation to indicate that a particular memory is to be written causes the

TAS3108/TAS3108IA to set an error bit to indicate a load for that memory type. This error bit is cleared

when the operation completes successfully.

Table 7-2. Status Register (0x02)

D31

D30

D29

D28

D27

D26

D25

D24

DESCRIPTION

–

Firmware definable

D23

D22

D21

D20

D19

D18

D17

D16

–

D15

D14

D13

D12

D11

D10

–

Microprocessor program memory load error

Microprocessor external data memory load error

Audio DSP core program memory load error

Audio DSP core coefficient memory load error

Audio DSP core data memory load error

Invalid memory select

–

End-of-load header error

No EPROM present

No errors

I²C Register Map

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7.3 I²C Memory Load Control and Data Registers (0x04 and 0x05)

Registers 0x04 (Table 7-3) and 0x05 (Table 7-4) allow the user to download TAS3108/TAS3108IA

program code and data directly from the system I²C controller. This mode is called the I²C slave mode

(from the TAS3108/TAS3108IA point-of-view). See the TAS3108/TAS3108IA Firmware Programmer's

Guide (SLEU067) for more details.

Table 7-3. TAS3108/TAS3108IA Memory Load Control Register (0x04)

BYTE

DATA BLOCK FORMAT

SIZE

NOTES

1–2

Checksum code

2 bytes Checksum of bytes 2 through N + 8. If this is a termination header,

this value is 0000.

3–4

Memory to be loaded

2 bytes 0 Microprocessor program memory

1 Microprocessor external data memory

2 Audio DSP core program memory

3 Audio DSP core coefficient memory

4 Audio DSP core data memory

5–15 Reserved for future expansion

Unused

1 byte

Reserved for future expansion

6–7

Starting TAS3108/TAS3108IA memory

address

2 bytes If this is a termination header – this value is 0000.

7–8

Number of data bytes to be transferred

2 bytes If this is a termination header – this value is 0000.

Table 7-4. TAS3108/TAS3108IA Memory Load Data Register (0x05)

BYTE

8-BIT DATA

28-BIT DATA

0000 D27–D24

D7–D0

48-BIT DATA

0000 0000

D47–D40

D39–D32

D31–D24

D23–D16

D15–D8

54-BIT DATA

0000 0000

00 D53–D48

D47–D40

D39–D32

D31–D24

D23–D16

D15–D8

Datum 1 D7–D0

Datum 2 D7–D0

Datum 3 D7–D0

Datum 4 D7–D0

Datum 5 D7–D0

Datum 6 D7–D0

Datum 7 D7–D0

Datum 8 D7–D0

D15–D8

D7–D0

0000 D27–D24

D23–D16

D15–D8

D7–D0

I²C Register Map

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7.4 Memory Access Registers (0x06 and 0x07)

Registers 0x06 (Table 7-5) and 0x07 (Table 7-6) allow the user to access the internal resources of the

TAS3108/TAS3108IA. See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more

details.

Table 7-5. Memory Select and Address Register (0x06)

D31

D30

D29

D28

D27

D26

D25

D24

DESCRIPTION

–

Unused

D23

D22

D21

D20

D19

D18

D17

D16

DESCRIPTION

Audio DSP core coefficient memory select

Audio DSP core data memory select

Reserved

Microprocessor internal data memory select

Microprocessor external data memory select

SFR select

Microprocessor program RAM select

Audio DSP core program RAM select

D15

D14

D13

D12

D11

D10

DESCRIPTION

Memory address

DESCRIPTION

A10

A11

A12

A13

A14

A15 Memory address

Table 7-6. Data Register (Peek and Poke) (0x07)

D63

D62

D61

D60

D59

D58

D57

D56

DESCRIPTION

D63

D62

D61

D60

D59

D58

D57

D56 Data to be written or read

D55

D54

D53

D52

D51

D50

D49

D48

D55

D54

D53

D52

D51

D50

D49

D48 Data to be written or read

D47

D46

D45

D44

D43

D42

D41

D40

D47

D46

D45

D44

D43

D42

D41

D40 Data to be written or read

D39

D38

D37

D36

D35

D34

D33

D32

D39

D38

D37

D36

D35

D34

D33

D32 Data to be written or read

D31

D30

D29

D28

D27

D26

D25

D24

D31

D30

D29

D28

D27

D25

D26

D25 Data to be written or read

D23

D22

D21

D20

D19

D18

D17

D16

D23

D22

D21

D20

D19

D18

D17

D16 Data to be written or read

D15

D14

D13

D12

D11

D10

D15

D14

D13

D12

D11

D10

Data to be written or read

I²C Register Map

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8 Electrical Specifications

8.1 Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted)⁽¹⁾

Supply voltage range, DVDD

Supply voltage, AVDD

–0.5 V to 3.8 V

–0.5 V to DVDD + 0.5 V

–0.5 V to 2.3 V

–0.5 V to DVDD + 0.5 V

–0.5 V to 2.3V⁽²⁾

±20 µA

3.3-V TTL

Input voltage

range

V_I

1.8 V LVCMOS (XTLI)

3.3 V TTL

Output voltage

range

V_O

1.8 V LVCMOS (XTLO)

I_IK

Input clamp current (V_I< 0 or V_I> DVDD

Output clamp current (V_O< 0 or V_O> DVDD)

TAS3108 operating free-air temperature

TAS3108IA operating free-air temperature

Storage temperature range

I_OK

±20 µA

0°C to 70°C

T_A

–40°C to 105°C

–65°C to 150°C

T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Pin XTALO is the only TAS3108/TAS3108IA output that is derived from the internal 1.8-V logic supply. The absolute maximum rating

listed is for reference; only a crystal should be connected to XTALO.

8.2 Package Dissipation Ratings (TAS3108/TAS3108IA)

PACKAGE

PIN COUNT

TAS3108IA⁽¹⁾

TAS3108⁽²⁾

TYPE

DESIGNATOR

θ_JA(°C/W)

27.41

θ_JC(°C/W)

θ_JA(°C/W)

52.93

θ_JC(°C/W)

TSSOP

DCP

0.72

(1) Use 2 oz. trace and thermal pad with solder

(2) Use 2 oz. trace and thermal pad without solder

See Application Information, Section 9, for PCB recommendations for TAS3108IA applications.

8.3 Recommended Operating Conditions (TAS3108/TAS3108IA)

MIN NOM

MAX UNIT

Digital supply voltage, DVDD

High-level input voltage

3.3

3.6

3.3 V TTL

V_IH

V_IL

T_A

T_J

1.8 V LVCMOS (XTL_IN)

3.3 V TTL

1.2

0.8

0.5

Low-level input voltage

1.8 V LVCMOS (XTL_IN)

TAS3108

–40

Operating ambient air temperature

Operating junction temperature

°C

TAS3108IA

105

125

TAS3108

TAS3108IA

–40

Electrical Specifications

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8.4 Electrical Characteristics (TAS3108/TAS3108IA)

over recommended operating conditions (unless otherwise noted)

PARAMETER

3.3-V TTL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OH= –4 mA

I_OH= –0.55 mA

I_OL= 4 mA

2.4

V_OH

High-level output voltage

1.8-V LVCMOS

(XTL_OUT)

1.44

3.3-V TTL

0.5

0.4

V_OL

Low-level output voltage

1.8-V LVCMOS

(XTL_OUT)

I_OL= 0.75 mA

High-impedance output

current

I_OZ

I_IL

3.3-V TTL

V_I= V_IL

±20

µA

±1

Low-level input current

High-level input current

1.8-V LVCMOS (XTL_IN) V_I= V_IL

3.3-V TTL V_I= V_IH

1.8-V LVCMOS (XTL_IN) V_I= V_IH

MCLKI = 24.576 MHz,

I_IH

µA

110

100

LRCLK = 192 kHz

MCLKI = 12.288 MHz,

LRCLK = 48 kHz

Normal operation

I_DVDD

Digital supply current

MCLKI = 8.192 MHz,

LRCLK = 32 kHz

Power down enabled

Normal operation

LRCLK, SCLK, MCLKI running

MCLKI = 24.576 MHz,

LRCLK = 192 kHz

I_{A_DVDD}Analog supply current

Power down enabled

LRCLK, SCLK, MCLKI running

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8.5 Timing Characteristics

The following sections describe the timing characteristics of the TAS3108/TAS3108IA.

8.5.1 Master Clock Signals (TAS3108/TAS3108IA)

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX UNIT

CONDITIONS

(1)

f_(XTALI)

t_c(1)

f_(MCLKI)

t_w(MCLKI)

Frequency, XTALI (1/ t_c(1)

)

See

6⁽²⁾

50⁽²⁾

6⁽²⁾

20⁽²⁾MHz

Cycle time, XTALI

166⁽²⁾

25 MHz

Frequency, MCLKI (1/ t_c(2)

)

(3)

Pulse duration, MCLKI high

MCLKI jitter

See

0.4 t_c(2)

0.5 t_c(2)

0.6 t_c(2)

±5⁽²⁾

f_(MCLKO)

t_r(MCLKO)

t_f(MCLKO)

t_w(MCLKO)

Frequency, MCLKO (1/ t_c(3)

)

6⁽²⁾

25⁽²⁾MHz

Rise time, MCLKO

C_L= 30 pF

15⁽²⁾

Fall time, MCLKO

(4)

Pulse duration, MCLKO high

See

H_MCLKO

XTALI master clock source

MCLKI master clock source See

MCLKO jitter

(5)

(6)

Delay time, MCLKI rising MCLKO = MCLKI

edge to MCLKO rising

See

20⁽²⁾

t_d(MI-MO)

(6) (7)

MCLKO < MCLKI

edge

(1) Duty cycle is 50/50.

(2) This measurement is specified by design.

(3) Period of MCLKI = T_MCLKI= 1 / f_MCLKI

(4) H_MCLKO= 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLKI when MCLKO = MCLKI. When MCLKO = 0.5 MCLKI or 0.25

MCLKI, the duty cycle of MCLKO is typically 50%.

(5) When MCLKO is derived from MCLKI, MCLKO jitter = MCLKI jitter

(6) Only applies when MCLKI is selected as master source clock

(7) Also applies to MCLKO falling edge when MCLKO = MCLKI/2 or MCLKI/4.

XTALI

c(1)

w(MCLKI)

MCLKI

c(2)

d(MI-MO)

w(MCLKO)

r(MCLKO)

f(MCLKO)

MCLKO

c(3)

T0088-01

Figure 8-1. Master Clock Signal Timing Waveforms

Electrical Specifications

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8.5.2 Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST

MIN

TYP

MAX UNIT

CONDITIONS

f_LRCLK

Frequency, LRCLK (f_S)

32⁽¹⁾

192⁽¹⁾kHz

(2)

(1)

t_w(SCLKIN)Pulse duration, SCLKIN high

See

0.4 t_c(SCLKIN)

0.5 t_c(SCLKIN)0.6 t_c(SCLKIN)

(3)

(1)

f_SCLKIN

t_pd1

t_su1

t_h1

Frequency, SCLKIN

See

64 f_S

25⁽¹⁾MHz

Propagation delay, SCLKIN falling edge to SDOUT

Setup time, LRCLK to SCLKIN rising edge

Hold time, LRCLK from SCLKIN rising edge

Setup time, SDIN to SCLKIN rising edge

Hold time, SDIN from SCLKIN rising edge

15⁽¹⁾

10⁽¹⁾

(1)

0.5 t_c(SCLKIN)

t_su2

t_h2

10⁽¹⁾

Propagation delay, SCLKIN falling edge to

SCLKOUT2 falling edge

t_pd2

17⁽¹⁾

(1) This measurement is specified by design.

(2) Period of SCLKIN = T_SCLKIN= 1/f_SCLKIN

(3) Duty cycle is 50/50.

c(SCLKIN)

w(SCLKIN)

SCLKIN

su1

LRCLK

(Input)

pd1

SDOUT1

SDOUT2

SDOUT3

SDOUT4

su2

SDIN1

SDIN2

SDIN3

SDIN4

pd2

SCLKOUT2

T0090-01

Figure 8-2. Serial Audio Port Slave Mode Timing Waveforms

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8.5.3 Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA)

over recommended operating conditions (unless otherwise noted)

PARAMETER

Frequency LRCLK

TEST CONDITIONS

C_L= 30 pF

MIN

32⁽¹⁾

TYP

MAX UNIT

f_(LRCLK)

192⁽¹⁾

12⁽¹⁾

25⁽¹⁾

kHz

(2)

t_r(LRCLK)

t_f(LRCLK)

f_(SCLKOUT)

Rise time, LRCLK

Fall time, LRCLK

C_L= 30 pF

(2)

Duty cycle is 50/50.

C_L= 30 pF

Frequency, SCLKOUT1/SCLKOUT2

MHz

(1)

f_S

t_r(SCLKOUT)

t_f(SCLKOUT)

Rise time, SCLKOUT1/SCLKOUT2

Fall time, SCLKOUT1/SCLKOUT2

C_L= 30 pF

20⁽¹⁾

4⁽¹⁾

t_{pd1(SCLKOUT1)}Propagation delay, SCLKOUT1 falling edge to LRCLK edge

t_{pd1(SCLKOUT2)}Propagation delay, SCLKOUT2 falling edge to LRCLK edge

t_pd2

t_su

Propagation delay, SCLKOUT2 falling edge to SDOUT

Setup time, SDIN to SCLKOUT1 rising edge

Hold time, SDIN from SCLKOUT1 rising edge

Skew time, SCLKOUT1 to SCLKOUT2

20⁽¹⁾

23⁽¹⁾

t_h

t_(SKEW)

3⁽¹⁾

(1) This measurement in specified by design.

(2) Rise time and fall time measured from 20% to 80% of maximum height of waveform.

f(SCLKOUT)

r(SCLKOUT)

SCLKOUT2

SCLKOUT1

r(SCLKOUT)

f(SCLKOUT)

pd1(SCLKOUT2)

pd1(SCLKOUT1)

LRCLK

(Output)

, t

f(LRCLK) r(LRCLK)

pd2

SDOUT1

SDOUT2

SDOUT3

SDOUT4

SDIN1

SDIN2

SDIN3

SDIN4

T0091-01

Figure 8-3. TAS3108/TAS3108IA Serial Audio Port Master Mode Timing Waveforms

Electrical Specifications

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8.5.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I²C-Bus Devices

STANDARD MODE

FAST MODE

PARAMETER

TEST CONDITIONS

UNIT

MIN

–0.5⁽¹⁾

MAX

MIN

–0.5⁽¹⁾

MAX

V_IL

LOW-level input voltage

HIGH-level input voltage

Hysteresis of inputs

0.8

V_IH

V_hys

(1)

N/A

N/A 0.05 V_DD

LOW-level output voltage (open drain or

open collector)

V_OL1

3-mA sink current

0.4⁽¹⁾

Bus capacitance from 10 pF

to 400 pF

7 + 0.1 C_b

t_of

Output fall time from V_IHminto _VILmax

Input current, each I/O pin

250⁽¹⁾

10⁽³⁾

µA

(2)(1)

I_I

–10

N/A

–10⁽³⁾

SCL pulse duration of spikes that must

be suppressed by the input filter

t_SP(SCL)

N/A

14⁽⁴⁾⁽¹⁾

SDA pulse duration of spikes that must

be suppressed by the input filter

t_SP(SDA)

C_I

N/A

22⁽⁴⁾⁽¹⁾

Capacitance, each I/O pin

10⁽¹⁾

(1) This measurement in specified by design.

(2) C_b= capacitance of one bus line in pF. The output fall time is faster than the standard I²C specification.

(3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if V_DDis switched off.

(4) These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by one half, the t_SPdoubles.

NOTE

SDA does not have the standard I²C specification 300-ns internal hold time. SDA must be

valid by the rising and falling edges of SCL.

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8.5.5 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I²C-Bus

Devices

All values are referred to V_IHminand V_ILmax(see Section 8.5.4).

STANDARD MODE

MIN MAX

100

FAST MODE

MIN MAX

TEST

CONDITIONS

PARAMETER

UNIT

f_SCL

SCL clock frequency⁽¹⁾

0⁽¹⁾

400⁽²⁾

kHz

Hold time (repeated) START condition.

t_HD-STAAfter this period, the first clock pulse is

generated.

4⁽¹⁾

0.6⁽¹⁾

µs

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

4.7⁽¹⁾

4⁽¹⁾

4.7⁽¹⁾

250⁽¹⁾

0⁽¹⁾

1.3⁽¹⁾

0.6⁽¹⁾

100⁽¹⁾

0⁽¹⁾

µs

t_SU-STASetup time for repeated START

t_SU-DATData setup time

(3)(4)

t_HD-DATData hold time

3.45⁽¹⁾

1000⁽¹⁾

0.9⁽¹⁾

20 + 0.1

t_r

t_f

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL

300⁽¹⁾

(5)(1)

C_b

20 + 0.1

300⁽¹⁾

µs

(5)(1)

C_b

t_SU-STOSetup time for STOP condition

4⁽¹⁾

0.6⁽¹⁾

Bus free time between a STOP and

START condition

t_BUF

4.7⁽¹⁾

1.3⁽¹⁾

C_b

Capacitive load for each bus line

400⁽¹⁾

Noise margin at the LOW level for each

connected device (including hysteresis)

(1)

V_nL

0.1 V_DVDD

Noise margin at the HIGH level for each

connected device (including hysteresis)

(1)

V_nH

0.2 V_DVDD

(1) This measurement is specified by design.

(2) In master mode, the maximum speed is 375 kHz.

(3) Note that SDA does not have the standard I²C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges

of SCL. TI recommends that a 2-kΩ pullup resistor be used to avoid potential timing issues.

(4) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_SU-DAT≥ 250 ns must then be met.

This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line t_r-max+ t_SU-DAT= 1000 + 250 = 1250 ns (according to the

standard-mode I²C bus specification) before the SCL line is released.

(5) C_b= total capacitance of one bus line in pF.

SDA

SU-DAT

HD-STA

BUF

LOW

SCL

SU-STO

HD-DAT

SU-STA

HIGH

HD-STA

T0114-01

Figure 8-4. Start and Stop Conditions Timing Waveforms

Electrical Specifications

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8.5.5.1 Recommended I²C Pullup Resistors

It is recommended that the I²C pullup resistors R_Pbe 4.7 kΩ (see Figure 8-5). If a series resistor is in the

circuit (see Figure 8-6), then the series resistor R_Sshould be less than or equal to 300 Ω.

DVDD

TAS3108/TAS3108IA

External

Microcontroller

I_P

R_P

V_I(SDA)

V_I(SCL)

SDA

SCL

B0099-03

Figure 8-5. I²C Pullup Circuit (With No Series Resistor)

DVDD

TAS3108/TAS3108IA

External

Microcontroller

I_P

R_P

(2)

R_S

SDA

SCL

V_I

(1)

V_S

B0100-03

(1) V_S= DVDD × R_S/_S= R_P). When driven low, V_S<< V_ILrequirements.

(2) _S≤ 300 Ω

Figure 8-6. I²C Pullup Circuit (With Series Resistor)

8.5.6 Reset Timing (TAS3108/TAS3108IA)

control signal parameters over recommended operating conditions; these measurements are specified by design (unless

otherwise noted)

PARAMETER

Pulse duration, RESET active

Time to enable I²C

TEST CONDITIONS

MIN

10⁽¹⁾

MAX

UNIT

t_w(RESET)

t_r(run)

PLL0 = PLL1 = MICROCLK_DIV = 0

(1) This measurement is specified by design.

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Electrical Specifications

Not Recommended for New Designs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

www.ti.com

SLES152B–OCTOBER 2005–REVISED NOVEMBER 2007

RESET

Start of

Boot Sequence

w(RESET)

Outputs

Inactive

r(run)

Enable I C Start System

T0029-02

NOTE: MCLK input = 12.288 MHz

Figure 8-7. Reset Timing

Electrical Specifications

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Not Recommended for New Designs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

www.ti.com

SLES152B–OCTOBER 2005–REVISED NOVEMBER 2007

9 Application Information

9.1 Schematics

Figure 9-1 shows a typical TAS3108/TAS3108IA application. In this application, the following conditions

apply:

•

TAS3108/TAS3108IA is in clock-slave mode. The audio (SDIN1, SDIN2, SDIN3, SDIN4) and clock

source (MCLKI) are external.

•

MCLKI = 12.288 MHz

Because MCLKI is sourced externally, the TAS3108/TAS3108IA crystal interface is not used. MCLKI

and XTLI are logically ORed together, meaning that when the MCLKI pin is used, the XTALI pin must

be grounded.

I²C register 0x00 contains the default settings which means:

•

–

Audio data word size is 24-bit input and 24-bit output.

Serial data format is 2 channel, I²S for input and output.

I²C data transfer is approximately 400 kbps for both master and slave I²C interfaces.

PLL0 = PLL1 = PLL2 = 0 means that f_DSPCLKis 11 × MCLKI = 135.2 MHz and that

f_I2CSCL= 375 kHz.

–

Sample frequency (f_S) is 48 kHz, which requires that f_LRCLK= 48 kHz and f_SCLKIN= 3.072 MHz.

•

Application code and data are loaded from an external EEPROM using the master I²C interface.

Application commands come from the system microprocessor to the TAS3108/TAS3108IA using the

slave I²C interface.

Good design practice requires isolation between the digital and analog power as shown. Power-supply

capacitors of 10 µF and 0.1 µF should be placed near the power-supply pins AVDD (AVSS) and DVDD

(DVSS).

The TAS3108/TAS3108IA reset needs external glitch protection. Also, reset going HIGH should be

delayed until TAS3108/TAS3108IA internal power is good (~200 µs). This is provided by the 1-kΩ resistor,

1-µF capacitor, and diode placed near the RESET pin.

It is recommended that a 4.7-µF capacitor (fast ceramic type) be placed near pin 28 (VR_DIG). This pin

must not be used to source external components.

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Application Information

Not Recommended for New Designs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

www.ti.com

SLES152B–OCTOBER 2005–REVISED NOVEMBER 2007

AVSS

AVDD

RESERVED

PLL2

3.3V_AVDD

0.01 µF

VR_PLL

XTALI

XTALO

PLL1

47 Ω

MCLKI

PLL0

MICROCLK_DIV

RESERVED

RESET

System

Reset

0.1 µF

CS0

1 kΩ

GPIO

DVDD

DVSS

SDIN1

SDIN2

SDIN3

PDN

Audio

and

3.3 V

DVDD

3.3 V

Clock

Source

TAS3108

(TAS3108IA)

DVSS

47 Ω

4.7 µF

47 Ω

VR_DIG

SDOUT1

SDOUT2

SDOUT3

SDOUT4

SCLKOUT2

SCLKOUT1

MCLKO

SCLKIN

47 Ω

SDIN4

SDA1

10 Ω

Audio

Output

3.3 V

SCL1

SDA2

SCL2

LRCLK

System

Micropro-

cessor

System Reset

10 kΩ

to DVDD

3.3 Ω

3.3 V

3.3V_AVDD

TAS3108/

TAS3108IA

Power Supply

to AVDD

0.1 µF

EEPROM

(Program Code and Data)

(1)

10 µF

0.1 µF

Ferrite Bead

S0123-01

(1) Capacitors should be placed as close as possible to the power-supply pins.

Figure 9-1. Typical Application Diagram

Application Information

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Not Recommended for New Designs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

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SLES152B–OCTOBER 2005–REVISED NOVEMBER 2007

9.2 Recommended Oscillator Circuit

TAS3108/TAS3108IA

Osc

Circuit

AVSS

S0114-01

•

MCLKI and XTLI are logically ORed together, meaning that when the XTALI pin is used, the MCLKI pin

must be grounded.

•

Crystal type = Parallel-mode, fundamental-mode crystal

r_d= Drive-level control resistor – vendor specified

C_L= Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)

C_L= (C₁× C₂)/C₁+ C₂) + C_S(where C_S= board stray capacitance, ~2 pF)

9.3 Recommended PCB Design for TAS3108IA Applications

Automotive applications require that the TAS3108IA operates properly while in an ambient temperature

range of –40° C to 105°C. Under the high-temperature condition of 105°C ambient, the TAS3108IA

thermal pad must be soldered to a copper area on the PCB designed for thermal relief.

High-temperature applications also require that the application be built on a high-K dielectric PCB.

High-K dielectric PCB requirements for using TAS3108IA with soldered thermal pad:

•

0.062 in thick

Minimum 3-in × 3-in PCB

2-oz copper traces located on top of the board (0,071 mm thick)

Copper area located on the top and bottom of the PCB for soldering

Power and ground planes, 1-oz. copper (0,036 mm thick)

Thermal vias, 0.3-mm diameter, 1.5-mm pitch

Thermal isolation of power plane

If the target application limits the ambient temperature to 0°C to 70°C (standard commercial

temperature range), the thermal pad does not need to be soldered to the PCB.

For more information, see PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD^TM

Made Easy (SLMA004).

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Application Information

PACKAGE OPTION ADDENDUM

www.ti.com

2-Feb-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TAS3108DCP

TAS3108DCPG4

TAS3108DCPR

NRND

HTSSOP

DCP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

2000

Green (RoHS

& no Sb/Br)

TAS3108DCPRG4

TAS3108IADCP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TAS3108IADCPG4

TAS3108IADCPR

TAS3108IADCPRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Feb-2012

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS3108DCPR

HTSSOP DCP

2000

330.0

16.4

6.9

10.2

1.8

12.0

16.0

TAS3108IADCPR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TAS3108DCPR

HTSSOP

DCP

2000

367.0

38.0

TAS3108IADCPR

Pack Materials-Page 2

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TAS3108IADCP [TI]

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