SNJ54LVTH16646WD [TI]
3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位总线收发器和寄存器具有三态输出
| 型号： | SNJ54LVTH16646WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总14页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢘ ꢑꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙ ꢒꢆ ꢚ ꢒꢆ
SCBS698G − JULY 1997 − REVISED MAY 2004
SN54LVTH16646 . . . WD PACKAGE
SN74LVTH16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1OE
2
1CLKBA
1SBA
GND
1B1
3
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
4
5
1A1
1A2
3.3-V V
)
6
1B2
CC
7
V
V
D
D
D
D
Support Unregulated Battery Operation
Down to 2.7 V
CC
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
9
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
D
D
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flowthrough Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
V
V
CC
CC
2A7
2A8
GND
2B7
2B8
GND
2SBA
2CLKBA
2OE
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
2SAB
2CLKAB
2DIR
description/ordering information
The ’LVTH16646 devices are 16-bit bus
transceivers and registers designed for
low-voltage (3.3-V) V
operation, but with the
CC
capability to provide a TTL interface to a 5-V
system environment.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVTH16646DL
SN74LVTH16646DLR
SN74LVTH16646DGGR
SNJ54LVTH16646WD
SSOP − DL
LVTH16646
Tape and reel
−40°C to 85°C
−55°C to 125°C
TSSOP − DGG Tape and reel
CFP − WD Tube
LVTH16646
SNJ54LVTH16646WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
ꢒ ꢁ ꢄꢕꢀꢀ ꢙ ꢆꢇ ꢕꢓꢘ ꢑꢀ ꢕ ꢁ ꢙꢆꢕꢖ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢚꢓ ꢙ ꢖ ꢒ ꢔꢆ ꢑꢙ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢃ ꢉꢊ ꢀ ꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉ ꢃ ꢉ
ꢌꢍ ꢌꢎꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢎ ꢐꢑ ꢆ ꢐꢒ ꢀ ꢆꢓ ꢏꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ ꢏꢁꢖ ꢓꢕꢗ ꢑ ꢀꢆ ꢕꢓꢀ
ꢘꢑ ꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙꢒꢆ ꢚꢒ ꢆꢀ
SCBS698G − JULY 1997 − REVISED MAY 2004
description/ordering information (continued)
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’LVTH16646
devices.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1−A8
Input
B1−B8
†
†
↑
X
Unspecified
Store A, B unspecified
†
†
X
X
↑
X
X
Unspecified
Input
Store B, A unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
X
X
X
Input disabled
Output
Input disabled
Input
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the
bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS698G − JULY 1997 − REVISED MAY 2004
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢃ ꢉꢊ ꢀ ꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉ ꢃ ꢉ
ꢌꢍ ꢌꢎꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢎ ꢐꢑ ꢆ ꢐꢒ ꢀ ꢆꢓ ꢏꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ ꢏꢁꢖ ꢓꢕꢗ ꢑ ꢀꢆ ꢕꢓꢀ
ꢘꢑ ꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙꢒꢆ ꢚꢒ ꢆꢀ
SCBS698G − JULY 1997 − REVISED MAY 2004
logic diagram (positive logic)
56
1OE
1
1DIR
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OE
28
2DIR
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘ ꢑꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙ ꢒꢆ ꢚ ꢒꢆ
SCBS698G − JULY 1997 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH16646 . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH16646 . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51−7.
recommended operating conditions (see Note 4)
SN54LVTH16646 SN74LVTH16646
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−24
48
0.8
5.5
−32
64
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢃ ꢉꢊ ꢀ ꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉ ꢃ ꢉ
ꢌꢍ ꢌꢎꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢎ ꢐꢑ ꢆ ꢐꢒ ꢀ ꢆꢓ ꢏꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ ꢏꢁꢖ ꢓꢕꢗ ꢑ ꢀꢆ ꢕꢓꢀ
ꢘꢑ ꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙꢒꢆ ꢚꢒ ꢆꢀ
SCBS698G − JULY 1997 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16646
SN74LVTH16646
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
−1.2
−1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −24 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
−0.2
CC
2.4
V
−0.2
CC
2.4
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
1
V
V
= 3.6 V,
V = V
I CC
or GND
1
10
20
1
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
20
1
CC
V = 5.5 V
I
I
I
µA
‡
V = V
V
CC
= 3.6 V
A or B ports
I
CC
V = 0
−5
−5
100
I
I
I
V
V
= 0,
V or V = 0 to 4.5 V
I
µA
µA
off
CC
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
−75
−75
A or B ports
I(hold)
§
V
V
= 3.6 V ,
V = 0 to 3.6 V
500
100
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
CC
O
100*
100*
µA
µA
I
I
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
100
OZPD
Outputs high
Outputs low
0.19
5
0.19
5
V
= 3.6 V, I = 0,
O
CC
V = V
I
mA
mA
CC
or GND
CC
I
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
¶
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
10
10
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
or GND
‡
§
¶
Unused pins at V
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
ꢚ
ꢓ
ꢙ
ꢖ
ꢒ
ꢔ
ꢆ
ꢚ
ꢓ
ꢕ
ꢅ
ꢑ
ꢕ
ꢘ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢟ ꢤ ꢞ ꢝ ꢯ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢰ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢍ ꢔ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢰ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢯ
ꢥ
ꢯ
ꢠ
ꢦ
ꢫ
ꢞ
ꢍ
ꢆ
ꢤ
ꢬ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜ ꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢍ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢰ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢯ
ꢜ
ꢛ
ꢛ
ꢠ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢉ
ꢃ
ꢉ
ꢊ
ꢀ
ꢁ
ꢋ
ꢃ
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢈ ꢉ ꢎꢐꢑ ꢆ ꢐꢒꢀ ꢆ ꢓꢏꢁꢀ ꢔꢕꢑ ꢅꢕꢓꢀ ꢏꢁꢖ ꢓꢕ ꢗ ꢑꢀ ꢆꢕ ꢓ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢉ
ꢃ
ꢉ
ꢀ
ꢀ
ꢘ ꢑꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙ ꢒꢆ ꢚ ꢒꢆ
SCBS698G − JULY 1997 − REVISED MAY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH16646
= 3.3 V
SN74LVTH16646
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
0.3 V
0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1.2
2
3.3
1.5
2.8
0
3.3
1.2
2
3.3
1.5
2.8
0
w
Data high
Data low
Data high
Data low
Setup time,
A or B before CLKAB↑ or CLKBA↑
t
ns
ns
su
h
0.5
0.5
0.5
0.5
Hold time,
A or B after CLKAB↑ or CLKBA↑
t
0.5
0.5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
SN54LVTH16646
= 3.3 V
SN74LVTH16646
V
V
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
0.3 V
0.3 V
†
MIN
150
1.3
1.3
1
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
150
150
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
4.5
4.5
3.6
3.6
4.7
4.7
4.5
4.5
5.8
5.6
4.6
4.6
6
5
5
1.3
1.3
1
2.8
2.8
2.4
2.1
2.8
3
4.2
4.2
3.4
3.4
4.5
4.5
4.3
4.3
5.6
5.4
4.4
4.4
5.7
5.2
4.7
4.7
3.9
3.9
5.4
5.4
5.2
5.2
6.1
6.1
5.3
5.3
6.8
5.7
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
A or B
A or B
A or B
4.1
4.1
5.6
5.6
5.4
5.4
6.3
6.3
5.5
5.5
7.1
6
A or B
SBA or SAB
OE
ns
ns
ns
ns
ns
ns
1
1
1
1
‡
1
1
1
1
2.5
2.6
4
1
1
2
2
OE
2
2
3.6
3
1
1
DIR
1
1
3
1.5
1.5
1.5
1.5
3.9
3.6
DIR
5.5
†
‡
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
ꢚ
ꢓ
ꢙ
ꢖ
ꢒ
ꢔ
ꢆ
ꢚ
ꢓ
ꢕ
ꢅ
ꢑ
ꢕ
ꢘ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢟꢤ ꢞ ꢝ ꢯꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢰ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢍ ꢔ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢡ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢰ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢯ
ꢥ
ꢯ
ꢠ
ꢦ
ꢫ
ꢞ
ꢍ
ꢆ
ꢤ
ꢬ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢍ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢰ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢯ
ꢜ
ꢛ
ꢛ
ꢠ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢉꢃ ꢉꢊ ꢀ ꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉ ꢃ ꢉ
ꢌꢍ ꢌꢎꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢎ ꢐꢑ ꢆ ꢐꢒ ꢀ ꢆꢓ ꢏꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ ꢏꢁꢖ ꢓꢕꢗ ꢑ ꢀꢆ ꢕꢓꢀ
ꢘꢑ ꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢙꢒꢆ ꢚꢒ ꢆꢀ
SCBS698G − JULY 1997 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
6 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
su
h
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
V
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
OL
+ 0.3 V
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
− 0.3 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jul-2007
PACKAGING INFORMATION
Orderable Device
74LVTH16646DGGRE4
74LVTH16646DLRG4
SN74LVTH16646DGGR
SN74LVTH16646DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SSOP
TSSOP
SSOP
SSOP
SSOP
DL
DGG
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH16646DLG4
SN74LVTH16646DLR
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74LVTH16646DGGR TSSOP
SN74LVTH16646DLR SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35
18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVTH16646DGGR
SN74LVTH16646DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
346.0
346.0
346.0
346.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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