SNJ54LVTH240FK [TI]
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT八路缓冲器/驱动器,具有三态输出型号: | SNJ54LVTH240FK |
厂家: | TEXAS INSTRUMENTS |
描述: | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
文件: | 总18页 (文件大小:445K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
D
D
D
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
A
I
and Power-Up 3-State Support Hot
off
Insertion
SN54LVTH240 . . . FK PACKAGE
SN54LVTH240 . . . J OR W PACKAGE
SN74LVTH240 . . . DB, DW, NS,
OR PW PACKAGE
SN74LVTH240 . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
20
3
2
1 20 19
18
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1Y1
17 2A4
1A2
2Y3
1A3
2Y2
1A4
4
5
6
7
8
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
16
15
14
1Y2
2A3
1Y3
9 10 11 12 13
10
11
description/ordering information
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − DW
Tape and reel SN74LVTH240RGYR
LXH240
Tube
SN74LVTH240DW
LVTH240
Tape and reel SN74LVTH240DWR
Tape and reel SN74LVTH240NSR
Tape and reel SN74LVTH240DBR
SOP − NS
LVTH240
LXH240
SSOP − DB
−40°C to 85°C
Tube
SN74LVTH240PW
TSSOP − PW
LXH240
LXH240
Tape and reel SN74LVTH240PWR
SN74LVTH240GQNR
VFBGA − GQN
VFBGA − ZQN (Pb-free)
CDIP − J
Tape and reel
SN74LVTH240ZQNR
Tube
Tube
Tube
SNJ54LVTH240J
SNJ54LVTH240W
SNJ54LVTH240FK
SNJ54LVTH240J
SNJ54LVTH240W
SNJ54LVTH240FK
CFP − W
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢑ ꢝ ꢨ ꢠ ꢟꢫ ꢦꢥ ꢣꢤ ꢥꢟ ꢡꢨ ꢪꢜ ꢢꢝ ꢣ ꢣꢟ ꢱꢙ ꢄꢎ ꢛꢖ ꢔ ꢎꢌꢲꢂ ꢌꢂꢊ ꢢꢪꢪ ꢨꢢ ꢠ ꢢ ꢡꢧ ꢣꢧꢠ ꢤ ꢢ ꢠ ꢧ ꢣꢧ ꢤꢣꢧ ꢫ
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1
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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
SN74LVTH240 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
2
3
4
A
B
C
D
E
A
B
C
D
E
1A1
1A2
1A3
1A4
GND
1OE
2A4
2Y3
2A2
2Y1
V
2OE
1Y1
1Y2
1Y3
1Y4
CC
2Y4
2A3
2Y2
2A1
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
2
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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1
19
1OE
2OE
2A1
2
18
16
14
12
11
13
15
17
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
4
1A2
2A2
2A3
2A4
6
1A3
8
1A4
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH240 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 5)
SN54LVTH240 SN74LVTH240
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−24
48
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 5: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH240
SN74LVTH240
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
= 2.7 V,
I = −18 mA
−1.2
−1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −24 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
−0.2
V
CC
−0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
2.4
2
2.4
2
V
V
OH
V
= 3 V
CC
CC
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
10
1
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
10
1
CC
Control inputs
Data inputs
V = V
or GND
CC
I
CC
I
I
I
µA
µA
µA
I
V = V
1
1
I
CC
V
V
= 3.6 V
CC
V = 0
I
−5
−5
100
= 0, V or V = 0 to 4.5 V
off
CC
I
O
V = 0.8 V
I
75
75
V
CC
V
CC
= 3 V
V = 2 V
I
−75
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
−5
−5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
∗
100
100
100
100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
∗
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
O
CC
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
CC
= 3 V to 3.6 V,
§
One input at V
− 0.6 V,
or GND
0.2
0.2
∆I
CC
CC
Other inputs at V
CC
C
C
V = 3 V or 0
3
7
3
7
pF
pF
i
I
V
O
= 3 V or 0
o
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
5
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ꢌꢍ
ꢌ
ꢎ
ꢅ
ꢏ
ꢐ
ꢆ
ꢑꢒ
ꢆ
ꢏ
ꢄ
ꢐ
ꢓ
ꢔ
ꢔ
ꢕ
ꢖ
ꢀ
ꢗ
ꢘ
ꢖ
ꢙ
ꢅ
ꢕ
ꢖ
ꢀ
ꢚ
ꢙ
ꢆ
ꢇ
ꢌ
ꢎ
ꢀ
ꢆ
ꢏ
ꢆ
ꢕ
ꢑ
ꢓ
ꢆ
ꢛ
ꢓ
ꢆ
ꢀ
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54LVTH240
SN74LVTH240
V = 3.3 V
CC
0.3 V
V
CC
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
0.3 V
†
MIN
MAX
4.3
4.7
5.7
5.5
5.1
5.4
MIN
MAX
5.1
4.9
6.7
6.2
5.2
5.4
MIN TYP
MAX
3.8
4
MIN
MAX
4.6
4.2
5.6
5
t
t
t
t
t
t
0.9
1.2
1
1.1
1.3
1.1
1.4
2
2.2
2.6
2.6
2.7
2.9
3
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
4.6
4.4
4.4
4.3
OE
OE
1.2
1
4.6
4.3
1.1
1.8
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢃ
ꢉ
ꢊ
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢑ ꢒꢆꢏꢄ ꢐꢓꢔ ꢔ ꢕꢖꢀꢗ ꢘ ꢖꢙ ꢅ ꢕꢖ
ꢀ
ꢁ
ꢋ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢃ
ꢉ
ꢀ
ꢀ
ꢚ ꢙꢆ ꢇ ꢌ ꢎꢀꢆꢏꢆ ꢕ ꢑ ꢓꢆ ꢛꢓ ꢆ
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
t
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MCFP006B − JANUARY 1995 − REVISED JULY 2003
W (R-GDFP-F20)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.300 (7,62)
0.245 (6,22)
0.045 (1,14)
0.026 (0,66)
0.009 (0,23)
0.004 (0,10)
0.100 (2,54)
0.045 (1,14)
0.320 (8,13) MAX
0.022 (0,56)
0.015 (0,38)
1
20
0.050 (1,27)
0.540 (13,72)
MAX
0.005 (0,13) MIN
4 Places
10
11
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
4040180-4/D 07/03
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within Mil-Std 1835 GDFP2-F20
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPBG133C – APRIL 2000 – REVISED AUGUST 2002
GQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95 TYP
3,10
2,90
0,65
0,325
E
D
C
B
A
4,10
3,90
2,60
1
2
3
4
A1 Corner
Bottom View
1,00 MAX
0,08
Seating Plane
0,25
0,15
0,45
20×
0,35
M
0,05
4200704/D 07/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Juniort configuration
D. Falls within JEDEC MO-225 variation BC.
E. This package is tin-lead (SnPb). Refer to the 20 ZQN package (drawing 4204492) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPBG297 – JULY 2002
ZQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95
0,65
3,10
2,90
0,325
E
D
C
B
A
4,10
3,90
2,60
1
2
3
4
Bottom View
A1 Corner
1,00 Max
0,08
Seating Plane
0,25
0,15
0,45
0,35
20×
0,05
M
4204492/A 06/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior configuration.
D. Fall within JEDEC MO-225 variation BC.
E. This package is lead-free. Refer to the 20 GQN package (drawing 4200704) for tin-lead )SnPb).
MicroStar Junior is a trademark of Texas Instruments.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
(18,03)
A MAX
(10,41) (11,73) (12,95) (15,49)
0.400
0.453
0.500
0.600
0.700
(17,78)
A MIN
(10,16) (11,51) (12,70) (15,24)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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