SNJ54HC595FKR [TI]
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20;
| 型号： | SNJ54HC595FKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20 输出元件 逻辑集成电路 触发器 |
| 文件： | 总27页 (文件大小：1212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC595
SN74HC595
www.ti.com
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
Check for Samples: SN54HC595 SN74HC595
1
FEATURES
SN54HC595...J OR W PACKAGE
SN74HC595...D, DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
•
•
•
8-Bit Serial-In, Parallel-Out Shift
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up To
15 LSTTL Loads
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
Q
C
D
A
•
•
•
•
•
Low Power Consumption: 80-μA (Max) ICC
tpd = 13 ns (Typ)
Q
SER
OE
Q
E
Q
Q
12 RCLK
F
±6-mA Output Drive at 5 V
11
10
9
SRCLK
SRCLR
G
Low Input Current: 1 μA (Max)
Shift Register Has Direct Clear
Q
H
GND
Q ′
H
DESCRIPTION
SN54HC595...FK PACKAGE
(TOP VIEW)
The 'HC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for both
the shift and storage register. The shift register has a
direct overriding clear (SRCLR) input, serial (SER)
input, and serial outputs for cascading. When the
output-enable (OE) input is high, the outputs are in
the high-impedance state.
3
2
1
2 0 1 9
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
E
NC
NC
15 RCLK
Q
F
14
9 10 11 12 1 3
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered. If
both clocks are connected together, the shift register
always is one clock pulse ahead of the storage
register.
SRCLK
Q
G
NC – No internal connection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1982–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54HC595
SN74HC595
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
www.ti.com
ORDERING INFORMATION(1)
(2)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SN74HC595N
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Tube of 40
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC595N
SN74HC595D
SN74HC595DR
SN74HC595DT
HC595
SN74HC595DW
SN74HC595DWR
SN74HC595NSR
SN74HC595DBR
SN74HC595PW
SN74HC595PWR
SNJ54HC595J
–40°C to 85°C
SOIC − DW
HC595
SOP − NS
HC595
HC595
SSOP − DB
TSSOP – PW
HC595
CDIP − J
CFP − W
LCCC − FK
SNJ54HC595J
SNJ54HC595W
SNJ54HC595FK
–55°C to 125°C
SNJ54HC595W
SNJ54HC595FK
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
INPUTS
FUNCTION
SER
X
SRCLK
SRCLR
RCLK
OE
H
X
X
X
X
X
L
X
X
X
Outputs QA−QH are disabled.
Outputs QA−QH are enabled.
Shift register is cleared.
X
L
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored in the storage register.
2
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Copyright © 1982–2009, Texas Instruments Incorporated
Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
www.ti.com
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
LOGIC DIAGRAM (POSITIVE LOGIC)
13
12
OE
RCLK
10
11
14
SRCLR
SRCLK
SER
1D
C1
3R
C3
15
Q
A
R
3S
2S
2R
3R
1
Q
C2
C3
B
R
3S
2S
2R
3R
2
C2
C3
Q
C
R
3S
2S
2R
3R
3
Q
C2
C3
D
R
3S
2S
2R
3R
4
Q
Q
Q
C2
C3
E
R
3S
2S
2R
3R
5
C2
C3
F
R
3S
2S
2R
3R
6
C2
C3
G
R
3S
2S
2R
3R
7
9
Q
Q
C2
C3
3S
H
R
H′
Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages.
Copyright © 1982–2009, Texas Instruments Incorporated
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Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
www.ti.com
TIMING DIAGRAM
SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
NOTE:
implies that the output is in 3-State mode.
4
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Copyright © 1982–2009, Texas Instruments Incorporated
Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
www.ti.com
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
Input clamp current(2)
Output clamp current
−0.5 V to 7 V
IIK
VI < 0 or VI > VCC
±20 mA
±20 mA
(2)
IOK
IO
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
±35 mA
Continuous current through VCC or GND
±70 mA
D package
73°C/W
DB package
DW package
N package
82°C/W
57°C/W
θJA
Package thermal impedance(3)
67°C/W
NS package
PW package
64°C/W
108°C/W
−65°C to 150°C
Tstg
Storage temperature range
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
SN54HC595
SN74HC595
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VIH
High-level input voltage
3.15
4.2
3.15
4.2
V
V
0.5
1.35
1.8
0.5
1.35
1.8
VIL
Low-level input voltage
VI
Input voltage
0
0
VCC
VCC
1000
500
400
125
0
0
VCC
VCC
1000
500
400
85
V
V
VO
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
Δt/Δv Input transition rise/fall time(2)
ns
°C
TA
Operating free-air temperature
–55
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Copyright © 1982–2009, Texas Instruments Incorporated
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Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
SN54HC595
SN74HC595
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
IOH = −20 μA
4.4
5.9
VOH
VI = VIH or VIL
QH′, IOH = −4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
4.5 V
6 V
QA−QH, IOH = −6 mA
QH′, IOH = −5.2 mA
QA−QH, IOH = −7.8 mA
3.98
5.48
5.48
5.8
5.8
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
±0.1
±0.01
0.1
0.1
0.1
0.1
0.1
0.1
IOL = 20 μA
0.1
0.1
0.1
VOL
VI = VIH or VIL
QH′, IOL = 4 mA
0.26
0.26
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
0.33
0.33
±1000
±5
V
4.5 V
6 V
QA−QH, IOL = 6 mA
QH′, IOL = 5.2 mA
QA−QH, IOL = 7.8 mA
0.4
0.4
0.4
II
VI = VCC or 0
6 V
6 V
6 V
±1000
±10
160
nA
µA
µA
IOZ
ICC
VO = VCC or 0, QA−QH
VI = VCC or 0, IO = 0
80
2 V
to 6 V
Ci
3
10
10
10
pF
6
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Copyright © 1982–2009, Texas Instruments Incorporated
Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
www.ti.com
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
SN54HC595
SN74HC595
VCC
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
2 V
4.5 V
6 V
6
31
36
4.2
21
25
5
fclock
Clock frequency
Pulse duration
25 MHz
29
2 V
80
16
14
80
16
14
100
20
17
75
15
13
50
10
9
120
24
20
120
24
20
150
30
25
113
23
19
75
15
13
75
15
13
0
100
20
17
100
20
17
125
25
21
94
19
16
65
13
11
60
12
11
0
SRCLK or RCLK high or low
SRCLR low
4.5 V
6 V
tw
ns
2 V
4.5 V
6 V
2 V
SER before SRCLK↑
4.5 V
6 V
2 V
SRCLK↑ before RCLK↑(1)
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
4.5 V
6 V
tsu
Setup time
ns
2 V
4.5 V
6 V
2 V
50
10
9
4.5 V
6 V
2 V
0
th
Hold time, SER after SRCLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
Copyright © 1982–2009, Texas Instruments Incorporated
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Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted)
TA = 25°C
TYP
26
38
42
50
17
14
50
17
14
51
18
15
40
15
13
42
23
20
28
8
SN54HC595
SN74HC595
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
fmax
31
36
25
29
MHz
25
2 V
160
32
240
48
200
40
SRCLK
RCLK
SRCLR
OE
QH′
4.5 V
6 V
27
41
34
tpd
ns
2 V
150
30
225
45
187
37
QA−QH
4.5 V
6 V
26
38
32
2 V
175
35
261
52
219
44
tPHL
QH′
4.5 V
6 V
ns
ns
ns
30
44
37
2 V
150
30
255
45
187
37
ten
QA−QH
QA−QH
QA−QH
QH′
4.5 V
6 V
26
38
32
2 V
200
40
300
60
250
50
tdis
OE
4.5 V
6 V
34
51
43
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
tt
ns
2 V
28
8
75
110
22
95
4.5 V
6 V
15
19
6
13
19
16
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted)
TA = 25°C
SN54HC595
SN74HC595
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN
TYP
60
22
19
70
23
19
45
17
13
MAX
200
40
MIN
MAX
300
60
2 V
4.5 V
6 V
250
50
tpd
RCLK
OE
QA−QH
QA−QH
QA−QH
ns
34
51
43
2 V
200
40
298
60
250
50
ten
4.5 V
6 V
ns
ns
34
51
43
2 V
210
42
315
63
265
53
tt
4.5 V
6 V
36
53
45
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
TEST CONDITIONS
No load
TYP UNIT
400 pF
Cpd
Power dissipation capacitance
8
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Copyright © 1982–2009, Texas Instruments Incorporated
Product Folder Link(s): SN54HC595 SN74HC595
SN54HC595
SN74HC595
www.ti.com
SCLS041H –DECEMBER 1982–REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
Open
Closed
Open
PHZ
C
(see Note A)
L
t
50 pF
dis
t
Closed
PLZ
50 pF
or
150 pF
t
or t
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
t
90%
50%
10%
50%
10%
CC
Low-Level
Pulse
0 V
50%
50%
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
t
50%
50%
0 V
V
0 V
t
PLH
PHL
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
Output
Waveform 1
(See Note B)
In-Phase
Output
CC
90%
t
90%
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
f
t
t
t
PLH
PZH
PHZ
PHL
90%
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
max
E. The outputs are measured one at a time, with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t .
en
are the same as t .
and t
PHL
pd
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1982–2009, Texas Instruments Incorporated
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Product Folder Link(s): SN54HC595 SN74HC595
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-86816012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
86816012A
SNJ54HC
595FK
5962-8681601EA
5962-8681601VEA
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8681601EA
SNJ54HC595J
5962-8681601VE
A
SNV54HC595J
5962-8681601VFA
ACTIVE
CFP
W
16
1
TBD
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8681601VF
A
SNV54HC595W
SN54HC595J
SN74HC595D
ACTIVE
ACTIVE
CDIP
SOIC
J
16
16
1
A42
N / A for Pkg Type
-55 to 125
-40 to 85
SN54HC595J
D
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC595
SN74HC595DBR
SN74HC595DBRE4
SN74HC595DBRG4
SN74HC595DE4
SN74HC595DG4
SN74HC595DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
DB
D
16
16
16
16
16
16
16
16
16
2000
2000
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
HC595
HC595
HC595
HC595
HC595
HC595
HC595
HC595
HC595
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
D
40
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
2500
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
SN74HC595DRE4
SN74HC595DRG3
SN74HC595DRG4
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
D
Green (RoHS
& no Sb/Br)
CU SN
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74HC595DT
SN74HC595DTE4
SN74HC595DTG4
SN74HC595DW
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
HC595
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
250
250
40
Green (RoHS
& no Sb/Br)
HC595
D
Green (RoHS
& no Sb/Br)
HC595
DW
DW
DW
DW
DW
DW
N
Green (RoHS
& no Sb/Br)
HC595
SN74HC595DWE4
SN74HC595DWG4
SN74HC595DWR
SN74HC595DWRE4
SN74HC595DWRG4
SN74HC595N
40
Green (RoHS
& no Sb/Br)
HC595
40
Green (RoHS
& no Sb/Br)
HC595
2000
2000
2000
25
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
HC595
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
HC595
Green (RoHS
& no Sb/Br)
HC595
Pb-Free
(RoHS)
SN74HC595N
SN74HC595N
HC595
SN74HC595NE4
SN74HC595NSR
SN74HC595NSRE4
SN74HC595NSRG4
SN74HC595PW
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
NS
NS
NS
PW
PW
PW
PW
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SO
Green (RoHS
& no Sb/Br)
HC595
SO
Green (RoHS
& no Sb/Br)
HC595
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
HC595
SN74HC595PWE4
SN74HC595PWG4
SN74HC595PWR
90
Green (RoHS
& no Sb/Br)
HC595
90
Green (RoHS
& no Sb/Br)
HC595
2000
Green (RoHS
& no Sb/Br)
HC595
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74HC595PWRE4
SN74HC595PWRG4
SNJ54HC595FK
ACTIVE
TSSOP
TSSOP
LCCC
PW
16
16
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
HC595
ACTIVE
ACTIVE
PW
FK
2000
1
Green (RoHS
& no Sb/Br)
-40 to 85
HC595
TBD
-55 to 125
5962-
86816012A
SNJ54HC
595FK
SNJ54HC595J
SNJ54HC595W
ACTIVE
CDIP
J
16
16
1
TBD
TBD
A42
N / A for Pkg Type
Call TI
-55 to 125
-55 to 125
5962-8681601EA
SNJ54HC595J
OBSOLETE
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC595, SN54HC595-SP, SN74HC595 :
Catalog: SN74HC595, SN54HC595
•
Enhanced Product: SN74HC595-EP, SN74HC595-EP
•
Military: SN54HC595
•
Space: SN54HC595-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC595DBR
SN74HC595DR
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
DB
D
16
16
16
16
16
16
16
16
2000
2500
2500
2500
2500
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.8
16.8
16.4
16.4
16.4
16.4
12.4
8.2
6.5
6.5
6.5
6.5
6.6
2.5
2.1
2.1
2.1
2.1
2.7
2.7
1.6
12.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.3
10.3
10.3
10.3
SN74HC595DRG3
SN74HC595DRG4
SN74HC595DRG4
SN74HC595DWR
SN74HC595DWRG4
SN74HC595PWR
D
8.0
D
8.0
D
8.0
DW
DW
PW
10.75 10.7
10.75 10.7
12.0
12.0
8.0
6.9
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC595DBR
SN74HC595DR
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
DB
D
16
16
16
16
16
16
16
16
2000
2500
2500
2500
2500
2000
2000
2000
367.0
364.0
364.0
367.0
333.2
366.0
367.0
367.0
367.0
364.0
364.0
367.0
345.9
364.0
367.0
367.0
38.0
27.0
27.0
38.0
28.6
50.0
38.0
35.0
SN74HC595DRG3
SN74HC595DRG4
SN74HC595DRG4
SN74HC595DWR
SN74HC595DWRG4
SN74HC595PWR
D
D
D
DW
DW
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Copyright © 2013, Texas Instruments Incorporated
相关型号：
SNJ54HC595J-00
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16
TI
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