SNJ54HC594J [TI]
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16;
| 型号： | SNJ54HC594J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
Wide Operating Voltage Range of 2 V to 6 V
Low Input Current of 1 µA Max
High-Current Outputs Can Drive Up To
15 LSTTL Loads
8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
Low Power Consumption, 80-µA Max I
Independent Direct Overriding Clears on
Shift and Storage Registers
CC
Typical t = 15 ns
pd
Independent Clocks for Both Shift and
Storage Registers
±6-mA Output Drive at 5 V
SN54HC594 . . . J OR W PACKAGE
SN74HC594 . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC594 . . . FK PACKAGE
(TOP VIEW)
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
3
2
1
20 19
18
C
D
A
SER
RCLR
NC
Q
4
5
6
7
8
D
Q
SER
Q
17
16
15
E
Q
RCLR
RCLK
SRCLK
SRCLR
E
NC
Q
F
RCLK
Q
F
Q
G
14 SRCLK
9 10 11 12 13
Q
G
Q
H
GND
Q
H′
NC – No internal connection
description/ordering information
The ’HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and
storage registers. A serial (Q ) output is provided for cascading purposes.
H′
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks
are connected together, the shift register always is one count pulse ahead of the storage register.
The parallel (Q –Q ) outputs have high-current capability. Q is a standard output.
A
H
H′
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74HC594N
SN74HC594N
Tube
SN74HC594D
HC594
–40°C to 85°C
Tape and reel
Tube
SN74HC594DR
SN74HC594DW
SN74HC594DWR
SNJ54HC594J
SNJ54HC594W
SNJ54HC594FK
SOIC – DW
HC594
Tape and reel
Tube
CDIP – J
CFP – W
LCCC – FK
SNJ54HC594J
SNJ54HC594W
SNJ54HC594FK
–55°C to 125°C
Tube
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
L
X
X
X
↓
H
X
X
X
X
X
↑
X
L
Shift register state is not changed.
Storage register is cleared.
X
X
X
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
↓
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3R
C3
14
SER
1D
C1
15
Q
Q
A
B
R
3S
2S
2R
R
3R
1
C2
C3
R
3S
2S
2R
C2
R
3R
2
Q
Q
C
D
C3
R
3S
2S
2R
C2
R
3R
3
C3
R
3S
2S
2R
C2
R
3R
4
Q
Q
Q
E
F
C3
R
3S
2S
2R
C2
R
3R
5
C3
R
3S
2S
2R
C2
R
3R
6
G
C3
R
3S
2S
2R
C2
R
3R
C3
3S
7
9
Q
Q
H
R
H′
Pin numbers shown are for the D, DW, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H′
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54HC594
MIN NOM
SN74HC594
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
ns
t
T
–55
–40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC594
SN74HC594
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.5 V
6 V
4.4
OH
5.9
V
OH
V = V or V
IH
Q
, I
H′ OH
= –4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
I
IL
4.5 V
6 V
Q –Q , I
= –6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= –5.2 mA
5.8
Q –Q , I
= –7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
±0.1
±0.01
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
V
OL
V = V or V
Q
, I
H′ OL
= 4 mA
0.26
0.26
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
0.33
0.33
±1000
±5
V
I
IH
IL
4.5 V
6 V
Q –Q , I
= 6 mA
0.4
A
H
OL
Q
, I
H′ OL
= 5.2 mA
0.4
Q –Q , I = 7.8 mA
H OL
0.4
A
I
I
I
V = V
or 0
6 V
6 V
6 V
±1000
±10
160
nA
µA
µA
I
I
CC
CC
V
O
= V
or 0
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
80
2 V
to 6 V
C
3
10
10
10
pF
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC594
SN74HC594
A
V
UNIT
CC
MIN
MAX
5
MIN
MAX
3.3
17
MIN
MAX
4
2 V
f
Clock frequency
Pulse duration
4.5 V
6 V
25
20
MHz
clock
29
20
24
2 V
100
20
17
100
20
17
90
18
15
90
18
15
50
10
9
150
30
25
150
30
25
135
27
23
135
27
23
75
15
13
20
10
10
5
125
25
21
125
25
21
110
22
19
110
22
19
63
13
11
20
10
10
5
SRCLK or RCLK high or low
SRCLR or RCLR low
4.5 V
6 V
t
w
ns
2 V
4.5 V
6 V
2 V
SER before SRCLK↑
4.5 V
6 V
2 V
†
SRCLK↑ before RCLK↑
4.5 V
6 V
2 V
t
su
Setup time
SRCLR low before RCLK↑
4.5 V
6 V
ns
2 V
20
10
10
5
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before SRCLK↑
4.5 V
6 V
2 V
4.5 V
6 V
5
5
5
5
5
5
2 V
5
5
5
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
5
5
5
ns
5
5
5
†
This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in which
case the output register is one clock pulse behind the shift register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
8
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5
MAX
MIN
3.3
17
MAX
MIN
4
MAX
2 V
f
4.5 V
6 V
25
29
35
40
50
20
15
50
20
15
50
20
15
50
20
15
38
8
20
24
MHz
max
pd
20
2 V
150
30
225
45
185
37
SRCLK
RCLK
Q
4.5 V
6 V
H′
25
38
31
t
ns
ns
ns
2 V
150
30
225
45
185
37
Q –Q
A
4.5 V
6 V
H
H
H
25
38
31
2 V
150
30
225
45
185
37
SRCLR
RCLR
Q
4.5 V
6 V
H′
25
38
31
t
PHL
2 V
125
25
185
37
155
31
Q –Q
A
4.5 V
6 V
21
31
26
2 V
75
110
22
95
Q
4.5 V
6 V
15
19
H′
6
13
19
16
t
t
2 V
38
8
60
90
75
Q –Q
A
4.5 V
6 V
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
90
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
t
t
t
RCLK
RCLR
Q –Q
A
4.5 V
6 V
23
ns
pd
PHL
t
H
H
H
19
34
51
43
2 V
90
200
40
300
60
250
50
Q –Q
A
4.5 V
6 V
23
ns
ns
19
34
51
43
2 V
45
210
42
315
63
265
53
Q –Q
A
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
395
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040D – DECEMBER 1982 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
F. t and t are the same as t .
t
.
pd
PLH
PHL
f
r
t
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
0.775
0.920
1.060
A MAX
A
(19,69) (19,69) (23,37) (26,92)
16
9
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21,59) (23,88)
MS-100
VARIATION
0.260 (6,60)
0.240 (6,10)
AA
BB
AC
AD
C
1
8
0.070 (1,78)
0.045 (1,14)
D
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
D
0.030 (0,76)
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
(18,03)
A MAX
(10,41) (11,73) (12,95) (15,49)
0.400
0.453
0.500
0.600
0.700
(17,78)
A MIN
(10,16) (11,51) (12,70) (15,24)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
1
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