SNJ54CDC586WD [TI]
3.3-V Phase-Lock-Loop Clock Driver With 3-State Outputs 56-CFP -55 to 125;
| 型号： | SNJ54CDC586WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V Phase-Lock-Loop Clock Driver With 3-State Outputs 56-CFP -55 to 125 驱动 CD 信息通信管理 逻辑集成电路 |
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SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
WD PACKAGE
(TOP VIEW)
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V V
CC
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Distributes One Clock Input to Twelve
Outputs
2
AV
CLKIN
NC
CC
3
AGND
Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
4
FBIN
AGND
SEL0
SEL1
GND
GND
1Y1
AV
CC
5
OE
6
TEST
CLR
No External RC Network Required
7
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
8
V
CC
9
4Y3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
Application for Synchronous DRAM,
High-Speed Microprocessor
V
V
CC
CC
GND
1Y2
4Y2
TTL-Compatible Inputs and Outputs
GND
Outputs Drive Parallel 50-Ω Terminated
Transmission Lines
V
V
CC
CC
GND
1Y3
4Y1
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
GND
GND
V
CC
Distributed V
Switching Noise
and Ground Pins Reduce
CC
GND
GND
2Y1
V
CC
3Y3
Packaged in 56-Pin Ceramic Flat Package
GND
V
V
CC
CC
description
GND
2Y2
3Y2
GND
The SN54CDC586 is
a high-performance,
V
V
CC
CC
low-skew, low-jitter clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the clock output signals to
the clock input (CLKIN) signal. It is specifically
designed for use with popular microprocessors
operating at speeds from 50 MHz to 100 MHz, or
down to 25 MHz on outputs configured as
half-frequency outputs. The SN54CDC586
GND
2Y3
3Y1
GND
GND
NC
V
CC
NC
NC – No internal connection
operates at 3.3-V V
properly terminated 50- transmission line.
and is designed to drive a
CC
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of
the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input
andtheoutputs. TheoutputusedasthefeedbackpinissynchronizedtothesamefrequencyastheCLKINinput.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are
adjusted to 50%, independent of the duty cycle at CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
description (continued)
Output-enable(OE)isprovidedforoutputcontrol. WhenOEishigh, theoutputsareinthehigh-impedancestate.
When OE is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs
operating at half frequency. TEST is used for factory testing of the device and can be used to bypass the PLL.
TEST should be strapped to GND for normal operation.
UnlikemanyproductscontainingPLLs, theSN54CDC586doesnotrequireexternalRCnetworks. Theloopfilter
for the PLL is included on chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the SN54CDC586 requires a stabilization time to achieve phase lock of
thefeedbacksignaltothereferencesignal. Thisstabilizationtimeisrequired, followingpowerupandapplication
of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or
feedbacksignals. Suchchangesoccuruponchangeoftheselectinputs, enablingofthePLLviaTEST, andupon
enable of all outputs via OE.
The SN54CDC586 is characterized for operation over the full military temperature range of –55°C to 125°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) used in the SN54CDC586 PLL has a frequency range of 100 MHz to
200 MHz, twice the operating frequency range of the SN54CDC586 outputs. The output of the VCO is divided
by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO
frequency. SEL0 and SEL1 select which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency and phase of this output match that of CLKIN. In the case in which a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at either the same
or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at twice or the
same frequency as the CLKIN frequency.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
output configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at one-half the CLKIN frequency, while outputs configured as 1x outputs
operate at the same frequency as CLKIN.
Table 1. Output Configuration A
INPUTS
OUTPUTS
1/2X
1X
SEL1 SEL0
FREQUENCY FREQUENCY
L
L
L
H
L
None
1Yn
All
2Yn, 3Yn, 4Yn
3Yn, 4Yn
4Yn
H
H
1Yn, 2Yn
1Yn, 2Yn, 3Yn
H
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B
INPUTS
OUTPUTS
1X
2X
SEL1 SEL0
FREQUENCY FREQUENCY
L
L
L
H
L
All
1Yn
None
2Yn, 3Yn, 4Yn
3Yn, 4Yn
H
1Yn, 2Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
functional block diagram
52
OE
50
CLR
4
FBIN
CLR
2
Phase-Lock Loop
2
55
51
CLKIN
TEST
One of Three Identical
Outputs – 1Yn
6
7
SEL0
SEL1
Select
Logic
10, 13, 16
1Y1–1Y3
One of Three Identical
Outputs – 2Yn
20, 23, 26
2Y1–2Y3
One of Three Identical
Outputs – 3Yn
32, 35, 38
3Y1–3Y3
One of Three Identical
Outputs – 4Yn
42, 45, 48
4Y1–4Y3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Clock input. CLKIN is the clock signal distributed by the SN54CDC586 clock-driver circuit. CLKIN provides
the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed
frequencyandfixedphaseforthePLLtoobtainphaselock. OncethecircuitispoweredupandavalidCLKIN
signalis applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference
signal.
CLKIN
55
I
Clear. CLR resets the VCO/4 reference frequency. CLR is negative-edge triggered and should be strapped
CLR
50
4
I
I
to GND or V
for normal operation.
CC
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
the 12 clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to
obtain zero phase delay between FBIN and CLKIN.
FBIN
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly
from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is
required before the PLL obtains phase lock.
OE
52
I
Output configuration select. SEL0 and SEL1 select the output configuration for each output bank
(e.g., 1×, 1/2×, or 2×). (see Tables 1 and 2).
SEL1, SEL0
TEST
7, 6
51
I
I
TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs
operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be strapped to GND for normal operation.
Output ports. These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the
frequency of the VCO. The relationship between the CLKIN frequency and the output frequency is
dependent on SEL1 and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of
the Y-output signals is nominally 50%, independent of the duty cycle of CLKIN.
1Y1–1Y3
2Y1–2Y3
3Y1–3Y3
10, 13, 16
20, 23, 26
32, 35, 38
O
O
Output ports. 4Y1–4Y3 transmit one-half the frequency of the VCO regardless of the state of SEL1 and
SEL0. The relationship between the CLKIN frequency and the output frequency is dependent on the
frequency of the output being fed back to FBIN. The duty cycle of the Y-output signals is nominally 50%,
independent of the duty cycle of CLKIN.
4Y1–4Y3
42, 45, 48
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state,
V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
recommended operating conditions (see Note 2)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
5.5
–32
32
V
IL
0
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
T
A
–55
125
NOTE 2: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
UNIT
V
MIN
MAX
V
V
V
V
V
= 3 V,
I = –18 mA
–1.2
IK
CC
CC
CC
I
†
= MIN to MAX ,
= 3 V,
I
I
I
I
= –100 µA
= – 32 mA
= 100 µA
= 32 mA
V
–0.2
2
OH
OH
OL
OL
CC
V
OH
0.2
0.5
±10
±1
10
–10
1
V
OL
V
CC
= 3 V
V
†
V
CC
V
CC
V
CC
V
CC
= 0 or MAX ,
V = 3.6 V
I
I
I
µA
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = V
or GND
CC
I
I
I
V
= 3 V
= 0
µA
µA
OZH
O
O
V
OZL
Outputs high
Outputs low
V
= 3.6 V, I = 0,
O
CC
I
1
mA
CC
V = V
I
or GND
CC
Outputs disabled
1
C
C
V = V
or GND
4
pF
pF
i
I
CC
V
O
= V or GND
CC
8
o
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
50
UNIT
VCO is operating at four times the CLKIN frequency
VCO is operating at double the CLKIN frequency
f
Clock frequency
MHz
clock
50
100
60%
50
Input clock duty cycle
40%
After SEL1, SEL0
After OE↓
50
†
Stabilization time
µs
After power up
After CLKIN
50
50
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF, unless otherwise noted (see Note 3 and Figures 1 through 3)
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
f
100
42%
–900
MHz
max
Duty cycle
Y
Y
Y
58%
200
200
0.75
1.1
‡
t
CLKIN↑
CLKIN↑
ps
ps
ns
ns
ns
ns
phase error
*
Jitter
t
(pk-pk)
‡
sk(o)
‡*
t
t
t
sk(pr)
1.4
r
f
1.4
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡
Thepropagationdelay,t
are valid only for equal loading of all outputs.
,isdependentonthefeedbackpathfromanyoutputtoFBIN.Thet
,t
,andt
specifications
sk(pr)
phaseerror phaseerror sk(o)
NOTE 3: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
I
1.5 V
1.5 V
OL
t
phase error
V
V
OH
2 V
0.8 V
2 V
Output
1.5 V
0.8 V
Output
Under Test
OL
V
TH
t
r
t
f
C
L
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
I
OH
PARAMETER
I
I
V
TH
C (typical)
L
OL
OH
t
32 mA
16 mA
32 mA
16 mA
1.5 V
1.5 V
20 pF
phase error
t , t
20 pF
r
f
LOAD CIRCUIT
NOTES: A.
B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
CLKIN
t
t
phase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
phase error 2
t
t
phase error 3
t
t
phase error 4
phase error 7
Outputs
Operating
at CLKIN
t
t
phase error 5
phase error 8
Frequency
t
phase error 6
phase error 9
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, . . . 6)
(n = 7, 8, 9)
phase error n
phase error n
B. Process skew, t , is calculated as the greater of:
sk(pr)
– The difference between the maximum and minimum t
devices under identical operating conditions.
(n = 1, 2, . . . 6) across multiple
phase error n
– The difference between the maximum and minimum t
under identical operating conditions.
(n = 7, 8, 9) across multiple devices
phase error n
Figure 2. Waveforms for Calculation of t
sk(o)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311 – FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
CLKIN
t
phase error 10
Outputs
Operating
at CLKIN
Frequency
t
phase error 11
phase error 12
t
t
phase error 13
Outputs
Operating
at 2X CLKIN
Frequency
t
phase error 14
phase error 15
t
NOTES: A. Output skew, t
, is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
(n = 10, 11, . . . 15)
phase error n
B. Process skew, t , is calculated as the greater of:
sk(pr)
–Thedifferencebetweenthemaximumandminimumt
under identical operating conditions.
(n=10,11, . . . 15)acrossmultipledevices
phaseerrorn
Figure 3. Waveforms for Calculation of t
and t
sk(pr)
sk(o)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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