SNJ54CDC341J [TI]
1-Line To 8-Line Clock Driver 20-CDIP -55 to 125;
| 型号： | SNJ54CDC341J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-Line To 8-Line Clock Driver 20-CDIP -55 to 125 驱动 CD 信息通信管理 逻辑集成电路 |
| 文件： | 总10页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
J OR W PACKAGE
(TOP VIEW)
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
V
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
CC
TTL-Compatible Inputs and Outputs
1G
2G
A
P0
P1
1Y1
1Y2
GND
1Y3
1Y4
GND
Distributes One Clock Input to Eight
Outputs
Distributed V
Switching Noise
and Ground Pins Reduce
CC
V
CC
2Y4
High-Drive Outputs (–48-mA I
,
OH
13 2Y1
12 2Y2
11 GND
48-mA I
)
OL
2Y3
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
GND 10
Package Options Include Ceramic
Flatpacks (W), Ceramic Chip Carriers (FK),
and Ceramic (J) 300-mil DIPS
FK PACKAGE
(TOP VIEW)
description
3
2 1 20 19
The SN54CDC341 is a high-performance clock-
driver circuit that distributes one (A) input signal to
eight (Y) outputs with minimum skew for clock
distribution. Through the use of the control pins
(1G and 2G), the outputs can be placed in a low
state regardless of the A input.
A
P0
P1
1Y2
GND
1Y3
1Y4
GND
4
5
6
7
8
18
17
16
15
14
V
CC
2Y4
Thepropagationdelaysareadjustedatthefactory
using the P0 and P1 pins. These pins are not
intendedforcustomeruseandshouldbestrapped
to GND.
9 10 11 12 13
The SN54CDC341 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
OUTPUTS
1G
X
2G
X
A
L
1Y1–1Y4 2Y1–2Y4
L
L
L
L
L
L
H
H
H
H
L
H
L
L
H
L
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
†
logic symbol
2
1G
G1
G2
3
2G
19
18
16
15
1
1
1
1
1Y1
1Y2
1Y3
1Y4
4
A
13
12
9
2
2
2
2
2Y1
2Y2
2Y3
2Y4
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
2
19
1G
1Y1
1Y2
1Y3
1Y4
3
18
16
15
2G
4
A
13
12
9
2Y1
2Y2
2Y3
2Y4
8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
IK
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
CC
V
I
I
High-level output current
Low-level output current
–48
48
mA
mA
OH
OL
I
One output bank loaded
Both output banks loaded
33
f
Input clock frequency
MHz
clock
25
T
A
Operating free-air temperature
–55
125
°C
NOTE 2: Unused pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
V
IK
I
I
I
I
I
= – 3 mA
= – 3 mA
= – 48 mA
= 48 mA
2.5
3
OH
OH
OH
OL
V
OH
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
2
0.5
V
OL
I
I
V = V
or GND
±1
µA
mA
I
I
CC
= 2.5 V
O
‡
V
–50 –200
O
Outputs high
Outputs low
3.5
33
V
= 5.5 V,
I
O
= 0,
CC
I
mA
pF
CC
V = V
I
or GND
CC
C
V = 2.5 V or 0.5 V
I
i
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
switching characteristics, C = 50 pF (see Figures 1 and 2)
L
V
T
= 5 V,
= 25°C
V
= 4.5 V to 5.5 V,
CC
A
CC
T = –55°C to 125°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
PACKAGE
UNIT
MIN
2.3
3.6
1.6
2.3
TYP MAX
6.7
MIN
1.8
MAX
7
t
t
t
t
PLH
PHL
PLH
PHL
A
Y
Y
All
All
ns
ns
6.3
3.3
1.3
1.8
7
4.1
4.7
4.9
1.9
1.9
0.8
0.9
1.2
0.7
1.7
1.7
2.1
1
G
4.4
J
W
FK
J
1.8
A
G
A
Y
Y
Y
0.7
ns
ns
ns
0.6
t
sk(o)
0.9
W
FK
J
0.5
0.6
1.7
W
FK
J
1.4
1.7
t
t
sk(p)
1
G
Y
Y
W
FK
0.6
1.3
1.8
1.2
ns
ns
1.3
†
A or G
1.2
sk(pr)
†
tsk
is guaranteed across the full voltage and temperature range but is measured only at 25C, V
= 5 V, using the A inputs.
CC
(pr)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
t
t
PHL
PLH
V
V
OH
2 V
1.5 V
0.8 V
1.5 V
0.8 V
Output
OL
t
r
t
f
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
A
1G
2G
1Yn
t
t
PHL1
PLH1
2Yn
t
t
PHL2
PLH2
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2)
(n = 1, 2)
PLHn
PHLn
B. Pulse skew, t
, is calculated as the greater of | t
sk(p)
– t
| (n = 1, 2).
PLHn PHLn
, is calculated as the greater of:
C. Process skew, t
sk(pr)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2) across multiple devices under identical operating conditions
(n = 1, 2) across multiple devices under identical operating conditions
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
, t
, t
sk(o) sk(p) sk(pr)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
C
0.755
(19,18)
0.755
(19,18)
0.930
(23,62)
0.280
(7,11)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
MECHANICAL INFORMATION
W (R-GDFP-F20)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.300 (7,62)
0.245 (6,22)
0.006 (0,15)
0.004 (0,10)
0.100 (2,54)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.320 (8,13)
0.265 (6,73)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
20
0.050 (1,27)
0.540 (13,72)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
10
11
1.040 (26,42)
0.745 (18,92)
4040180-4/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL-STD-1835 GDFP2-F20
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
SNJ54CDC341FK
SNJ54CDC341J
SNJ54CDC341W
OBSOLETE
OBSOLETE
OBSOLETE
FK
J
20
20
20
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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