SNJ54BCT8240AJT [TI]
SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS; 八进制反相缓冲器扫描测试设备
| 型号： | SNJ54BCT8240AJT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS |
| 文件： | 总26页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
SN54BCT8240A . . . JT PACKAGE
SN74BCT8240A . . . DW OR NT PACKAGE
(TOP VIEW)
Members of the Texas Instruments
SCOPE Family of Testability Products
Octal Test-Integrated Circuits
1OE
1Y1
1Y2
1Y3
1Y4
GND
2Y1
2Y2
2Y3
2OE
1A1
1A2
1A3
1A4
2A1
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
Functionally Equivalent to ’F240 and
’BCT240 in the Normal-Function Mode
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Test Operation Synchronous to Test
Access Port (TAP)
V
CC
2A2
2A3
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V) on TMS Pin
2Y4 10
TDO
TMS
15 2A4
TDI
TCK
11
12
14
13
SCOPE Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
SN54BCT8240A . . . FK PACKAGE
(TOP VIEW)
– Sample Inputs/Toggle Outputs
4
3
2
1
28 27 26
25
5
6
7
8
9
1A2
1A1
2OE
NC
1OE
1Y1
1Y2
2A4
TDI
TCK
Package Options Include Plastic
24
23
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)
22 NC
21 TMS
20 TDO
19 2Y4
10
11
description
12 13 14 15 16 17 18
The ’BCT8240A scan test devices with octal
buffers are members of the Texas Instruments
SCOPE testability integrated-circuit family. This
family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of
complex circuit-board assemblies. Scan access
to the test circuitry is accomplished via the 4-wire
test access port (TAP) interface.
NC – No internal connection
In the normal mode, these devices are functionally equivalent to the ’F240 and ’BCT240 octal buffers. The test
circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals
or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the
functional operation of the SCOPE octal buffers.
In the test mode, the normal operation of the SCOPE octal buffers is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations, as described in IEEE Standard 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
description (continued)
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output
(TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8240A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74BCT8240A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(normal mode, each buffer)
INPUTS
OUTPUT
Y
OE
A
X
L
H
L
L
Z
H
L
H
†
logic symbol
Φ
SCAN
’BCT8240A
14
12
13
TDI
TMS
TCK
TDI
11
TMS
TDO
TDO
TCK-IN
TCK-OUT
EN1
EN2
1
1OE
2OE
24
23
22
21
20
19
17
16
15
2
3
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1
2
4
5
7
8
9
10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
functional block diagram
Boundary-Scan Register
V
CC
1
1OE
1A1
V
CC
2
23
1Y1
One of Four Channels
V
V
CC
24
19
2OE
2A1
CC
7
2Y1
One of Four Channels
Bypass Register
Boundary-Control
Register
V
CC
V
V
CC
11
TDO
14
12
Instruction Register
TDI
CC
TMS
TAP
Controller
V
CC
13
TCK
Pin numbers shown are for the DW, JT, and NT packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
Terminal Functions
TERMINAL
NAME
DESCRIPTION
1A1–1A4,
2A1–2A4
Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.
GND
Ground
Normal-function output-enable inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high
level if left unconnected.
1OE, 2OE
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.
TCK
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.
TDO
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its
TAP-controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test
TMS
resetsignalofIEEEStandard1149.1-1990.Thisisimplementedbyrecognizingathirdlogiclevel,doublehigh(V
),atTMS.
IHH
V
CC
Supply voltage
1Y1–1Y4,
2Y1–2Y4
Normal-function data outputs. See function table for normal-mode logic.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a
2-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
Run-Test/Idle
Select-DR-Scan
TMS = L
Select-IR-Scan
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
TMS = L
Capture-IR
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
Exit1-IR
TMS = H
Exit1-DR
TMS = L
TMS = L
Pause-DR
TMS = H
Pause-IR
TMS = H
Exit2-IR
TMS = L
TMS = L
TMS = L
TMS = L
Exit2-DR
TMS = H
TMS = H
Update-DR
Update-IR
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
state diagram description
TheTAPcontrollerisasynchronousfinitestatemachinethatprovidestestcontrolsignalsthroughoutthedevice.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register may be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuted.
For the ’BCT8240A, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected-data register may capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.
For the ’BCT8240A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
register overview
With the exception of the bypass register, any test register may be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
may be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
itsnormallogicfunction, ortestmode, inwhichthenormallogicfunctionisinhibitedoraltered), thetestoperation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 2 lists the instructions supported by the ’BCT8240A. The even-parity feature specified for SCOPE
devices is not supported in this device. Bit 7 of the instruction opcode is a don’t-care bit. Any instructions that
are defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.
Bit 7
(MSB)
Don’t
Care
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TDI
TDO
Figure 2. Instruction Register Order of Scan
data-register description
boundary-scan register
The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function output pin. The BSR is used 1) to store test
data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output
terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or
externally at the device input terminals.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents
of the BSR are not changed in Test-Logic-Reset.
The BSR order of scan is from TDI through bits 17–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
17
16
––
––
––
––
––
––
1OE
2OE
––
15
14
13
12
11
10
9
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
7
6
5
4
3
2
1
0
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
––
––
––
––
––
8
boundary-control register
The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction
to implement additional test operations not included in the basic SCOPE instruction set. Such operations
include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.
Bit 1
(MSB)
Bit 0
(LSB)
TDI
TDO
Figure 3. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation.
During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in
Figure 4.
TDI
TDO
Bit 0
Figure 4. Bypass Register Order of Scan
instruction-register opcode description
The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of
each instruction.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
Table 2. Instruction-Register Opcodes
†
BINARY CODE
BIT 7 → BIT 0
MSB → LSB
SELECTED DATA
REGISTER
SCOPE OPCODE
DESCRIPTION
MODE
X0000000
X0000001
X0000010
X0000011
X0000100
X0000101
X0000110
X0000111
X0001000
X0001001
X0001010
X0001011
X0001100
X0001101
X0001110
X0001111
All others
EXTEST/INTEST
Boundary scan
Bypass scan
Boundary scan
Bypass
Test
Normal
Normal
Test
‡
BYPASS
SAMPLE/PRELOAD
INTEST/EXTEST
Sample boundary
Boundary scan
Boundary scan
Bypass
Boundary scan
‡
BYPASS
BYPASS
Bypass scan
Normal
Normal
Modified test
Test
‡
Bypass scan
Bypass
HIGHZ (TRIBYP)
CLAMP (SETBYP)
Control boundary to high impedance
Control boundary to 1/0
Bypass scan
Bypass
Bypass
‡
BYPASS
Bypass
Normal
Test
RUNT
Boundary run test
Bypass
READBN
READBT
CELLTST
TOPHIP
Boundary read
Boundary scan
Boundary scan
Boundary scan
Bypass
Normal
Test
Boundary read
Boundary self test
Boundary toggle outputs
Boundary-control register scan
Boundary-control register scan
Bypass scan
Normal
Test
SCANCN
SCANCT
BYPASS
Boundary control
Boundary control
Bypass
Normal
Test
Normal
†
‡
Bit 7 is a don’t-care bit; X = don’t care.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’BCT8240A.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output terminals. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT8240A, SN74BCT8240A
SCAN TEST DEVICES
WITH OCTAL INVERTING BUFFERS
SCBS067E – FEBRUARY 1990 – REVISED DECEMBER 1996
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device output terminals are placed in the high-impedance state,
the device input terminals remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output terminals. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output
terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and
is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured
in the input BSCs. The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
11
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boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 1–0, as shown in Table 3. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 3. Boundary-Control Register Opcodes
BINARY CODE
BIT 1 → BIT 0
MSB → LSB
DESCRIPTION
00
01
10
11
Sample inputs/toggle outputs (TOPSIP)
Pseudo-random pattern generation/16-bit mode (PRPG)
Parallel-signature analysis/16-bit mode (PSA)
Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)
It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample,
toggle, PSA, or PRPG algorithms, the output-enable BSCs (bits 17–16 of the BSR) do control the drive state
(active or high impedance) of the selected device output terminals.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each
rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs
of the normal on-chip logic. Data in the shift-register elements of the output BSCs is toggled on each rising edge
of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK
and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK.
This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip
logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are
generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value
of all zeroes will not produce additional patterns.
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
=
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 5. 16-Bit PRPG Configuration
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parallel-signature analysis (PSA)
Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register
elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input
BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register
algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
=
=
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 6. 16-Bit PSA Configuration
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows
the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An
initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes
will not produce additional patterns.
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
=
=
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
Figure 7. 8-Bit PSA/PRPG Configuration
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timing description
Alltestoperationsofthe’BCT8240AaresynchronoustoTCK. DataontheTDI, TMS, andnormal-functioninputs
is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the
falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the
value of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is shown in Figure 8. In this example, the TAP controller begins in the Test-Logic-Reset
state and is advanced through its states, as necessary, to perform one instruction-register scan and one
data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used
to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 details the
operation of the test circuitry during each TCK cycle.
Table 4. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
1
Test-Logic-Reset
2
3
4
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
5
6
Capture-IR
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is seriallyscannedintotheIR.Atthesametime,the8-bitbinaryvalue10000001isseriallyscanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
7–13
Shift-IR
14
15
16
Exit1-IR
Update-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
Select-DR-Scan
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
17
18
Capture-DR
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
21
Shift-DR
Exit1-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
Select-IR-Scan
Test-Logic-Reset
24
25
Test operation completed
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1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TCK
TMS
TDI
TDO
TAP
Controller
State
3-State (TDO) or Don’t Care (TDI)
Figure 8. Timing Example
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : except TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
TMS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 12 V
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Input clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
IK
Current into any output in the low state: SN54BCT8240A (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
SN54BCT8240A (any Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT8240A (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74BCT8240A (any Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DW package . . . . . . . . . . . . . . . . . . 1.7 W
A
NT package . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage rating may be exceeded if the input clamp-current rating is observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
15
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recommended operating conditions
SN54BCT8240A
MIN NOM MAX
SN74BCT8240A
MIN NOM MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Double-high-level input voltage
Low-level input voltage
Input clamp current
IH
TMS
10
12
0.8
–18
–3
10
12
0.8
–18
–3
V
IHH
IL
V
I
IK
mA
TDO
I
High-level output current
mA
OH
OL
Any Y
TDO
–12
20
–15
24
I
Low-level output current
mA
Any Y
48
64
T
A
Operating free-air temperature
–55
125
0
70
°C
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT8240A
SN74BCT8240A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.75 V,
I
I
I
I
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –12 mA
= –15 mA
= –1 mA
= –1 mA
= –3 mA
= 48 mA
= 64 mA
= 20 mA
= 24 mA
2.7
2.4
2
3.4
3.4
3.2
2.7
2.4
3.4
3.4
CC
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
Any Y
V
V
V
V
CC
= 4.5 V
V
OH
2
2.7
2.5
2.4
3.1
3.4
3.4
3.3
V
V
= 4.75 V,
= 4.5 V
2.7
2.5
2.4
3.4
3.4
CC
TDO
CC
3.3
0.38
0.55
0.5
Any Y
V
V
= 4.5 V
= 4.5 V
CC
0.42
0.35
–35
–70
–35
–70
0.55
V
OL
0.3
TDO
CC
0.5
0.1
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V
I
0.1
–100
1
mA
µA
I
V = 2.7 V
I
–1
–30
–1
–35
–70
–35
–70
–1
–30
–1
–100
1
IH
TMS
V = 10 V
I
mA
µA
IHH
IL
V = 0.5 V
I
–200
50
–200
50
Any Y
TDO
I
V
= 5.5 V,
= 5.5 V,
V
= 2.7 V
= 0.5 V
µA
µA
OZH
OZL
CC
CC
O
O
–100
–50
–200
±250
±250
±250
–225
7.5
–100
–50
–200
±250
±250
±250
–225
7.5
Any Y
TDO
I
V
V
–30
–30
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 0 to 2 V,
= 2 V to 0,
= 0,
V
V
= 0.5 V or 2.7 V
= 0.5 V or 2.7 V
µA
µA
µA
mA
OZPU
OZPD
off
O
O
V or V ≤ 4.5 V
I
O
‡
= 5.5 V,
V
O
= 0
–100
–100
OS
Outputs high
Outputs low
3.5
35
1.5
10
18
3.5
35
1.5
10
18
I
V
CC
= 5.5 V,
Outputs open
52
52
mA
CC
Outputs disabled
3.5
3.5
C
C
V
V
= 5 V,
= 5 V,
V = 2.5 V or 0.5 V
I
pF
pF
i
CC
V
O
= 2.5 V or 0.5 V
o
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
17
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 9)
V
T
= 5 V,
= 25°C
CC
A
SN54BCT8240A SN74BCT8240A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
TCK
20
20
20
MHz
ns
clock
TCK high or low
TMS double high
Any A before TCK↑
Any OE before TCK↑
TDI before TCK↑
TMS before TCK↑
Any A after TCK↑
Any OE after TCK↑
TDI after TCK↑
25
50*
6
25
50*
6
25
50
6
w
6
6
6
t
su
Setup time
ns
6
6
6
12
4.5
4.5
4.5
0
12
4.5
4.5
4.5
0
12
4.5
4.5
4.5
0
t
t
Hold time
ns
ns
h
TMS after TCK↑
Power up to TCK↑
Delay time
100*
100*
100
d
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
18
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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 9)
V
T
= 5 V,
= 25°C
CC
A
SN54BCT8240A SN74BCT8240A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2.5
2.5
3
TYP
5.7
5.2
6
MAX
MIN
2.5
2.5
3
MAX
10
9
MIN
2.5
2.5
3
MAX
9
t
t
t
t
t
t
7.5
7
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
8
8
10
12
10
10
9.5
11
9
OE
OE
3.5
2.5
2.5
7
9
3.5
2.5
2.5
3.5
2.5
2.5
6
8
5.5
8
9
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 9)
V
T
= 5 V,
= 25°C
CC
A
SN54BCT8240A SN74BCT8240A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
20
6
TYP
MAX
MIN
20
6
MAX
MIN
20
6
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
13
12.5
7.6
8
15.5
15.5
10.5
10.5
20
21.5
21.5
14
20
20
TCK↓
Y
TDO
Y
6
6
6
3.5
3.5
7.5
7.5
6.5
7
3.5
3.5
7.5
7.5
6.5
7
3.5
3.5
7.5
7.5
6.5
7
13
TCK↓
ns
ns
ns
ns
ns
ns
ns
ns
13
12
16.5
17
28
24
TCK↑
TCK↓
21
29
25
14
17
24
21
Y
15
20
26
23
3.5
4
7.6
8.5
18
10.5
11
3.5
4
11.5
13.5
30
3.5
4
11
TCK↓
TDO
Y
12.5
27
8
22
8
8
TCK↑
TCK↓
TCK↓
8
19
25
8
32
8
29
6
14
18
6
24
6
22
Y
6
14
17
6
23
6
21
3
8
11.5
10
3
13
3
12.5
12
TDO
Y
3
7.5
18.5
18.5
3
13
3
8
22
8
31
8
27
TCK↑
8
22
8
31
8
27
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PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
S1
PZL PLZ
Open
(all others)
R1
From Output
Under Test
Point
Test
Point
From Output
Under Test
Test
C
L
R1
C
L
R2
(see Note A)
(see Note A)
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3 V
0 V
High-Level
Pulse
3 V
1.5 V
1.5 V
Timing Input
1.5 V
0 V
3 V
0 V
t
w
t
h
t
su
3 V
0 V
Low-Level
Pulse
Data Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
Output
Control
(low-level enable)
3 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
PHL
t
t
PZL
t
t
PLZ
t
PLH
3.5 V
V
OH
1.5 V
In-Phase
Output
Waveform 1
(see Note B)
1.5 V
1.5 V
1.5 V
t
V
OL
V
OL
0.3 V
t
PHZ
PLH
t
PHL
PZH
V
OH
V
OH
Waveform 2
(see Note B)
Out-of-Phase
Output
1.5 V
1.5 V
0.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 9. Load Circuits and Voltage Waveforms
20
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SOIC
Drawing
5962-9174601Q3A
5962-9174601QLA
SN74BCT8240ADW
ACTIVE
ACTIVE
ACTIVE
FK
28
24
24
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
JT
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74BCT8240ADWE4
SN74BCT8240ADWR
SN74BCT8240ADWRE4
SN74BCT8240ANT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
NT
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74BCT8240ANTE4
NT
15
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SNJ54BCT8240AFK
SNJ54BCT8240AJT
ACTIVE
ACTIVE
LCCC
CDIP
FK
JT
28
24
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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