SNJ54BCT652FK [TI]
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 八路总线收发器和寄存器具有三态输出
| 型号： | SNJ54BCT652FK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总16页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
SN54BCT652 . . . JT OR W PACKAGE
SN74BCT652 . . . DW OR NT PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
CLKAB
SAB
OEAB
A1
V
CC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
CLKBA
SBA
OEBA
B1
B2
B3
• Independent Registers and Enables for
A and B Buses
A2
A3
A4
A5
• Multiplexed Real-Time and Stored Data
• Power-Up High-Impedance Mode
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and Flatpacks (W), and
Standard Plastic and Ceramic 300-mil DIPs
(JT, NT)
B4
B5
A6
A7 10
15 B6
A8
GND
B7
B8
11
12
14
13
SN54BCT652 . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
4
3
2 1 28 27 26
25
24
23
22
21
20
19
5
6
7
8
9
A1
A2
A3
NC
A4
OEBA
B1
B2
NC
B3
B4
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-managementfunctionsthatcanbeperformed
with the ′BCT652.
A5 10
A6 11
B5
12 13 14 15 16 17 18
NC – No internal connection
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Therefore,
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at
its last state.
The SN54BCT652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74BCT652 is characterized for operation from 0°C to 70°C.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
3
21
OEAB OEBA
L
1
23
2
22
SBA
L
3
21
1
23
2
22
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
3
21
1
23
2
22
SBA
X
3
21
1
23
2
22
SBA
H
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
L
L
L
X
L
L
L
H
X
H
↑
X
X
H
X
H
H
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DW, JT, NT, and W packages.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
FUNCTION TABLE
DATA I/O
†
INPUTS
CLKAB
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1 THRU A8
Input
B1 THRU B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.
§
logic symbol
21
OEBA
EN1 [BA]
EN2 [AB]
3
OEAB
CLKBA
SBA
23
22
1
C4
G5
CLKAB
SAB
C6
2
G7
20
4D
2
B1
5
5
≥1
4
A1
1
1
6D
7
7
≥1
1
5
19
18
17
16
15
14
13
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
6
7
8
9
10
11
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, NT, and W packages.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
logic diagram (positive logic)
21
OEBA
3
OEAB
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight
Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
CC
Input voltage range: Control inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
O
CC
Current into any output in the low state: SN54BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range: SN54BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74BCT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
recommended operating conditions
SN54BCT652
MIN NOM MAX
SN74BCT652
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–12
48
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT652
SN74BCT652
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
= 4.5 V
I = –18 mA
–1.2
–1.2
V
IK
CC
I
I
I
I
I
I
= –3 mA
= –12 mA
= –15 mA
= 48 mA
= 64 mA
2.4
2
3.3
3.2
2.4
2
3.3
3.1
OH
OH
OH
OL
OL
V
OH
CC
0.38
0.55
V
OL
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
0.42
0.55
1
A or B port
1
1
I
I
I
V = 5.5 V
I
mA
µA
mA
I
Control inputs
A or B port
1
70
70
‡
V = 2.7 V
I
IH
Control inputs
A or B port
20
20
–0.7
–0.7
–0.7
–0.7
–225
69
‡
V = 0.5 V
I
IL
Control inputs
§
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5 V,
V = 0
O
–100
–225 –100
mA
mA
mA
mA
pF
OS
A or B port
V = 0
I
43
6
69
10
17
43
6
CCL
CCH
CCZ
A or B port
A or B port
Control inputs
A or B port
V = 4.5 V
I
10
V = 0
I
10
6
10
6
17
C
C
V = 2.5 V or 0.5 V
I
i
= 5 V,
V
O
= 2.5 V or 0.5 V
14
14
pF
io
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
= 5 V, T = 25°C.
A
CC
IH
IL
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
SN54BCT652 SN7BCTT652
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
77
77
77
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
6.5
5
7
6.5
5
w
6
ns
su
h
1
1
1
ns
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Note 2)
L
V
T
= 5 V,
= 25°C
CC
A
SN54BCT652 SN74BCT652
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
77
TYP
MIN
MIN
77
MAX
MIN
77
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
2.6
2.8
2.6
2.8
1.7
2.4
1.7
2.4
3.5
2.4
3
6.9
6.8
6.9
6.8
5.8
6.5
5.8
6.5
8.8
5.9
7.6
8.3
8.8
5.9
7.6
8.3
7.2
8.1
6.7
6.3
5.4
6.2
8.2
7.2
8.9
8.8
8.9
8.8
7.5
8.2
7.5
8.2
10.8
7.7
9.7
10.4
10.8
7.7
9.7
10.4
8.9
10.1
8.6
8.4
7.1
8.1
10
2.6
2.8
2.6
2.8
1.7
2.4
1.7
2.4
3.5
2.4
3
11.6
10.7
11.6
10.7
10.3
11
2.6
2.8
2.6
2.8
1.7
2.4
1.7
2.4
3.5
2.4
3
10.5
9.9
CLKBA
A
B
B
A
A
A
B
B
A
A
B
B
10.5
9.9
CLKAB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.9
A
B
9.8
10.3
11
8.9
9.8
†
SBA
14.2
9.1
13.1
8.5
(with B high)
†
SBA
12.4
12.9
14.2
9.1
11.3
12.5
13.1
8.5
(with B low)
3.8
3.5
2.4
3
3.8
3.5
2.4
3
3.8
3.5
2.4
3
†
SAB
(with A high)
†
SAB
12.4
12.9
11.2
12.6
10.9
10.5
9
11.3
12.5
10.6
12
(with A low)
3.8
2.5
3.2
2.8
2.4
1.5
2.3
3.5
2.8
3.8
2.5
3.2
2.8
2.4
1.5
2.3
3.5
2.8
3.8
2.5
3.2
2.8
2.4
1.5
2.3
3.5
2.8
OEBA
10
OEBA
OEAB
OEAB
9.5
8.1
10.3
12.2
12
9.3
11.6
11.3
9.5
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9155301M3A
5962-9155301MKA
5962-9155301MLA
SN74BCT652DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
28
24
24
24
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
JT
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74BCT652DWE4
SN74BCT652DWG4
SN74BCT652DWR
SN74BCT652DWRE4
SN74BCT652DWRG4
SN74BCT652NT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
NT
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
SN74BCT652NTE4
NT
15
Pb-Free
(RoHS)
SNJ54BCT652FK
SNJ54BCT652JT
SNJ54BCT652W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JT
W
28
24
24
1
1
1
TBD
TBD
TBD
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74BCT652DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN74BCT652DWR
2000
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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