SNJ54AC533W [TI]
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 八路透明D类锁存器具有三态输出
| 型号： | SNJ54AC533W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ
ꢁ
ꢎ
ꢂ
ꢁ
ꢒ
ꢃ
ꢊ
ꢄ
ꢏ
ꢆ
ꢅ
ꢐ
ꢂ
ꢊ
ꢊ
ꢆ
ꢑ
ꢄ
ꢆ
ꢍ
ꢊ
ꢇ
ꢀ
ꢎ
ꢎ
ꢁ
ꢋ
ꢉ
ꢈ
ꢄ
ꢕ
ꢃ
ꢊ
ꢊ
ꢄ
ꢅ
ꢍ
ꢅ
ꢒ
ꢕ
ꢂ
ꢎ
ꢊ
ꢆ
ꢆ
ꢀ
ꢀ
ꢉ
ꢅ
ꢊ
ꢄ
ꢋ
ꢊ
ꢌ
ꢄ
ꢁ
ꢀ
ꢍ
ꢄ
ꢌ
ꢓ
ꢔꢊ
ꢐ
ꢀ
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
SN54AC533 . . . J OR W PACKAGE
SN74AC533 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
2-V to 6-V V
Operation
CC
Inputs Accept Voltages to 6 V
Max t of 10.5 ns at 5 V
pd
3-State Inverting Outputs Drive Bus Lines
Directly
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
D
Full Parallel Access for Loading
description/ordering information
The ’AC533 devices are octal transparent D-type
latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
GND
SN54AC533 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
3
2 1 20 19
18
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
15
14
9 10 11 12 13
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74AC533N
SN74AC533N
Tube
SN74AC533DW
SN74AC533DWR
SN74AC533NSR
SN74AC533DBR
SN74AC533PW
SN74AC533PWR
SNJ54AC533J
SOIC − DW
AC533
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
AC533
AC533
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
AC533
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AC533J
SNJ54AC533W
SNJ54AC533FK
Tube
SNJ54AC533W
SNJ54AC533FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢕ ꢁ ꢋꢎꢀꢀ ꢉ ꢊꢒ ꢎꢌꢓ ꢔꢀ ꢎ ꢁ ꢉꢊꢎꢏ ꢖꢗ ꢘꢙ ꢚꢛꢜ ꢝꢞꢟ ꢠꢖ ꢜꢛ ꢠꢖꢡ ꢘꢠꢙ ꢍꢌ ꢉ ꢏ ꢕ ꢅꢊ ꢔꢉ ꢁ
ꢧ
ꢏ
ꢄ
ꢊ
ꢄ
ꢘ
ꢠ
ꢢ
ꢛ
ꢣ
ꢞ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢜ
ꢝ
ꢣ
ꢣ
ꢟ
ꢠ
ꢖ
ꢡ
ꢙ
ꢛ
ꢢ
ꢤ
ꢝ
ꢥ
ꢦ
ꢘ
ꢜ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢚ
ꢡ
ꢖ
ꢟ
ꢍ
ꢣ
ꢛ
ꢚ
ꢝ
ꢜ
ꢖ
ꢙ
ꢜ
ꢛ
ꢠ
ꢢ
ꢛ
ꢣ
ꢞ
ꢖ
ꢛ
ꢙ
ꢤ
ꢟ
ꢜ
ꢘ
ꢢ
ꢘ
ꢜ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢙ
ꢤ
ꢟ
ꢣ
ꢖ
ꢗ
ꢟ
ꢖ
ꢟ
ꢣ
ꢞ
ꢙ
ꢛ
ꢢ
ꢊ
ꢟ
ꢨ
ꢡ
ꢙ
ꢔ
ꢠ
ꢙ
ꢖ
ꢣ
ꢝ
ꢞ
ꢟ
ꢠ
ꢖ
ꢙ
ꢙ
ꢖ
ꢡ
ꢠ
ꢚ
ꢡ
ꢣ
ꢚ
ꢩ
ꢡ
ꢣ
ꢣ
ꢡ
ꢠ
ꢖ
ꢪ
ꢧ
ꢍ
ꢣ
ꢛ
ꢚ
ꢝ
ꢜ
ꢖ
ꢘ
ꢤꢡ ꢣ ꢡ ꢞ ꢟ ꢖ ꢟ ꢣ ꢙ ꢧ
ꢛ
ꢠ
ꢤ
ꢣ
ꢛ
ꢜ
ꢟ
ꢙ
ꢙ
ꢘ
ꢠ
ꢫ
ꢚ
ꢛ
ꢟ
ꢙ
ꢠ
ꢛ
ꢖ
ꢠ
ꢟ
ꢜ
ꢟ
ꢙ
ꢙ
ꢡ
ꢣ
ꢘ
ꢦ
ꢪ
ꢘ
ꢠ
ꢜ
ꢦ
ꢝ
ꢚ
ꢟ
ꢖ
ꢟ
ꢙ
ꢖ
ꢘ
ꢠ
ꢫ
ꢛ
ꢢ
ꢡ
ꢦ
ꢦ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢆꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢆ
ꢉꢅ ꢊꢄ ꢋ ꢊ ꢌ ꢄꢁ ꢀꢍꢄꢌ ꢎꢁ ꢊ ꢏꢐꢊ ꢑ ꢍꢎ ꢋꢄꢊꢅ ꢒꢎꢀ
ꢓꢔ ꢊ ꢒ ꢆ ꢐꢀꢊꢄꢊ ꢎ ꢉꢕꢊ ꢍ ꢕꢊꢀ
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
LE
H
H
L
D
H
L
L
L
L
H
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1Q
3
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢎ
ꢂ
ꢁ
ꢒ
ꢃ
ꢊ
ꢄ
ꢏ
ꢆ
ꢅ
ꢐ
ꢂ
ꢊ
ꢊ
ꢆ
ꢑ
ꢄ
ꢆ
ꢍ
ꢊ
ꢇ
ꢀ
ꢎ
ꢎ
ꢁ
ꢋ
ꢉ
ꢈ
ꢄ
ꢕ
ꢃ
ꢊ
ꢊ
ꢄ
ꢅ
ꢍ
ꢅ
ꢒ
ꢕ
ꢂ
ꢎ
ꢊ
ꢆ
ꢆ
ꢀ
ꢀ
ꢉ
ꢅ
ꢊ
ꢄ
ꢋ
ꢊ
ꢌ
ꢄ
ꢁ
ꢀ
ꢍ
ꢄꢌ
ꢓ
ꢔꢊ
ꢐꢀ
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC533
SN74AC533
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
High-level input voltage
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
8
8
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC533
SN74AC533
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
4.4
4.4
I
= −50 µA
OH
5.4
5.4
V
OH
V
I
I
= −12 mA
= −24 mA
2.56
3.86
4.86
2.46
3.76
4.76
OH
4.5 V
5.5 V
3 V
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
0.5
5
0.1
0.1
0.1
0.44
0.44
0.44
2.5
1
4.5 V
5.5 V
3 V
I
= 50 µA
OL
0.1
V
OL
V
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.25
0.1
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
OL
I
I
I
V
= V
or GND
µA
µA
µA
pF
OZ
O CC
V = V
or GND
or GND,
or GND
1
I
I
CC
CC
CC
V = V
I = 0
O
4
80
40
CC
I
C
V = V
4.5
i
I
ꢍ
ꢌ
ꢉ
ꢏ
ꢕ
ꢅ
ꢊ
ꢍ
ꢌ
ꢎ
ꢬ
ꢔ
ꢎ
ꢓ
ꢘ
ꢠ
ꢢ
ꢛ
ꢣ
ꢞ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢜ
ꢛ
ꢠ
ꢜ
ꢟ
ꢣ
ꢠ
ꢙ
ꢤ
ꢣ
ꢛ
ꢚ
ꢝ
ꢜ
ꢖ
ꢙ
ꢚꢟ ꢙ ꢘ ꢫꢠ ꢤꢗ ꢡ ꢙ ꢟ ꢛꢢ ꢚꢟ ꢭ ꢟ ꢦꢛ ꢤꢞꢟ ꢠꢖꢧ ꢅ ꢗꢡ ꢣꢡ ꢜꢖ ꢟꢣ ꢘꢙ ꢖꢘ ꢜ ꢚꢡ ꢖꢡ ꢡꢠ ꢚ ꢛꢖ ꢗꢟꢣ
ꢘ
ꢠ
ꢖ
ꢗ
ꢟ
ꢢ
ꢛ
ꢣ
ꢞ
ꢡ
ꢖ
ꢘ
ꢭ
ꢟ
ꢛ
ꢣ
ꢙ
ꢤ
ꢟ
ꢜ
ꢘ
ꢢ
ꢘ
ꢜ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢙ
ꢡ
ꢣ
ꢟ
ꢚ
ꢟ
ꢙ
ꢘ
ꢫ
ꢠ
ꢫ
ꢛ
ꢡ
ꢦ
ꢙ
ꢧ
ꢊ
ꢟ
ꢨ
ꢡ
ꢙ
ꢔ
ꢠ
ꢙ
ꢖ
ꢣ
ꢝ
ꢞ
ꢟ
ꢠ
ꢖ
ꢙ
ꢣ
ꢜ ꢗꢡ ꢠ ꢫꢟ ꢛꢣ ꢚꢘ ꢙ ꢜ ꢛꢠ ꢖꢘ ꢠꢝꢟ ꢖ ꢗꢟ ꢙ ꢟ ꢤꢣ ꢛꢚ ꢝꢜꢖ ꢙ ꢩ ꢘꢖꢗ ꢛꢝꢖ ꢠꢛꢖ ꢘꢜꢟ ꢧ
ꢟ
ꢙ
ꢟ
ꢣ
ꢭ
ꢟ
ꢙ
ꢖ
ꢗ
ꢟ
ꢣ
ꢘ
ꢫ
ꢗ
ꢖ
ꢖ
ꢛ
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢆꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢆ
ꢉꢅ ꢊꢄ ꢋ ꢊ ꢌ ꢄꢁ ꢀꢍꢄꢌ ꢎꢁ ꢊ ꢏꢐꢊ ꢑ ꢍꢎ ꢋꢄꢊꢅ ꢒꢎꢀ
ꢓꢔ ꢊ ꢒ ꢆ ꢐꢀꢊꢄꢊ ꢎ ꢉꢕꢊ ꢍ ꢕꢊꢀ
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54AC533
SN74AC533
A
UNIT
MIN
6
MAX
MIN
8
MAX
MIN
6.5
6
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
5.5
1.5
7.5
2.5
1
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54AC533
SN74AC533
A
UNIT
MIN
4.5
4
MAX
MIN
6.5
6
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
4.5
1
1.5
2.5
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
SN54AC533
SN74AC533
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
14
MIN
1
MAX
17.5
16
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
16
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
2
13
1
14.5
16.5
14.5
14
2
14.5
13
1
18
LE
OE
OE
ns
2
1
16
2
12.5
12.5
13
1
15.5
15.5
16
ns
2
1
14
2
1
14.5
14.5
ns
2
13
1
16
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
SN54AC533
SN74AC533
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
10
MIN
1
MAX
12.5
12
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
11
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
2
9.5
10.5
10
1
10.5
11.5
11
2
1
13
LE
ns
2
1
13
2
9.5
9.5
10
1
12
10.5
10.5
11
ns
OE
OE
2
1
12
2
1
12.5
12.5
ns
2
10
1
11
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
C
40
pF
pd
L
ꢍ
ꢌ
ꢉ
ꢏ
ꢕ
ꢅ
ꢊ
ꢍ
ꢌ
ꢎ
ꢬ
ꢔ
ꢎ
ꢓ
ꢘ
ꢠ
ꢢ
ꢛ
ꢣ
ꢞ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢜ
ꢛ
ꢠ
ꢜ
ꢟ
ꢣ
ꢠ
ꢙ
ꢤ
ꢣ
ꢛ
ꢚ
ꢝ
ꢜ
ꢖ
ꢙ
ꢚ ꢟ ꢙ ꢘ ꢫ ꢠ ꢤꢗ ꢡ ꢙ ꢟ ꢛꢢ ꢚꢟ ꢭ ꢟ ꢦ ꢛꢤ ꢞꢟ ꢠ ꢖꢧ ꢅ ꢗꢡ ꢣꢡ ꢜꢖ ꢟꢣ ꢘꢙ ꢖꢘ ꢜ ꢚꢡ ꢖꢡ ꢡꢠ ꢚ ꢛꢖ ꢗꢟꢣ
ꢘ
ꢠ
ꢖ
ꢗ
ꢟ
ꢢ
ꢛ
ꢣ
ꢞ
ꢡ
ꢖ
ꢘ
ꢭ
ꢟ
ꢛ
ꢣ
ꢙ
ꢤ
ꢟ
ꢜ
ꢘ
ꢢ
ꢘ
ꢜ
ꢡ
ꢖ
ꢘ
ꢛ
ꢠ
ꢙ
ꢡ
ꢣ
ꢟ
ꢚ
ꢟ
ꢙ
ꢘ
ꢫ
ꢠ
ꢫ
ꢛ
ꢡ
ꢦ
ꢙ
ꢧ
ꢊ
ꢟ
ꢨ
ꢡ
ꢙ
ꢔ
ꢠ
ꢙ
ꢖ
ꢣ
ꢝ
ꢞ
ꢟ
ꢠ
ꢖ
ꢙ
ꢣ
ꢜ ꢗ ꢡ ꢠ ꢫꢟ ꢛꢣ ꢚꢘ ꢙ ꢜ ꢛꢠ ꢖꢘ ꢠꢝ ꢟ ꢖ ꢗꢟ ꢙ ꢟ ꢤꢣ ꢛ ꢚꢝꢜ ꢖꢙ ꢩ ꢘꢖꢗ ꢛꢝꢖ ꢠꢛꢖ ꢘꢜꢟ ꢧ
ꢟ
ꢙ
ꢟ
ꢣ
ꢭ
ꢟ
ꢙ
ꢖ
ꢗ
ꢟ
ꢣ
ꢘ
ꢫ
ꢗ
ꢖ
ꢖ
ꢛ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢎ
ꢂ
ꢁ
ꢒ
ꢃ
ꢊ
ꢄ
ꢏ
ꢆ
ꢅ
ꢐ
ꢂ
ꢊ
ꢊ
ꢆ
ꢑ
ꢄ
ꢆ
ꢍ
ꢊ
ꢇ
ꢀ
ꢎ
ꢎ
ꢁ
ꢋ
ꢉ
ꢈ
ꢄ
ꢕ
ꢃ
ꢊ
ꢊ
ꢄ
ꢅ
ꢍ
ꢅ
ꢒ
ꢕ
ꢂ
ꢎ
ꢊ
ꢆ
ꢆ
ꢀ
ꢀ
ꢉ
ꢅ
ꢊ
ꢄ
ꢋ
ꢊ
ꢌ
ꢄ
ꢁ
ꢀ
ꢍ
ꢄꢌ
ꢓ
ꢔ
ꢊ
ꢐꢀ
SCAS555C − NOVEMBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
500 Ω
Open
From Output
Under Test
TEST
/t
S1
t
Open
PLH PHL
t
/t
2 × V
CC
Open
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
(see Note A)
PHZ PZH
LOAD CIRCUIT
V
CC
50% V
CC
Timing Input
Data Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
50% V
50% V
CC
CC
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
CC
V
CC
50% V
CC
50% V
CC
50% V
50% V
CC
CC
Input
0 V
0 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
PHL
Output
Waveform 1
≈V
CC
V
OH
CC
50% V
CC
50% V
50% V
V
+ 0.3 V
OL
CC
CC
S1 at 2 × V
(see Note B)
CC
In-Phase
Output
V
OL
V
OL
t
t
PZH
PHZ
t
PLH
Output
Waveform 2
S1 at Open
(see Note B)
Out-of-Phase
Output
V
OH
V
OH
V
− 0.3 V
OH
50% V
50% V
50% V
CC
V
CC
≈0 V
OL
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
0.775
0.920
1.060
A MAX
A
(19,69) (19,69) (23,37) (26,92)
16
9
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21,59) (23,88)
MS-100
VARIATION
0.260 (6,60)
0.240 (6,10)
AA
BB
AC
AD
C
1
8
0.070 (1,78)
0.045 (1,14)
D
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
D
0.030 (0,76)
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
(18,03)
A MAX
(10,41) (11,73) (12,95) (15,49)
0.400
0.453
0.500
0.600
0.700
(17,78)
A MIN
(10,16) (11,51) (12,70) (15,24)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明