SNJ54AC563W [TI]
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS; 八路D型透明锁存器带3态输出
| 型号： | SNJ54AC563W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003
SN54AC563 . . . J OR W PACKAGE
SN74AC563 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
2-V to 6-V V
Operation
CC
Inputs Accept Voltages to 6 V
Max t of 9 ns at 5 V
pd
3-State Inverting Outputs Drive Bus Lines
Directly
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
D
Full Parallel Access for Loading
D
Flow-Through Architecture to Optimize
PCB Layout
description/ordering information
The ’AC563 devices are octal D-type transparent
latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
GND
SN54AC563 . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
3
2
1
20 19
18
3D
4D
5D
6D
7D
2Q
17 3Q
4
5
6
7
8
16
15
14
4Q
5Q
6Q
9 10 11 12 13
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74AC563N
SN74AC563N
Tube
SN74AC563DW
SN74AC563DWR
SN74AC563NSR
SN74AC563DBR
SN74AC563PW
SN74AC563PWR
SNJ54AC563J
SOIC − DW
AC563
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
AC563
AC563
−40°C to 85°C
−55°C to 125°C
SSOP − DB
TSSOP − PW
AC563
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AC563J
SNJ54AC563W
SNJ54AC563FK
Tube
SNJ54AC563W
SNJ54AC563FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢂ ꢆ ꢇ
ꢊꢅ ꢋꢄ ꢌ ꢍ ꢎꢋ ꢏꢐꢑ ꢋꢒ ꢄꢁ ꢀꢐꢄꢒ ꢑꢁ ꢋ ꢌꢄꢋꢅ ꢓ ꢑꢀ
ꢔꢕ ꢋ ꢓ ꢇ ꢎꢀꢋꢄꢋ ꢑ ꢊꢖꢋ ꢐꢖ ꢋꢀ
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
19
1Q
2
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC563
SN74AC563
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
High-level input voltage
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
8
8
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC563
SN74AC563
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.99
4.49
5.49
2.56
3.86
4.86
TYP
MAX
MIN
2.9
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
4.4
4.4
I
I
= −50 µA
OH
5.4
5.4
= −12 mA
2.48
3.8
2.46
3.76
4.76
3.85
V
OH
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= −24 mA
= −75 mA
OH
4.8
†
3.85
OH
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.5
0.5
0.5
1.65
1
0.1
0.1
0.1
0.44
0.44
0.44
1.65
1
4.5 V
5.5 V
3 V
I
I
= 50 µA
OL
0.1
= 12 mA
= 24 mA
0.36
0.36
0.36
V
OL
V
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
I
I
OL
†
= 75 mA
OL
I
I
I
V = V
or GND
0.1
0.5
8
µA
µA
µA
pF
I
I
CC
V
= V
or GND
5
5
OZ
CC
O CC
V = V
or GND,
or GND
I = 0
O
80
I
CC
C
V = V
4.5
i
I
CC
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢀꢁ ꢉ ꢃ ꢄꢅꢂ ꢆ ꢇ
ꢊꢅ ꢋꢄ ꢌ ꢍ ꢎꢋ ꢏꢐꢑ ꢋꢒ ꢄꢁ ꢀꢐꢄꢒ ꢑꢁ ꢋ ꢌꢄꢋꢅ ꢓ ꢑꢀ
ꢔꢕ ꢋ ꢓ ꢇ ꢎꢀꢋꢄꢋ ꢑ ꢊꢖꢋ ꢐꢖ ꢋꢀ
SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54AC563
SN74AC563
A
UNIT
MIN
6
MAX
MIN
8
MAX
MIN
7
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
2.5
2
5
3
3
2
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54AC563
SN74AC563
A
UNIT
MIN
4
MAX
MIN
6
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
2
4.5
3
2.5
2
2
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.3
SN54AC563
SN74AC563
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
3.5
3.5
3.5
3.5
2.5
3
MAX
13
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
16.5
15.5
16.5
15.5
13.5
14
MIN
3.5
3.5
3.5
3.5
2.5
3.5
4.5
2.5
MAX
15
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
5.6
12
14
4.6
13
15
LE
OE
OE
ns
4.8
12
14
5.3
11
12
ns
5.4
11
12.5
13.5
10.5
4
6
12.5
9.5
15
ns
2
5.1
12
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.3
SN54AC563
SN74AC563
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2
MAX
10
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
13
MIN
2
MAX
11.5
11
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
2
5.6
9.5
9.5
8.5
9
12.5
12.5
11.5
11.5
11
2
2
4.6
2
11
LE
ns
2
4.8
2
9.5
10
2
5.3
2
ns
OE
OE
1.5
2
5.4
8.5
11
2
9.5
12
6
13.5
10.5
2
ns
1.5
5.1
8
1.5
9
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
C
25
pF
pd
L
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS552C − NOVEMBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
500 Ω
Open
From Output
Under Test
TEST
/t
S1
t
Open
PLH PHL
t
/t
2 × V
CC
Open
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
(see Note A)
PHZ PZH
LOAD CIRCUIT
V
CC
50% V
CC
Timing Input
Data Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
Input
CC
50% V
50% V
CC
CC
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
50% V
CC
50% V
CC
50% V
CC
50% V
Input
CC
0 V
0 V
t
t
t
PLZ
t
PHL
PZL
PLH
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
V
+ 0.3 V
OL
S1 at 2 × V
(see Note B)
CC
V
OL
OL
t
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
50% V
CC
OH
50% V
50% V
CC
CC
≈0 V
V
OL
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
Drawing
SN74AC563DBLE
SN74AC563DBR
OBSOLETE
ACTIVE
DB
20
20
TBD
Call TI
Call TI
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC563DBRE4
SN74AC563DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC563DWE4
SN74AC563DWR
SN74AC563DWRE4
SN74AC563N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74AC563NE4
SN74AC563NSR
SN74AC563NSRE4
SN74AC563PW
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
NS
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC563PWE4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC563PWLE
SN74AC563PWR
OBSOLETE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AC563PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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