SN74SSTV16859_16 [TI]
3-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS;
| 型号： | SN74SSTV16859_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS 输入元件 输出元件 |
| 文件： | 总10页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢀꢀ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ
ꢆ ꢋ ꢌꢍꢎ ꢄ ꢄ ꢏ ꢐ ꢇ ꢌꢍꢎ ꢄ ꢑꢒ ꢓꢎ ꢀꢄ ꢒꢑꢒꢔ ꢍ ꢕꢖ ꢖꢒ ꢑ
ꢗ ꢎꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢐ ꢎꢁ ꢛꢕꢄ ꢀ ꢜꢁꢔ ꢏ ꢕꢄ ꢛꢕ ꢄꢀ
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
DGG PACKAGE
(TOP VIEW)
D
D
Member of the Texas Instruments
Widebus Family
1-to-2 Outputs to Support Stacked DDR
DIMMs
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
V
DDQ
2
GND
D13
D12
D
Supports SSTL_2 Data Inputs
3
D
Outputs Meet SSTL_2 Class II
Specifications
4
5
V
V
CC
6
V
D
D
D
Differential Clock (CLK and CLK) Inputs
DDQ
DDQ
7
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
GND
D11
D10
D9
GND
D8
Supports LVCMOS Switching Levels on the
RESET Input
8
9
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
D
D
Pinout Optimizes DIMM PCB Layout
D7
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
RESET
GND
CLK
CLK
V
V
V
D6
GND
D5
D4
D3
GND
V
V
D2
D1
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
V
DDQ
DDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
CC
description/ordering information
REF
This 13-bit to 26-bit registered buffer is designed
for 2.3-V to 2.7-V V
operation.
CC
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
Q6B
GND
V
DDQ
Q5B
DDQ
CC
The SN74SSTV16859 operates from a differential
clock (CLK and CLK). Data are registered at the
crossing of CLK going high and CLK going low.
Q4B
Q3B
Q2B
Q1B
GND
V
DDQ
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
QFN − RGQ
A
SN74SSTV16859RGQR
SN74SSTV16859RGQ8
(Tin−Pb Finish)
Tape and reel
SS859
0°C to 70°C
QFN − RGQ
(Matte−Tin Finish)
TSSOP − DGG
Tape and reel SN74SSTV16859DGGR
SSTV16859
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ
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ꢩ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆꢋ ꢌꢍꢎ ꢄ ꢄꢏ ꢐ ꢇꢌ ꢍꢎ ꢄ ꢑꢒ ꢓ ꢎꢀ ꢄꢒ ꢑꢒ ꢔ ꢍꢕ ꢖꢖ ꢒ ꢑ
ꢗꢎ ꢄ ꢘ ꢀꢀ ꢄ ꢙ ꢚꢐ ꢎ ꢁ ꢛꢕ ꢄꢀ ꢜꢁ ꢔ ꢏ ꢕꢄꢛ ꢕꢄ ꢀ
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
description/ordering information (continued)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
RGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
D10
D9
D8
D7
RESET
GND
CLK
CLK
†
GND
9
V
V
V
V
DDQ
DDQ
CC
REF
10
11
12
13
14
Q12B
Q11B
Q10B
Q9B
D6
D5
D4
Q8B
†
The center die pad must be connected to GND.
FUNCTION TABLE
INPUTS
OUTPUT
Q
RESET
CLK
↑
CLK
↓
D
H
H
H
H
H
L
↑
↓
L
L or H
L or H
X
Q
0
X or
X or
X or
L
L
floating floating floating
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢎꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢐ ꢎꢁ ꢛꢕꢄ ꢀ ꢜꢁꢔ ꢏ ꢕꢄ ꢛꢕ ꢄꢀ
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
logic diagram (positive logic)
51
RESET
48
CLK
49
CLK
45
V
REF
One of 13 channels
35
D1
16
32
Q1A
Q1B
1D
C1
R
To 12 Other Channels
Pin numbers shown are for the DGG package.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
CC
DDQ
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
CC
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
DDQ
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O
O
DDQ
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through each V , V
O
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
JA
(see Note 4): RGQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗꢎ ꢄ ꢘ ꢀꢀ ꢄ ꢙ ꢚꢐ ꢎ ꢁ ꢛꢕ ꢄꢀ ꢜꢁ ꢔ ꢏ ꢕꢄꢛ ꢕꢄ ꢀ
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
recommended operating conditions (see Note 5)
MIN
NOM
MAX
2.7
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
V
CC
DDQ
REF
TT
I
DDQ
2.3
Output supply voltage
2.7
V
Reference voltage (V
Termination voltage
Input voltage
= V
DDQ
/2)
1.15
1.25
1.35
+ 40 mV
V
REF
V
− 40 mV
0
V
V
V
REF
REF
REF
REF
REF
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
V
+ 310 mV
V
IH
V
V
− 310 mV
− 150 mV
V
IL
REF
+ 150 mV
1.7
V
IH
V
IL
REF
V
IH
RESET
0.7
V
IL
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
I
I
−20
20
OH
mA
Low-level output current
OL
T
Operating free-air temperature
0
70
_C
A
NOTE 5: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
V
I = −18 mA
2.3 V
2.3 V to 2.7 V
2.3 V
−1.2
V
IK
I
I
I
I
I
= −100 µA
= −16 mA
= 100 µA
= 16 mA
V
DDQ
1.95
− 0.2
OH
OH
OL
OL
V
V
OH
2.3 V to 2.7 V
2.3 V
0.2
0.35
5
V
OL
I
I
All inputs
V = V
I CC
or GND
2.7 V
µA
µA
Static standby
Static operating
RESET = GND
RESET = V , V = V
10
I
I
I
= 0
= 0
2.7 V
CC
O
or V
or V
40
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
Dynamic operating − RESET = V , V = V
,
,
µA/
MHz
CC
I
IL(AC)
30
10
clock only
CLK and CLK switching 50% duty cycle
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.5 V
CCD
O
Dynamic operating −
per each data input
r
r
r
Output high
Output low
I
I
I
= −20 mA
= 20 mA
7
7
20
20
Ω
Ω
Ω
2.3 V to 2.7 V
2.3 V to 2.7 V
2.5 V
OH
OL
OH
OL
r
− r
OH OL
= 20 mA, T = 25°C, One output
6
3.5
3.5
O(∆)
O
A
Data inputs
CLK, CLK
RESET
V = V
I
310 mV
2.5
2.5
3
3
3
REF
§
C
V
= 1.25 V, V
= 360mV
pF
2.5 V
i
ICR
I(PP)
or GND
V = V
CC
I
†
‡
§
For this test condition, V
DDQ
always is equal to V .
CC
All typical values are at V = 2.5 V, T = 25°C.
CC
A
Measured with 50-MHz input frequency for the QFN package and 10-MHz input frequency for the TSSOP package
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢎꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢐ ꢎꢁ ꢛꢕꢄ ꢀ ꢜꢁꢔ ꢏ ꢕꢄ ꢛꢕ ꢄꢀ
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
CC
0.2 V
†
UNIT
MIN
MAX
f
t
t
Clock frequency
200
MHz
ns
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 6)
2.5
w
22
22
ns
act
t
Differential inputs inactive time (see Note 7)
ns
inact
su
Setup time, fast slew rate (see Notes 8 and 10)
Setup time, slow slew rate (see Notes 9 and 10)
Hold time, fast slew rate (see Notes 8 and 10)
0.75
0.9
t
ns
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
0.75
t
h
ns
Hold time, slow slew rate (see Notes 9 and 10)
0.9
†
For this test condition, V
always is equal to V .
CC
DDQ
must be held at a valid input level, and data inputs must be held low for a minimum time of t
NOTES: 6. V
max, after RESET is taken high.
max, after RESET is taken
REF
act
7.
V
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t
REF inact
low.
8. For data signal input slew rate ≥ 1 V/ns
9. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns
10. CLK, CLK signals input slew rates are ≥ 1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
MIN
200
1.1
MAX
f
t
MHz
ns
max
CLK and CLK
RESET
Q
Q
2.8
5
pd
t
ns
PHL
†
For this test condition, V
DDQ
always is equal to V .
CC
5
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SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
TT
50 Ω
Test Point
From Output
Under Test
C
= 30 pF
L
(see Note A)
LOAD CIRCUIT
t
w
V
V
IH
V
REF
V
REF
Input
IL
LVCMOS
RESET
Input
V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
/2
V
CC
/2
0 V
V
I(PP)
t
t
act
inact
Timing
Input
V
ICR
V
ICR
I
CC
I
I
(operating)
CC
90%
(see
Note B)
t
t
PLH
PHL
10%
(standby)
CC
V
OH
OL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
Output
V
TT
V
TT
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
LVCMOS
RESET
Input
IH
Timing
Input
V
ICR
V
CC
/2
IL
t
PHL
t
t
h
su
V
V
V
OH
IH
V
REF
Input
V
REF
Output
V
TT
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V
L
I
or GND, and I = 0 mA.
CC
CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
V
V
V
= V
= V
= V /2
TT
IH
IL
REF
REF
DDQ
+ 310 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
IH CC
− 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
= V
and t
REF IL
t
are the same as t .
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74SSTV16859DGGRG4
74SSTV16859RGQ8G3
SN74SSTV16859DGGR
SN74SSTV16859RGQ8
SN74SSTV16859RGQR
TSSOP
DGG
64
56
64
56
56
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
TSSOP
QFN
RGQ
DGG
RGQ
RGQ
2000 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
QFN
2000
TBD
CU SNPB
Level-3-235C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MPQF113C − DECEMBER 2001 − REVISED AUGUST 2002
RGQ (S−PQFP−N56)
PLASTIC QUAD FLATPACK
8,15
7,85
A
B
42
29
43
28
8,15
7,85
Pin 1 Identifier
56
15
1
14
7,85
7,65
1,00
0,80
Sq
0,20 Nominal
Lead Frame
Seating Plane
0,08 C
C
0,05
0,00
5,35
5,05
0,50
0,30
56X
1
14
56
15
Pin 1 Identifier
4,65
4,35
6,50
4X
43
28
42
29
0,50
+0,07
−0,05
56X 0,23
Exposed Thermal Die Pad
D
0,10
0,05
C A B
C
M
M
Bottom View
4203438/D 08/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
This pad may be electrically connected to ground.
E. Package registration with JEDEC MO-220 variation VLLD-2.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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