SN74LVCZ240ADGVRG4 [TI]
LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, TVSOP-20;
| 型号： | SN74LVCZ240ADGVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, TVSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总15页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES273H–JUNE 1999–REVISED APRIL 2005
FEATURES
DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
•
•
•
•
Operates From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.5 ns at 3.3 V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
•
•
•
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC
)
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVCZ240A is designed specifically to improve the performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVCZ240AN
TOP-SIDE MARKING
PDIP – N
Tube of 20
SN74LVCZ240AN
Tube of 25
SN74LVCZ240ADW
SOIC – DW
LVCZ240A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SN74LVCZ240ADWR
SN74LVCZ240ANSR
SN74LVCZ240ADBR
SN74LVCZ240APW
SOP – NS
LVCZ240A
CV240A
–40°C to 85°C
SSOP – DB
TSSOP – PW
TVSOP – DGV
Reel of 2000
Reel of 250
Reel of 2000
SN74LVCZ240APWR
SN74LVCZ240APWT
SN74LVCZ240ADGVR
CV240A
CV240A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES273H–JUNE 1999–REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
L
H
Z
L
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
18
16
2
4
6
1Y1
1Y2
1Y3
1Y4
1A1
1A2
14
12
1A3
1A4
8
19
2OE
11
13
15
17
9
7
5
2Y1
2Y2
2A1
2A2
2A3
2A4
2Y3
2Y4
3
2
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES273H–JUNE 1999–REVISED APRIL 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC Supply voltage range
VI
Input voltage range(2)
6.5
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
70
DB package
DGV package
DW package
N package
92
58
θJA
Package thermal impedance(4)
°C/W
°C
69
NS package
PW package
60
83
Tstg
Storage temperature range
–65
150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.7
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
0.8
5.5
VCC
5.5
–12
–24
12
0
0
0
High or low state
3-state
VO
IOH
IOL
Output voltage
V
VCC = 2.7 V
VCC = 3 V
High-level output current
Low-level output current
mA
mA
VCC = 2.7 V
VCC = 3 V
24
∆t/∆v
∆t/∆VCC
TA
Input transition rise or fall rate
Power-up ramp rate
6
ns/V
µs/V
°C
150
–40
Operating free-air temperature
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES273H–JUNE 1999–REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.7 V to 3.6 V
2.7 V
MIN TYP(1) MAX
UNIT
IOH = –100 µA
VCC – 0.2
2.2
VOH
IOH = –12 mA
V
3 V
2.4
IOH = –24 mA
3 V
2.2
IOL = 100 µA
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
±5
VOL
IOL = 12 mA
V
IOL = 24 mA
3 V
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VO = 0.5 to 2.5 V,
VO = 0.5 to 2.5 V,
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
3.6 V
µA
µA
µA
µA
µA
Ioff
0
±5
IOZ
3.6 V
±5
IOZPU
IOZPD
OE = don't care
0 to 1.5 V
1.5 V to 0
±5
OE = don't care
±5
100
100
100
ICC
IO = 0
3.6 V
µA
∆ICC
Ci
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
µA
pF
pF
3.5
5.5
Co
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.3
1.1
1.4
MAX
tpd
ten
tdis
A or B
OE
B or A
A or B
A or B
7.5
9
6.5
8
ns
ns
ns
OE
8
7
Operating Characteristics
TA = 25°C
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
37
3
Outputs enabled
Outputs disabled
Cpd
Power dissipation capacitance per buffer/driver
f = 10 MHz
pF
4
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES273H–JUNE 1999–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V and 3.3 V ± 0.3 V
2 × V
CC
S1
TEST
S1
500 Ω
Open
GND
From Output
Under Test
t
pd
Open
t
t
/t
2 × V
CC
GND
PLZ PZL
C = 30 pF
L
500 Ω
/t
PHZ PZH
(see Note A)
t
w
LOAD CIRCUIT
V
CC
V /2
CC
V /2
CC
Input
V
CC
Timing
Input
0 V
V
/2
h
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
V
CC
Data
Input
V
CC
Output
V /2
CC
V /2
CC
Control
(low-level
enabling)
0 V
V /2
CC
V /2
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
V /2
CC
Input
V /2
CC
V
OL
+ 0.3 V
S1 at 2 × V
V /2
CC
CC
(see Note B)
OL
0 V
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
V
OH
− 0.3 V
OH
V /2
CC
Output
V /2
CC
V /2
CC
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
SN74LVCZ240ADW
SN74LVCZ240ADWR
SN74LVCZ240ANSR
SN74LVCZ240APW
SN74LVCZ240APWR
SN74LVCZ240APWRG4
SN74LVCZ240APWT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
DW
20
20
20
20
20
20
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LVCZ240A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
NS
2000
2000
70
Green (RoHS
& no Sb/Br)
LVCZ240A
LVCZ240A
CV240A
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
Green (RoHS
& no Sb/Br)
2000
2000
250
Green (RoHS
& no Sb/Br)
CV240A
Green (RoHS
& no Sb/Br)
CV240A
Green (RoHS
& no Sb/Br)
CV240A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVCZ240ADWR
SN74LVCZ240ANSR
SN74LVCZ240APWR
SN74LVCZ240APWT
SOIC
SO
DW
NS
20
20
20
20
2000
2000
2000
250
330.0
330.0
330.0
330.0
24.4
24.4
16.4
16.4
10.8
8.2
13.3
13.0
7.1
2.7
2.5
1.6
1.6
12.0
12.0
8.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
6.95
6.95
7.1
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCZ240ADWR
SN74LVCZ240ANSR
SN74LVCZ240APWR
SN74LVCZ240APWT
SOIC
SO
DW
NS
20
20
20
20
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
38.0
38.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
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