SN74LVCZ240APWLE [TI]
LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20;
| 型号： | SN74LVCZ240APWLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总9页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES273B – JUNE 1999 – REVISED JANUARY 2000
DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
= 3.3 V, T = 25°C
A
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
Typical V
(Output V
Undershoot)
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
I
and Power-Up 3-State Support Hot
off
Insertion
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
)
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Shrink
Small-Outline (DB), Plastic Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages
description
This octal buffer/driver is designed for 2.7-V to 3.6-V V
operation.
CC
The SN74LVCZ240A is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN74LVCZ240A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES273B – JUNE 1999 – REVISED JANUARY 2000
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
†
logic diagram (positive logic)
logic symbol
1
1OE
1
1OE
EN
18
16
2
2
4
6
8
18
1Y1
1Y2
1Y3
1Y4
1A1
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
16
14
12
4
1A2
6
14
12
1A3
19
EN
2OE
8
1A4
11
13
15
17
9
7
5
3
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
19
2OE
11
9
7
5
2Y1
2Y2
2A1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
13
2A2
15
2Y3
2Y4
2A3
17
3
2A4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES273B – JUNE 1999 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
Supply voltage
3.6
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
5.5
CC
0
0
0
High or low state
3-state
V
CC
5.5
V
O
Output voltage
V
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
24
6
I
I
High-level output current
mA
OH
OL
= 2.7 V
= 3 V
Low-level output current
mA
∆t/∆v
∆t/∆V
Input transition rise or fall rate
ns/V
Power-up ramp rate
150
85
µs/V
°C
CC
T
Operating free-air temperature
–40
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES273B – JUNE 1999 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
V –0.2
CC
MAX
UNIT
V
CC
I
I
= –100 µA
2.7 V to 3.6 V
2.7 V
OH
2.2
2.4
2.2
V
= –12 mA
V
OH
OL
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
±5
V
V
3 V
I
I
I
I
I
V = 0 to 5.5 V
3.6 V
µA
µA
µA
µA
µA
I
I
V or V = 5.5 V
0
±5
off
I
O
V
V
V
= 0 to 5.5 V
3.6 V
±5
O
O
O
OZ
= 0.5 to 2.5 V,
= 0.5 to 2.5 V,
OE = don’t care
OE = don’t care
0 to 1.5 V
1.5 V to 0
±5
OZPU
OZPD
±5
V = V
or GND
100
100
100
I
CC
I
I
= 0
3.6 V
µA
CC
O
‡
3.6 V ≤ V ≤ 5.5 V
I
∆I
CC
One input at V
CC
– 0.6 V,
Other inputs at V
or GND
2.7 V to 3.6 V
3.3 V
µA
pF
pF
CC
C
V = V
or GND
3.5
5.5
i
I
CC
= V
C
V
O
or GND
3.3 V
o
CC
= 3.3 V, T = 25°C.
†
‡
All typical values are at V
CC
This applies in the disabled state only.
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
7.5
9
MIN
1.3
1.1
1.4
MAX
6.5
8
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
t
en
t
8
7
OE
dis
operating characteristics, T = 25°C
A
V
CC
= 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Outputs enabled
Outputs disabled
37
3
C
Power dissipation capacitance per buffer/driver
f = 10 MHz
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ240A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES273B – JUNE 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
2 × V
CC
Open
GND
S1
TEST
S1
500 Ω
From Output
Under Test
t
Open
pd
/t
t
2 × V
CC
GND
PLZ PZL
/t
C
= 30 pF
L
500 Ω
t
PHZ PZH
(see Note A)
t
LOAD CIRCUIT
w
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
V
CC
Output
V
CC
/2
V
CC
/2
Control
(low-level
enabling)
0 V
V
CC
/2
V
CC
/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
V
+ 0.3 V
S1 at 2 × V
(see Note B)
V
CC
/2
OL
CC
V
OL
0 V
t
t
PZH
PHZ
– 0.3 V
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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PRODUCT FOLDER PRODUCT INFO:
|
APPLICATION NOTES RELATED DOCUMENTS
|
PRODUCT SUPPORT: TRAINING
SN74LVCZ240A, Octal Buffer/Driver With 3-State Outputs
DEVICE STATUS: ACTIVE
FEATURES
Back to Top
TM
l EPIC
(Enhanced-Performance Implanted CMOS) Submicron Process
Typical V
(Output Ground Bounce) <0.8 V at V
= 3.3 V, T = 25°C
l
OLP
CC
A
Typical V
(Output V
Undershoot)
l
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
I and Power-Up 3-State Support Hot Insertion
l
off
l Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V
V )
CC
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
l
l Package Options Include Shrink Small-Outline (DB), Plastic Thin Very Small-Outline
(DGV), Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages
EPIC is a trademark of Texas Instruments Incorporated.
DESCRIPTION
Back to Top
This octal buffer/driver is designed for 2.7-V to 3.6-V V
operation.
CC
The SN74LVCZ240A is designed specifically to improve the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE\) inputs.
When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high,
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these
devices as translators in a mixed 3.3-V/5-V system environment.
2 of 3
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up
CC
or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied
to V through a pullup resistor; the minimum value of the resistor is determined by the
CC
current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The
off
I circuitry disables the outputs, preventing damaging current backflow through the device
off
when it is powered down. The power-up 3-state circuitry places the outputs in the high-
impedance state during power up and power down, which prevents driver conflict.
The SN74LVCZ240A is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
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To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
DATASHEET
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Full datasheet in Acrobat PDF: sces273b.pdf (83 KB) (
)
Updated: 01/13/2000
Full datasheet in Zipped PostScript: sces273b.psz (87 KB)
APPLICATION NOTES
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View Application Reports for Digital Logic
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive
l
l
Outputs (SCBA012A -
)
Updated: 08/01/1997
CMOS Power Consumption and CPD Calculation (SCAA035B -
)
Updated: 06/01/1997
l Implications of Slow or Floating CMOS Inputs (SCBA004C -
)
Updated: 02/01/1998
l Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated:
)
10/01/1996
l LVC Characterization Information (SCBA011 -
)
Updated: 12/01/1996
l Live Insertion (SDYA012 - Updated: 10/01/1996)
Low-Voltage Logic (LVC) Designer's Guide (SCBA010 -
)
Updated: 09/01/1996
l
l Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices (SCEA005 -
Updated:
)
12/01/1997
l Understanding Advanced Bus-Interface Products Design Guide (SCAA029, 253 KB -
)
Updated: 05/01/1996
RELATED DOCUMENTS
Back to Top
Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB -
l
l
Updated:
)
05/06/1999
Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB -
)
Updated: 04/17/2000
l MicroStar Junior BGA Design Summary (SCET004, 167 KB -
)
Updated: 07/28/2000
l More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996)
SAMPLES
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SAMPLES
Request Samples
ORDERABLE DEVICE
PACKAGE
DB
PINS
20
TEMP (ºC)
-40 TO 85
STATUS
ACTIVE
SN74LVCZ240ADBR
3 of 3
SN74LVCZ240ADGVR
SN74LVCZ240ADWR
SN74LVCZ240APWR
DGV
DW
PW
20
20
20
-40 TO 85
-40 TO 85
-40 TO 85
ACTIVE
ACTIVE
ACTIVE
Request Samples
Request Samples
Request Samples
PRICING/AVAILABILITY
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BUDGETARY
TEMP
(ºC)
PRICE
US$/UNIT
QTY=1000+
PACK
QTY
ORDERABLE DEVICE PACKAGE PINS
STATUS
PRICING/AVAILABILITY
-40 TO
85
SN74LVCZ240ADBR
SN74LVCZ240ADGVR
SN74LVCZ240ADW
SN74LVCZ240ADWR
SN74LVCZ240AN
DB
DGV
DW
DW
N
20
20
20
20
20
20
20
20
ACTIVE
ACTIVE
0.59
0.67
0.59
0.59
0.59
2000
2000
25
Check stock or order
Check stock or order
Check stock or order
Check stock or order
Check stock or order
-40 TO
85
-40 TO
85
ACTIVE
-40 TO
85
ACTIVE
2000
20
-40 TO
85
ACTIVE
-40 TO
85
SN74LVCZ240ANSR
SN74LVCZ240APW
SN74LVCZ240APWR
NS
OBSOLETE
OBSOLETE
ACTIVE
-40 TO
85
PW
PW
-40 TO
85
0.59
2000
Check stock or order
Table Data Updated on: 11/17/2000
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相关型号：
SN74LVCZ240APWTG4
LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20
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