SN74LVCZ16245ADLG4 [TI]
LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, SSOP-48;
| 型号： | SN74LVCZ16245ADLG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, SSOP-48 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Operates From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
Max t of 3.7 ns at 3.3 V
pd
4
I
and Power-Up 3-State Support Hot
off
5
Insertion
6
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
3.3-V V
)
CC
9
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver is designed for 2.7-V to 3.6-V V
operation.
V
V
CC
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
The SN74LVCZ16245A is designed for
asynchronous communication between data
buses. The control-function implementation
minimizes external timing requirements.
2DIR
This device can be used as two 8-bit transceivers
or one 16-bit transceiver. It allows data
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVCZ16245ADL
SSOP – DL
LVCZ16245A
Tape and reel
SN74LVCZ16245ADLR
SN74LVCZ16245ADGGR
SN74LVCZ16245ADGVR
–40°C to 85°C
TSSOP – DGG Tape and reel
TVSOP – DGV Tape and reel
LVCZ16245A
CW245A
†
Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
description/ordering information (continued)
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
logic diagram (positive logic)
1
24
1DIR
2DIR
48
25
13
1OE
1B1
2OE
2B1
47
36
1A1
2A1
2
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
Supply voltage
3.6
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
5.5
CC
0
0
0
High or low state
3-state
V
CC
5.5
V
O
Output voltage
V
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
24
6
I
I
High-level output current
mA
OH
= 2.7 V
= 3 V
Low-level output current
mA
OL
∆t/∆v
∆t/∆V
Input transition rise or fall rate
ns/V
Power-up ramp rate
150
µs/V
°C
CC
T
Operating free-air temperature
–40
85
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
V –0.2
CC
MAX
UNIT
V
CC
I
I
= –100 µA
= –12 mA
2.7 V to 3.6 V
2.7 V
OH
2.2
2.4
2.2
V
V
OH
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
±5
V
V
OL
3 V
I
I
I
I
I
Control inputs
V = 0 to 5.5 V
3.6 V
µA
µA
µA
µA
µA
I
I
V or V = 5.5 V
0
±5
off
I
O
‡
V
V
V
= 0 to 5.5 V
3.6 V
±5
O
O
O
OZ
= 0.5 V to 2.5 V,
= 0.5 V to 2.5 V,
OE = don’t care
OE = don’t care
0 to 1.5 V
1.5 V to 0
±5
OZPU
OZPD
±5
V = V
or GND
60
I
CC
I
I
O
= 0
3.6 V
µA
CC
§
3.6 V ≤ V ≤ 5.5 V
60
I
∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
C
C
Control inputs
A or B ports
V = V
or GND
5
i
I
CC
= V
V
O
or GND
3.3 V
6.5
io
CC
†
‡
§
All typical values are at V
For I/O ports, the parameter I
OZ
This applies in the disabled state only.
= 3.3 V, T = 25°C.
CC
A
includes the input leakage current.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
4.2
MIN
1.3
1.4
2
MAX
4
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
t
en
6.1
5.6
6.6
t
7.1
OE
dis
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
3.9
1
3.7
ns
ns
ns
pd
en
dis
5.9
6.7
1.1
1.6
5.4
6.2
OE
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
operating characteristics, T = 25°C
A
V
= 3.3 V
CC
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Outputs enabled
Outputs disabled
42
4
C
Power dissipation capacitance per transceiver
f = 10 MHz
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCZ16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES278D – JUNE 1999 – REVISED AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF or 50 pF
(see Note A)
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ 0.3 V
OL
CC
V
0 V
OL
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.3 V
V
CC
/2
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74LVCZ16245ADGGRE4
74LVCZ16245ADGGRG4
74LVCZ16245ADGVRE4
74LVCZ16245ADGVRG4
74LVCZ16245ADLRG4
SN74LVCZ16245ADGGR
SN74LVCZ16245ADGVR
SN74LVCZ16245ADL
TSSOP
DGG
48
48
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
SSOP
DGG
DGV
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
SSOP
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCZ16245ADLG4
SN74LVCZ16245ADLR
SSOP
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVCZ16245ADGGR TSSOP
SN74LVCZ16245ADGVR TVSOP
DGG
DGV
DL
48
48
48
2000
2000
1000
330.0
330.0
330.0
24.4
16.4
32.4
8.6
7.1
15.8
10.2
1.8
1.6
3.1
12.0
12.0
16.0
24.0
16.0
32.0
Q1
Q1
Q1
SN74LVCZ16245ADLR
SSOP
11.35 16.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCZ16245ADGGR
SN74LVCZ16245ADGVR
SN74LVCZ16245ADLR
TSSOP
TVSOP
SSOP
DGG
DGV
DL
48
48
48
2000
2000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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