SN74LVC1G06DCK [TI]
LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-5;![SN74LVC1G06DCK](http://pdffile.icpdf.com/pdf2/p00304/img/icpdf/SN74LVC1G06D_1834576_icpdf.jpg)
型号: | SN74LVC1G06DCK |
厂家: | ![]() |
描述: | LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO5, PLASTIC, SOT-5 输入元件 光电二极管 逻辑集成电路 |
文件: | 总6页 (文件大小:85K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN74LVC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES295I – JUNE 2000 – REVISED SEPTEMBER 2002
DBV OR DCK PACKAGE
(TOP VIEW)
Available in the Texas Instruments
NanoStar and NanoFree Packages
Supports 5-V V
Operation
CC
NC
A
GND
V
Y
1
2
3
5
4
CC
Input and Open-Drain Output Accept
Voltages up to 5.5 V
Max t of 4 ns at 3.3 V
pd
Low Power Consumption, 10 µA Max I
±24-mA Output Drive at 3.3 V
NC – No internal connection
CC
YEA OR YZA PACKAGE
(BOTTOM VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
3 4
2
GND
A
DNU
Y
V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1 5
CC
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DNU – Do not use
– 1000-V Charged-Device Model (C101)
description/ordering information
This single inverter buffer/driver is designed for 1.65-V to 5.5-V V
operation.
CC
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
The output of the SN74LVC1G06 device is open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using I .The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
NanoStar
WCSP (DSBGA) – YEA (Lead)
Tape and reel
Tape and reel
SN74LVC1G06YEAR
_ _ _CT_
NanoFree
SN74LVC1G06YZAR
–40°C to 85°C
WCSP (DSBGA) – YZA (Lead-free)
SOT (SOT-23) – DBV
Tape and reel
Tape and reel
SN74LVC1G06DBVR
SN74LVC1G06DCKR
C06_
CT_
SOT (SC-70) – DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES295I – JUNE 2000 – REVISED SEPTEMBER 2002
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
2
4
A
Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES295I – JUNE 2000 – REVISED SEPTEMBER 2002
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
IH
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.7 × V
CC
0.35 × V
0.7
0.8
0.3 × V
5.5
5.5
4
CC
V
IL
Low-level input voltage
= 4.5 V to 5.5 V
CC
V
V
Input voltage
0
0
V
V
I
Output voltage
O
V
V
= 1.65 V
= 2.3 V
CC
8
CC
I
Low-level output current
16
mA
OL
V
CC
= 3 V
24
V
CC
V
CC
V
CC
V
CC
= 4.5 V
32
= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
20
∆t/∆v Input transition rise or fall rate
10
ns/V
5
T
A
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
MIN
MAX
0.1
UNIT
TYP
CC
I
I
I
I
I
I
= 100
A
1.65 V to 5.5 V
1.65 V
OL
OL
OL
OL
OL
OL
= 4 mA
= 8 mA
0.45
0.3
2.3 V
V
V
OL
= 16 mA
= 24 mA
= 32 mA
0.4
3 V
0.55
0.55
±5
4.5 V
0 to 5.5 V
0
I
I
I
A input
V = 5.5 V or GND
A
A
I
I
V or V = 5.5 V
±10
10
off
I
O
V = 5.5 V or GND,
I = 0
O
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
A
CC
I
∆I
CC
One input at V
CC
– 0.6 V,
Other inputs at V
or GND
500
A
CC
C
C
V = V
or GND
4
5
pF
pF
i
I
CC
= V
V
or GND
3.3 V
o
O
CC
= 3.3 V, T = 25°C.
†
All typical values are at V
CC
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES295I – JUNE 2000 – REVISED SEPTEMBER 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
CC
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
pd
A
Y
2.2
5.6
1.1
4
1.2
4
1
3
ns
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
CC
= 3.3 V
V = 5 V
CC
CC
TYP
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
TYP
TYP
TYP
C
Power dissipation capacitance
3
3
4
6
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G06
SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUT
SCES295I – JUNE 2000 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
Open
S1
R
L
TEST
S1
From Output
Under Test
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
R
L
C
t
L
PLZ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
C
V
∆
R
V
CC
LOAD
L
L
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
V
V
/2
/2
2 × V
2 × V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤ 2 ns
≤ 2 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
CC
V
CC
CC
3 V
1.5 V
/2
6 V
≤ 2.5 ns
≤ 2.5 ns
V
CC
V
CC
2 × V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
M
Output
M
V
V
+ V
∆
S1 at V
(see Note B)
OL
LOAD
OL
OL
t
t
t
PHZ
PLH
PZH
Output
Waveform 2
S1 at V
LOAD
(see Note B)
V
∆
V
V
LOAD
OH
– V
LOAD/2
V
M
M
M
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E. Since this device has open-drain outputs, t
and t
are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at V
.
M
PZL
PLZ
is measured at V
+ V .
∆
OL
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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