SN74LVC1G06DCKTE4 [TI]
SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT; 单个逆变器缓冲器/驱动器，具有漏极开路输出
| 型号： | SN74LVC1G06DCKTE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT |
| 文件： | 总24页 (文件大小：1195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G06
www.ti.com
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
Check for Samples: SN74LVC1G06
1
FEATURES
2
•
Available in the Texas Instruments
NanoFree™ Package
•
•
•
Ioff Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
•
•
Supports 5-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Input and Open-Drain Output Accept
Voltages up to 5.5 V
ESD Protection Exceeds JESD 22
•
•
•
Max tpd of 4 ns at 3.3 V
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
5
4
N.C.
A
VCC
1
2
3
5
N.C.
A
VCC
1
2
3
N.C.
A
5
4
VCC
GND
Y
4
GND
Y
GND
Y
DRY PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
1
2
3
6
5
4
VCC
N.C.
1
2
3
6
5
4
N.C.
A
VCC
A
N.C.
Y
N.C.
Y
GND
N.C. – No internal connection
See mechanical drawings for dimensions.
GND
YZP PACKAGE
(TOP VIEW)
Table 1. YZP PACKAGE TERMINAL
ASSIGNMENTS
A1
B1
C1
A2
B2
C2
1
2
VCC
No ball
Y
DNU
A
VCC
A
B
C
DNU
A
GND
Y
GND
DNU – Do not use
YZV PACKAGE
(TOP VIEW)
Table 2. YZV PACKAGE TERMINAL
ASSIGNMENTS
A1
B1
A2
B2
1
A
2
VCC
Y
A
VCC
Y
A
B
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2012, Texas Instruments Incorporated
SN74LVC1G06
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
www.ti.com
DESCRIPTION/ORDERING INFORMATION
This single inverter buffer/driver is designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
The output of the SN74LVC1G06 device is open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
Reel of 3000
SN74LVC1G06YZPR
_ _ _CT_
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZV (Pb-free)
_ _ _ _
CT
SN74LVC1G06YZVR
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
SN74LVC1G06DBVR
SN74LVC1G06DBVT
SN74LVC1G06DCKR
SN74LVC1G06DCKT
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
C06_
–40°C to 85°C
CT_
Jumbo Tube of
10000
SN74LVC1G06DCKJ
SOT (SOT-553) – DRL
µQFN – DSF
Reel of 4000
Reel of 5000
Reel of 5000
SN74LVC1G06DRLR
SN74LVC1G06DSFR
SN74LVC1G06DRYR
CT_
CT
QFN – DRY
CT
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2
has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Table 3. FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
DBV, DCK, DSF, DRY, DRL, and YZP PACKAGE
2
4
A
Y
YZV PACKAGE
2
4
A
Y
2
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Copyright © 2000–2012, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G06
SN74LVC1G06
www.ti.com
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
6.5
V
VO
VO
IIK
6.5
V
6.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
206
252
142
132
123
300
234
150
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DBV package
DCK package
DRL package
YZP package
YZV package
DSF package
DRY package
θJA
Package thermal impedance(4)
°C/W
°C
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
VI
Input voltage
0
0
5.5
5.5
4
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
24
32
20
10
5
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Δt/Δv Input transition rise or fall rate
ns/V
°C
TA
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2000–2012, Texas Instruments Incorporated
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SN74LVC1G06
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
MAX
0.1
UNIT
IOL = 100 μA
IOL = 4 mA
0.45
0.3
IOL = 8 mA
2.3 V
VOL
V
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.55
0.55
±1
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
A input
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
μA
μA
μA
μA
pF
pF
Ioff
ICC
±10
10
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
ΔICC
Ci
One input at VCC – 0.6 V,
VI = VCC or GND
Other inputs at VCC or GND
500
4
5
Co
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
2.2
6.5
1.1
4
1.2
4
1
3
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd Power dissipation capacitance
f = 10 MHz
3
3
4
6
pF
4
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Copyright © 2000–2012, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G06
SN74LVC1G06
www.ti.com
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
S1
Open
R
L
TEST
S1
From Output
Under Test
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
R
L
C
L
t
PLZ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
LOAD
C
L
V
∆
R
L
V
CC
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
V
/2
/2
2 × V
2 × V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
V
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
2 × V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
PLZ
t
t
PHL
PZL
PLH
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
S1 at V
LOAD
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
V
LOAD
V
V
OH
− V
∆
LOAD/2
M
V
M
M
Output
S1 at V
LOAD
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t
and t are the same as t .
PZL pd
PLZ
F.
G.
t
t
is measured at V .
M
is measured at V + V .
∆
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2000–2012, Texas Instruments Incorporated
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SN74LVC1G06
SCES295V –JUNE 2000–REVISED NOVEMBER 2012
www.ti.com
REVISION HISTORY
Changes from Revision U (June 2011) to Revision V
Page
•
Added Jumbo Reel to ORDERING INFORMATION TABLE. ............................................................................................... 2
6
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Copyright © 2000–2012, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G06
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74LVC1G06DBVR
SN74LVC1G06DBVRE4
SN74LVC1G06DBVRG4
SN74LVC1G06DBVT
SN74LVC1G06DBVTE4
SN74LVC1G06DBVTG4
SN74LVC1G06DCKR
SN74LVC1G06DCKRE4
SN74LVC1G06DCKRG4
SN74LVC1G06DCKT
SN74LVC1G06DCKTE4
SN74LVC1G06DCKTG4
SN74LVC1G06DRLR
SN74LVC1G06DRLRG4
SN74LVC1G06DRYR
SN74LVC1G06DSFR
SN74LVC1G06YZPR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
(C065 ~ C06F ~
C06R ~ C06T)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DRL
DRL
DRY
DSF
YZP
3000
3000
250
Green (RoHS
& no Sb/Br)
(C065 ~ C06F ~
C06R ~ C06T)
Green (RoHS
& no Sb/Br)
(C065 ~ C06F ~
C06R ~ C06T)
Green (RoHS
& no Sb/Br)
(C065 ~ C06F ~
C06R)
250
Green (RoHS
& no Sb/Br)
(C065 ~ C06F ~
C06R)
250
Green (RoHS
& no Sb/Br)
(C065 ~ C06F ~
C06R)
3000
3000
3000
250
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR ~ CTT)
SC70
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR ~ CTT)
SC70
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR ~ CTT)
SC70
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR)
SC70
250
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR)
SC70
250
Green (RoHS
& no Sb/Br)
(CT5 ~ CTF ~ CTK ~
CTR)
SOT
4000
4000
5000
5000
3000
Green (RoHS
& no Sb/Br)
(CT7 ~ CTR)
(CT7 ~ CTR)
CT
SOT
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
CT
DSBGA
Green (RoHS
& no Sb/Br)
(CT7 ~ CTN)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
SN74LVC1G06YZVR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
DSBGA
YZV
4
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CT
(7 ~ N)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G06 :
Enhanced Product: SN74LVC1G06-EP
•
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G06DBVR
SN74LVC1G06DBVR
SN74LVC1G06DBVT
SN74LVC1G06DBVT
SN74LVC1G06DCKR
SN74LVC1G06DCKR
SN74LVC1G06DCKR
SN74LVC1G06DCKT
SN74LVC1G06DCKT
SN74LVC1G06DCKT
SN74LVC1G06DRLR
SN74LVC1G06DRLR
SN74LVC1G06DRYR
SN74LVC1G06DSFR
SN74LVC1G06YZPR
SN74LVC1G06YZVR
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DRL
DRL
DRY
DSF
YZP
YZV
5
5
5
5
5
5
5
5
5
5
5
5
6
6
5
4
3000
3000
250
178.0
178.0
178.0
178.0
178.0
180.0
178.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
178.0
178.0
9.0
9.2
9.0
9.2
9.2
9.2
9.0
9.2
9.0
9.2
9.5
8.4
9.5
9.5
9.2
9.2
3.23
3.3
3.17
3.2
1.37
1.55
1.37
1.55
1.22
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q1
Q2
Q1
Q1
3.23
3.3
3.17
3.2
250
3000
3000
3000
250
2.4
2.4
SC70
2.3
2.55
2.5
SC70
2.4
1.2
SC70
2.3
2.55
2.5
1.2
SC70
250
2.4
1.2
SC70
250
2.4
2.4
1.22
0.69
0.69
0.75
0.5
SOT
4000
4000
5000
5000
3000
3000
1.78
1.98
1.15
1.16
1.02
1.0
1.78
1.78
1.6
SOT
SON
SON
1.16
1.52
1.0
DSBGA
DSBGA
0.63
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G06DBVR
SN74LVC1G06DBVR
SN74LVC1G06DBVT
SN74LVC1G06DBVT
SN74LVC1G06DCKR
SN74LVC1G06DCKR
SN74LVC1G06DCKR
SN74LVC1G06DCKT
SN74LVC1G06DCKT
SN74LVC1G06DCKT
SN74LVC1G06DRLR
SN74LVC1G06DRLR
SN74LVC1G06DRYR
SN74LVC1G06DSFR
SN74LVC1G06YZPR
SN74LVC1G06YZVR
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DRL
DRL
DRY
DSF
YZP
YZV
5
5
5
5
5
5
5
5
5
5
5
5
6
6
5
4
3000
3000
250
180.0
180.0
180.0
180.0
180.0
205.0
180.0
205.0
180.0
180.0
180.0
202.0
180.0
180.0
220.0
220.0
180.0
180.0
180.0
180.0
180.0
200.0
180.0
200.0
180.0
180.0
180.0
201.0
180.0
180.0
220.0
220.0
18.0
18.0
18.0
18.0
18.0
33.0
18.0
33.0
18.0
18.0
30.0
28.0
30.0
30.0
35.0
35.0
250
3000
3000
3000
250
SC70
SC70
SC70
SC70
250
SC70
250
SOT
4000
4000
5000
5000
3000
3000
SOT
SON
SON
DSBGA
DSBGA
Pack Materials-Page 2
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
D: Max = 0.918 mm, Min =0.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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