SN74HSTL16918DGG [TI]
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH; 9位至18位的HSTL到LVTTL存储器地址锁存器
| 型号： | SN74HSTL16918DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH |
| 文件： | 总5页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Inputs Meet JEDEC HSTL Std JESD 8-6 and
Outputs Meet Level III Specifications
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2Q1
1Q1
GND
D1
V
V
CC
CC
2
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
3
1Q2
2Q2
GND
1Q3
2Q3
4
5
D2
Latch-Up Performance Exceeds 250 mA Per
JESD 17
6
V
CC
D3
7
Packaged in Plastic Thin Shrink
Small-Outline Package
8
D4
GND
1LE
V
CC
9
1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
description
GND
V
REF
This 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V V operation. The D inputs
GND
CC
2LE
GND
D5
D6
D7
accept HSTL levels and the Q outputs provide
LVTTL levels.
The SN74HSTL16918 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE) input.
V
CC
1Q7
2Q7
GND
1Q8
2Q8
V
CC
D8
D9
Eachof the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
GND
2Q9
1Q9
V
V
CC
CC
The SN74HSTL16918 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
Q
LE
D
H
L
L
L
H
L
†
Q
0
H
X
†
Output level before the
indicated steady-state input
conditions were established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
logic diagram (positive logic)
10
1LE
4
D1
1D
C1
2
1
1Q1
2Q1
14
1D
C1
2LE
To Eight Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
3.15
0.68
0
NOM
MAX
3.45
0.9
UNIT
V
V
V
V
V
V
V
V
Supply voltage
CC
REF
I
Reference voltage
0.75
V
Input voltage
1.5
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
All inputs
All inputs
All inputs
All inputs
V
V
+200 mV
REF
V
IH
IL
V
V
–200 mV
REF
V
+100 mV
REF
V
IH
IL
–100 mV
–24
V
REF
I
I
mA
mA
°C
OH
24
OL
T
A
0
70
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 3.15 V,
= 3.15 V,
= 3.15 V,
–1.2
V
V
V
IK
CC
CC
CC
I
I
I
= –24 mA
= 24 mA
2.4
OH
OL
OH
0.5
±5
OL
Control inputs
Data inputs
V = 0 or 1.5 V
I
I
I
V
CC
= 3.45 V
V = 0 or 1.5 V
I
±5
µA
V
V
= 0.68 V or 0.9 V
90
REF
REF
V = 0 or 1.5 V
I
V
CC
V
CC
V
CC
V
CC
= 3.45 V,
= 0 or 3.3 V,
= 0 or 3.3 V,
= 0,
50
2
100
mA
pF
pF
CC
I
Control inputs
Data inputs
Outputs
V = 0 or 3.3 V
I
C
i
V = 0 or 3.3 V
I
2.5
4
C
V
O
= 0
o
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V = 3.3 V
CC
± 0.15 V
UNIT
MIN
3
MAX
t
t
t
t
Pulse duration, LE low
Setup time, D before LE↑
Hold time
ns
ns
ns
ns
w
2
su
h
D after LE↑
D after LE↓
1
‡
Data race condition time
0
ldr
‡
This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a
glitch on the output.
switching characteristics over recommended operating free-air temperature range, V
= 0.75 V
REF
V
= 3.3 V
CC
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
MAX
3.4
4.2
D
t
pd
Q
ns
LE
1.9
simultaneous switching characteristics over recommended operating free-air temperature range,
§
V
= 0.75 V
REF
V
= 3.3 V
CC
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
MAX
D
4.4
5.2
t
pd
Q
ns
LE
1.9
§
All outputs switching
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES096C – APRIL 1997 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
1.25 V
0.25 V
V
REF
LE
From Output
Under Test
C
= 80 pF
L
t
su
t
h
500 Ω
(see Note A)
1.25 V
0.25 V
V
REF
V
REF
Data Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.25 V
0.25 V
Input
(see Note B)
V
REF
V
REF
t
t
PHL
t
w
PLH
1.25 V
0.25 V
V
V
OH
V
REF
V
REF
Output
Input
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1 ns, t ≤ 1 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
D. and t are the same as t
t
.
PHL
PLH pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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