SN74HSTL16919DGGR [TI]
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS; 9位至18位HSTL - TO- LVTTL存储器地址锁存器中输入上拉电阻
| 型号： | SN74HSTL16919DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS |
| 文件： | 总8页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
DGG PACKAGE
(TOP VIEW)
Member of Texas Instruments’ Widebus
Family
Inputs Meet JEDEC HSTL Std JESD 8-6,
and Outputs Meet Level III Specifications
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2Q1
1Q1
GND
D1
V
V
CC
CC
2
10-kΩ Pullup Resistor on Data and LE
Inputs
3
1Q2
2Q2
GND
1Q3
2Q3
4
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
5
D2
6
V
CC
D3
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
7
8
D4
GND
1LE
V
CC
9
1Q4
2Q4
GND
1Q5
2Q5
GND
1Q6
2Q6
– 1000-V Charged-Device Model (C101)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
description
V
REF
GND
This 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V V operation. The D inputs
2LE
GND
D5
D6
D7
CC
accept HSTL levels and the Q outputs provide
LVTTL levels.
V
CC
The SN74HSTL16919 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE) input.
1Q7
2Q7
GND
1Q8
2Q8
V
CC
D8
D9
GND
2Q9
1Q9
Eachof the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
V
V
CC
CC
To ensure low I
to ensure a differential voltage relative to V
during power up or power down, 10-kΩ pullup resistors are included on the D and LE inputs
CC
. V
must be applied prior to or at the same time as V , or
REF REF CC
V
must be pulled down to ground.
REF
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
0°C to 70°C
TSSOP – DGG Tape and reel
SN74HSTL16919DGGR
HSTL16919
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
FUNCTION TABLE
INPUTS
OUTPUT
Q
LE
D
H
L
L
L
H
L
†
Q
0
H
X
†
Output level before the
indicated steady-state input
conditions were established
logic diagram (positive logic)
12
V
REF
10
4
1LE
D1
1D
C1
2
1
1Q1
2Q1
14
1D
C1
2LE
To Eight Other Channels
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
recommended operating conditions (see Note 3)
MIN
3.15
0.68
0
NOM
MAX
3.45
0.9
UNIT
V
V
V
V
V
V
V
V
Supply voltage
CC
REF
I
Reference voltage
0.75
V
Input voltage
1.5
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
All inputs
All inputs
All inputs
All inputs
V
V
+200 mV
REF
V
IH
IL
V
V
–200 mV
REF
V
+100 mV
REF
V
IH
IL
–100 mV
–24
V
REF
I
I
mA
mA
°C
OH
OL
24
T
A
0
70
NOTE 3: All unused inputs of the device must maintain a minimum differential voltage of 100 mV between data inputs and V
to ensure proper
REF
device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 3.15 V,
= 3.15 V,
= 3.15 V,
–1.2
V
V
V
IK
CC
CC
CC
I
I
I
= –24 mA
2.4
OH
OL
OH
= 24 mA
0.5
–500
–500
90
OL
Control inputs
Data inputs
V = 0 or 1.5 V
I
I
I
V
CC
= 3.45 V
V = 0 or 1.5 V
I
µA
V
V
= 0.68 V or 0.9 V
REF
REF
V = 0 or 1.5 V
I
V
CC
V
CC
V
CC
V
CC
= 3.45 V,
= 0 or 3.3 V,
= 0 or 3.3 V,
= 0,
50
2.5
2.5
2.5
100
mA
pF
pF
CC
I
Control inputs
Data inputs
Outputs
V = 0 or 3.3 V
I
C
i
V = 0 or 3.3 V
I
C
V
O
= 0
o
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V = 3.3 V
CC
± 0.15 V
UNIT
MIN
3
MAX
t
t
t
t
Pulse duration, LE low
Setup time, D before LE↑
Hold time
ns
ns
ns
ns
w
2
su
h
D after LE↑
D after LE↓
1
‡
Data race condition time
0
ldr
‡
This is the maximum time after LE switches low that the data input can return to the latched state from the opposite state without producing a
glitch on the output.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
switching characteristics over recommended operating free-air temperature range, V
= 0.75 V
REF
V
= 3.3 V
CC
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
MAX
3.5
4.3
D
t
pd
Q
ns
LE
1.9
simultaneous switching characteristics over recommended operating free-air temperature range,
†
V
= 0.75 V
REF
V
= 3.3 V
CC
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
MAX
D
4.5
5.3
t
pd
Q
ns
LE
1.9
†
All outputs switching.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
PARAMETER MEASUREMENT INFORMATION
1.25 V
V
REF
LE
0.25 V
From Output
Under Test
t
t
h
su
C
= 80 pF
L
500 Ω
(see Note A)
1.25 V
0.25 V
V
REF
V
REF
Data Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.25 V
0.25 V
Input
(see Note B)
V
REF
V
REF
t
t
PHL
t
PLH
w
1.25 V
0.25 V
V
V
OH
V
REF
V
REF
Output
Input
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1 ns, t ≤ 1 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
D. and t are the same as t
t
.
pd
PHL
PLH
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74HSTL16919DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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