SN74HC259D [TI]
8-BIT ADDRESSABLE LATCHES; 8位可寻址锁存器
| 型号： | SN74HC259D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT ADDRESSABLE LATCHES |
| 文件： | 总9页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
SN54HC259 . . . J OR W PACKAGE
SN74HC259 . . . D, N, OR PW PACKAGE
(TOP VIEW)
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
Asynchronous Parallel Clear
Active-High Decoder
S0
S1
S2
Q0
Q1
Q2
Q3
GND
V
CC
CLR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Enable Input Simplifies Expansion
Expandable for n-Bit Applications
Four Distinct Functional Modes
G
D
Q7
Q6
Q5
Q4
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
SN54HC259 . . . FK PACKAGE
(TOP VIEW)
description
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches, and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
3
2
1
20 19
18
S2
Q0
NC
Q1
Q2
G
4
5
6
7
8
17
16
15
14
D
NC
Q7
Q6
9 10 11 12 13
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs.
In the addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all
unaddressed latches remaining in their previous
states. In the memory mode, all latches remain in
their previous states and are unaffected by the
data or address inputs. To eliminate the possibility
of entering erroneous data in the latches, G
should be held high (inactive) while the address
lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output
follows the level of the D input with all other
outputs low. In the clear mode, all outputs are low
and unaffected by the address and data inputs.
NC – No internal connection
The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC259 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
Function Tables
FUNCTION
OUTPUT OF
ADDRESSED
LATCH
EACH
OTHER
OUTPUT
INPUTS
FUNCTION
CLR
H
G
L
D
Q
Q
Addressable latch
Memory
iO
iO
H
H
L
Q
iO
L
D
L
8-line demultiplexer
Clear
L
H
L
L
LATCH SELECTION
SELECT INPUTS
LATCH
ADDRESSED
S2
S1
L
S0
L
L
L
H
L
0
1
2
3
4
5
6
7
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
†
logic symbol
1
S0
S1
S2
0
2
2
0
7
8M
3
14
13
G8
Z9
G
D
15
CLR
Z10
4
9, 0D
Q0
10, 0R
5
9, 1D
Q1
10, 1R
6
9, 2D
Q2
10, 2R
7
9, 3D
Q3
10, 3R
9
9, 4D
Q4
10, 4R
10
9, 5D
Q5
10, 5R
11
9, 6D
Q6
10, 6R
12
9, 7D
Q7
10, 7R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
1D
C1
4
5
1
S0
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
1R
1D
C1
1R
1D
C1
6
2
S1
1R
1D
C1
7
1R
3
S2
1D
C1
9
1R
1D
C1
10
1R
14
G
1D
C1
11
12
Q
Q
6
7
1R
13
D
1D
C1
1R
15
CLR
Pin numbers shown are for the D, J, N, PW, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
logic symbol, each internal latch
D
C
R
1D
C1
1R
Q
logic diagram, each internal latch (positive logic)
C
D
C
TG
C
Q
C
C
C
TG
C
R
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HC259
MIN NOM
SN74HC259
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
–55
–40
°C
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC259
SN74HC259
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 4 mA
4.5 V
6 V
0.26
0.26
±100
8
0.4
0.33
0.33
±1000
80
OL
= 5.2 mA
0.15
0.4
OL
I
I
V = V
I
or 0
6 V
±0.1
±1000
160
10
nA
µA
pF
I
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
C
2 V to 6 V
3
10
10
i
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC259
SN74HC259
A
V
UNIT
CC
MIN
80
16
14
80
16
14
75
15
13
5
MAX
MIN
120
24
20
120
24
20
115
23
20
5
MAX
MIN
100
20
17
100
20
17
95
19
16
5
MAX
2 V
4.5 V
6 V
CLR low
G low
t
w
Pulse duration
ns
2 V
4.5 V
6 V
2 V
t
t
Setup time, data or address before G↑
Hold time, data or address after G↑
4.5 V
6 V
ns
ns
su
2 V
4.5 V
6 V
5
5
5
h
5
5
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
60
18
14
56
17
13
74
21
17
66
20
16
28
8
SN54HC259
SN74HC259
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
190
38
2 V
4.5 V
6 V
t
t
t
CLR
Data
Any Q
Any Q
Any Q
Any Q
Any
ns
PHL
pd
t
26
38
32
2 V
130
26
195
39
165
33
4.5 V
6 V
22
33
28
2 V
200
40
300
60
250
50
Address
G
4.5 V
6 V
ns
34
51
43
2 V
170
34
255
51
215
43
4.5 V
6 V
29
43
37
2 V
75
110
22
95
4.5 V
6 V
15
19
ns
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per latch
TEST CONDITIONS
TYP
UNIT
C
No load
33
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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