SN74AVCH1T45YZPR [TI]
SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER; 单位双电源总线收发器
| 型号： | SN74AVCH1T45YZPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER |
| 文件： | 总21页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢐꢋ ꢉ ꢑꢒꢄ ꢍꢏꢀ ꢒꢓꢓꢍꢔ ꢐꢒꢀ ꢉ ꢕꢄꢁꢀ ꢆꢎ ꢋ ꢅꢎ ꢕ
ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Control Inputs V /V Levels Are
IH IL
CCA
1
2
3
6
5
4
V
GND
V
CCB
DIR
CCA
Referenced to V
Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
A
B
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D
D
D
I/Os Are 4.6-V Tolerant
I
Supports Partial-Power-Down Mode
off
3 4
2 5
1 6
A
GND
B
DIR
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CCB
CCA
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V . V accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
CCA CCA
V
. V
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
CCB CCB
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVCH1T45 is designed so that the DIR input is powered by V
.
CCA
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74AVCH1T45YEPR
SN74AVCH1T45YZPR
Tape and reel
_ _ _TF_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
SOT (SOT-23) − DBV
Tape and reel SN74AVCH1T45DBVR
Tape and reel SN74AVCH1T45DCKR
ET1_
TF_
SOT (SC-70) − DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖꢋ ꢉ ꢇ ꢆ ꢗꢁ ꢘꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅ ꢗꢍꢉꢄꢌ ꢎ ꢉꢕ ꢄꢁ ꢀꢍ ꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓꢒꢉ ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The V isolation feature ensures that if either V input is at GND, then both outputs are in the high-impedance
CC
CC
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
INPUT
OPERATION
DIR
L
B data to A bus
A data to B bus
H
logic diagram (positive logic)
5
DIR
3
A
4
B
V
CCA
V
CCB
2
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ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CCA
CCB
Input voltage range, V (see Note 1): I/O ports (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
I/O ports (B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
CCA
CCB
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
, V
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CCA CCB
Package thermal impedance, θ (see Note 3):DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCES598C – JULY 2004 – REVISED OCTOBER 2004
recommended operating conditions (see Notes 4 through 8)
V
CCI
V
CCO
MIN
1.2
MAX
3.6
UNIT
V
V
V
Supply voltage
Supply voltage
CCA
1.2
3.6
V
CCB
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
V
× 0.65
1.6
CCI
High-level input
voltage
Data inputs
(see Note 7)
V
IH
V
IL
V
IH
V
IL
V
V
V
V
2
V
× 0.35
CCI
Low-level input
voltage
Data inputs
(see Note 7)
0.7
0.8
V
CCA
× 0.65
1.6
DIR
High-level input
voltage
(referenced to V
(see Note 8)
)
)
CCA
2
V
CCA
× 0.35
0.7
DIR
Low-level input
voltage
(referenced to V
(see Note 8)
CCA
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CCO
Output voltage
O
3.6
−3
−6
−8
−9
−12
3
1.2 V
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
1.2 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
6
8
I
9
12
5
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
NOTES: 4. V is the V associated with the data input port.
ns/V
T
A
−40
85
°C
CCI
CCO
CC
CC
5.
V
is the V
associated with the output port.
6. All unused data inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CCI
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7. For V
8. For V
values not specified in the data sheet, V min = V
× 0.7 V, V max = V
× 0.7 V, V max = V
IL CCA
× 0.3 V.
× 0.3 V.
CCI
CCI
IH
CCI
IL CCI
values not specified in the data sheet, V min = V
IH
CCA
4
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SCES598C – JULY 2004 – REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Notes 9 and 10)
T
A
= 25°C
−40°C to 85°C
PARAMETER
TEST CONDITIONS
UNIT
V
CCA
V
CCB
MIN
TYP
MAX
MIN
MAX
I
I
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −3 mA
= −6 mA
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
V
CCO
− 0.2 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.95
1.4 V
1.4 V
1.05
1.2
V
V = V
IH
V
OH
I
= −8 mA
= −9 mA
= −12 mA
= 100 µA
= 3 mA
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
3 V
3 V
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
0.2
0.15
= 6 mA
1.4 V
1.4 V
0.35
0.45
0.55
0.7
V
OL
V = V
I IL
V
= 8 mA
1.65 V
2.3 V
1.65 V
2.3 V
= 9 mA
= 12 mA
3 V
3 V
DIR
input
I
I
V = V
CCA
or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
0.025
25
0.25
1
µA
µA
I
I
V = 0.42 V
I
1.2 V
1.4 V
1.65 V
2.3 V
3.3 V
1.2 V
1.4 V
1.65 V
2.3 V
3.3 V
1.2 V
1.6 V
1.95 V
2.7 V
3.6 V
1.2 V
1.6 V
1.95 V
2.7 V
3.6 V
1.2 V
1.4 V
1.65 V
2.3 V
3.3 V
1.2 V
1.4 V
1.65 V
2.3 V
3.3 V
1.2 V
1.6 V
1.95 V
2.7 V
3.6 V
1.2 V
1.6 V
1.95 V
2.7 V
3.6 V
V = 0.49 V
I
15
25
†
V = 0.58 V
I
BHL
V = 0.7 V
I
45
V = 0.8 V
I
100
V = 0.78 V
I
−25
V = 0.91 V
I
−15
−25
‡
V = 1.07 V
I
I
I
I
µA
µA
µA
BHH
V = 1.6 V
I
−45
V = 2 V
I
−100
50
125
200
300
500
§
V = 0 to V
CC
BHLO
I
−50
−125
−200
−300
−500
¶
V = 0 to V
CC
BHHO
I
†
‡
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
IL BHL
should be measured after lowering V to GND and
IN
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V and
IN CC
IH
BHH
then lowering it to V min.
IH
§
¶
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
associated with the output port.
NOTES: 9. V
is the V
CCO
is the V
CC
10.
V
associated with the input port.
CC
CCI
5
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SCES598C – JULY 2004 – REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Notes 9 and 10) (continued)
T
A
= 25°C
TYP
0.1
−40°C to 85°C
PARAMETER
TEST CONDITIONS
UNIT
V
V
CCB
CCA
MIN
MAX
MIN
MAX
A port
0 V
0 to 3.6 V
0 V
1
1
5
5
I
I
V or V = 0 to 3.6 V
µA
µA
off
I
O
B port
0 to 3.6 V
0.1
A or B
ports
V
O
= V
CCO
or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
0.5
2.5
5
OZ
1.2 V to 3.6 V
0 V
1.2 V to 3.6 V
3.6 V
10
−2
10
10
10
−2
20
I
V = V
or GND,
I
= 0
µA
µA
CCA
I
CCI
O
3.6 V
0 V
1.2 V to 3.6 V
0 V
1.2 V to 3.6 V
3.6 V
I
I
V = V
or GND,
or GND,
I
I
= 0
= 0
CCB
I
CCI
O
3.6 V
0 V
) I
V = V
1.2 V to 3.6 V
1.2 V to 3.6 V
µA
CCA
CCB
I
CCI
O
Control
inputs
C
C
V = 3.3 V or GND
3.3 V
3.3 V
3.3 V
3.3 V
2.5
6
pF
i
I
A or B
ports
V
O
= 3.3 V or GND
pF
io
NOTES: 9.
10.
V
is the V
associated with the output port.
associated with the input port.
CC
CCO
is the V
CC
V
CCI
switching characteristics over recommended operating free-air temperature range,
= 1.2 V (see Figure 11)
V
CCA
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V = 3.3 V
CCB
FROM
(INPUT)
TO
(OUTPUT)
CCB
TYP
3.3
CCB
TYP
2.7
CCB
TYP
2.4
CCB
TYP
2.3
PARAMETER
UNIT
ns
TYP
2.4
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PHZ
PLZ
PZH
A
B
A
A
B
A
B
3.3
3.3
3.3
5.1
5.1
5.3
5.3
8.5
8.5
8.3
8.3
2.7
3.1
3.1
5.2
5.2
4.3
4.3
6.9
6.9
7.8
7.8
2.4
2.9
2.9
5.3
5.3
4
2.3
2.8
2.8
5.2
5.2
3.3
3.3
5.5
5.5
7.5
7.5
2.4
2.7
2.7
3.7
3.7
3.7
3.7
6.1
6.1
5.9
5.9
B
ns
ns
DIR
DIR
DIR
DIR
ns
4
†
†
6.4
6.4
7.7
7.7
ns
†
PZL
PZH
ns
†
PZL
†
The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ
ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢐꢋ ꢉ ꢑꢒꢄ ꢍꢏꢀ ꢒꢓꢓꢍꢔ ꢐꢒꢀ ꢉ ꢕꢄꢁꢀ ꢆꢎ ꢋ ꢅꢎ ꢕ
ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range,
= 1.5 V 0.1 V (see Figure 11)
V
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
V
= 1.2 V
CCB
TYP
2.9
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.7
0.7
0.6
0.6
1.6
1.6
1.8
1.8
MAX
5.6
MIN
0.6
0.6
0.4
0.4
1.5
1.5
1.6
1.6
MAX
5.2
5.2
5.3
5.3
6.8
6.8
7.1
7.1
12.4
12.4
12
MIN
0.5
0.5
0.3
0.3
0.3
0.3
1.1
1.1
MAX
4.2
4.2
4.9
4.9
6.9
6.9
4.7
4.7
9.6
9.6
11.1
11.1
MIN
0.5
0.5
0.3
0.3
0.9
0.9
1.4
1.4
MAX
3.8
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PHZ
PLZ
PZH
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
2.9
2.6
2.6
3.8
3.8
5.1
5.1
7.7
7.7
6.7
6.7
5.6
3.8
5.5
4.8
B
5.5
4.8
6.7
6.9
DIR
DIR
DIR
DIR
6.7
6.9
8.1
4.5
8.1
4.5
†
†
13.6
13.6
12.3
12.3
9.3
†
9.3
PZL
10.7
10.7
PZH
†
12
PZL
†
The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
switching characteristics over recommended operating free-air temperature range,
= 1.8 V 0.15 V (see Figure 11)
V
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
V
= 1.2 V
CCB
TYP
2.8
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.6
0.6
0.5
0.5
1.6
1.6
1.8
1.89
MAX
5.3
MIN
0.5
0.5
0.4
0.4
1.6
1.6
1.4
1.4
MAX
5
MIN
0.4
0.4
0.3
0.3
1.6
1.6
1
MAX
3.9
3.9
4.6
4.6
5.9
5.9
4.4
4.4
9
MIN
0.4
0.4
0.2
0.2
0.5
0.5
1.4
1.4
MAX
3.4
3.4
4.4
4.4
6
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PHZ
PLZ
PZH
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
2.8
2.3
2.3
3.8
3.8
5
5.3
5
5.2
5
B
5.2
5
5.9
5.9
5.9
6.8
6.8
11.8
11.8
10.9
10.9
DIR
DIR
DIR
DIR
5.9
6
7.7
4.3
4.3
8.7
8.7
9.4
9.4
5
7.7
1
†
†
7.3
7.3
6.5
6.5
12.9
12.9
11.2
11.2
†
9
PZL
9.8
9.8
PZH
†
PZL
†
The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖꢋ ꢉ ꢇ ꢆ ꢗꢁ ꢘꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅ ꢗꢍꢉꢄꢌ ꢎ ꢉꢕ ꢄꢁ ꢀꢍ ꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓꢒꢉ ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range,
= 2.5 V 0.2 V (see Figure 11)
V
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
V
= 1.2 V
CCB
TYP
2.6
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.5
0.5
0.4
0.4
0.3
0.3
2
MAX
4.9
4.9
4.2
4.2
3.8
3.8
7.6
7.6
11.8
11.8
8.6
8.6
MIN
0.4
0.4
0.3
0.3
0.8
0.8
1.5
1.5
MAX
4.6
MIN
0.3
0.3
0.2
0.2
0.4
0.4
0.6
0.6
MAX
3.4
3.4
3.4
3.4
3.8
3.8
4.1
4.1
7.5
7.5
7
MIN
0.3
0.3
0.2
0.2
0.5
0.5
1
MAX
3
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PHZ
PLZ
PZH
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
2.6
2.2
2.2
2.8
2.8
4.9
4.9
7.1
7.1
5.4
5.4
4.6
3
3.8
3.3
3.3
3.8
3.8
4
B
3.8
3.8
DIR
DIR
DIR
DIR
3.8
6.5
2
6.5
1
4
†
†
10.3
10.3
8.1
7.3
7.3
6.6
6.6
†
PZL
PZH
†
8.1
7
PZL
†
The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (see Figure 11)
V
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
V
= 1.2 V
CCB
TYP
2.6
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
0.4
0.4
0.4
0.4
1.3
1.3
0.7
0.7
MAX
4.7
4.7
3.8
3.8
4.3
4.3
7.4
7.4
11.2
11.2
8.9
8.9
MIN
0.3
0.3
0.3
0.3
1.3
1.3
0.6
0.6
MAX
4.4
4.4
3.4
3.4
4.3
4.3
6.5
6.5
9.9
9.9
8.5
8.5
MIN
0.2
0.2
0.2
0.2
1.3
1.3
0.7
0.7
MAX
3.3
3.3
3
MIN
0.2
0.2
0.1
0.1
1.3
1.3
1.5
1.5
MAX
2.8
2.8
2.8
2.8
4.3
4.3
3.9
3.9
6.7
6.7
6.8
6.8
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PHZ
PLZ
PHZ
PLZ
PZH
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
2.6
2.2
2.2
3.1
3.1
4
B
3
4.3
4.3
4
DIR
DIR
DIR
DIR
4
4
†
†
6.2
6.2
5.7
5.7
7
†
7
PZL
7.2
7.2
PZH
†
PZL
†
The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ
ꢀ
ꢋ
ꢉ
ꢁ
ꢄ
ꢌ
ꢌ
ꢍ
ꢎ
ꢎ
ꢏ
ꢐ
ꢋ
ꢉ
ꢑ
ꢒ
ꢄ
ꢍ
ꢏ
ꢀ
ꢒ
ꢓ
ꢓ
ꢍ
ꢔ
ꢐ
ꢒ
ꢀ
ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
ꢉ
ꢕ
ꢄ
ꢁ
ꢀ
ꢆ
ꢎ
ꢋ
ꢅ
ꢎ
ꢕ
ꢖ
ꢋ
ꢉ
ꢇ
ꢆ
ꢗ
ꢁ
ꢘ
ꢋ
ꢌꢒ
ꢕ
ꢄ
ꢐ
ꢍ
ꢎ
ꢅ
ꢗ
ꢍ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
operating characteristics, T = 25°C
A
V
=
V
=
V
=
V
=
V
=
CCA
CCA
CCA
CCA
CCA
TEST
CONDITIONS
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
PARAMETER
CCB
CCB
CCB
CCB
CCB
UNIT
TYP
TYP
TYP
TYP
TYP
A-port input,
B-port output
3
14
14
3
3
14
14
3
3
14
14
3
3
15
15
3
4
16
16
4
C
= 0 pF,
L
†
C
C
f = 10 MHz,
t = t = 1 ns
r
pF
pdA
B-port input,
A-port output
f
A-port input,
B-port output
C
= 0 pF,
L
†
pF
f = 10 MHz,
t = t = 1 ns
pdB
B-port input,
A-port output
r
f
†
Power-dissipation capacitance per transceiver
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖꢋ ꢉ ꢇ ꢆ ꢗꢁ ꢘꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅ ꢗꢍꢉꢄꢌ ꢎ ꢉꢕ ꢄꢁ ꢀꢍ ꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓꢒꢉ ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up V
.
CCA
3. V
can be ramped up along with or after V
.
CCB
CCA
typical total static power consumption (I
+ I
)
CCA
CCB
Table 1
V
CCA
V
UNIT
CCB
0 V
0
1.2 V
<0.5
<1
1.5 V
<0.5
<1
1.8 V
<0.5
<1
2.5 V
<0.5
<1
3.3 V
<0.5
1
0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
<0.5
<0.5
<0.5
<0.5
<0.5
<1
<1
<1
<1
1
µA
<1
<1
<1
<1
<1
1
<1
<1
<1
<1
1
<1
<1
<1
<1
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ
ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢐꢋ ꢉ ꢑꢒꢄ ꢍꢏꢀ ꢒꢓꢓꢍꢔ ꢐꢒꢀ ꢉ ꢕꢄꢁꢀ ꢆꢎ ꢋ ꢅꢎ ꢕ
ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
T = 25°C, V
= 1.2 V
A
CCA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
V
V
V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
V
V
= 2.5 V
= 3.3 V
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
− pF
C
− pF
L
L
Figure 1
Figure 2
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
T = 25°C, V
= 1.5 V
A
CCA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
V
CCB
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
− pF
C
− pF
L
L
Figure 3
Figure 4
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖꢋ ꢉ ꢇ ꢆ ꢗꢁ ꢘꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅ ꢗꢍꢉꢄꢌ ꢎ ꢉꢕ ꢄꢁ ꢀꢍ ꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓꢒꢉ ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
T = 25°C, V
= 1.8 V
A
CCA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
CCB
CCB
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
V
CCB
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
− pF
C
− pF
L
L
Figure 6
Figure 5
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
T = 25°C, V
= 2.5 V
A
CCA
6
6
5
4
3
2
1
0
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
V
V
V
V
5
4
3
2
1
0
V
V
= 2.5 V
= 3.3 V
CCB
CCB
V
V
= 2.5 V
= 3.3 V
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
− pF
C
− pF
L
L
Figure 7
Figure 8
12
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ
ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢐꢋ ꢉ ꢑꢒꢄ ꢍꢏꢀ ꢒꢓꢓꢍꢔ ꢐꢒꢀ ꢉ ꢕꢄꢁꢀ ꢆꢎ ꢋ ꢅꢎ ꢕ
ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
T = 25°C, V
= 3.3 V
A
CCA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
V
CCB
CCB
CCB
CCB
V
V
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
− pF
C
− pF
L
L
Figure 9
Figure 10
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖ
ꢋ
ꢉ
ꢇ
ꢆ
ꢗ
ꢁ
ꢘꢋ
ꢌ
ꢒ
ꢕ
ꢄ
ꢐ
ꢍ
ꢎ
ꢅ
ꢗ
ꢍ
ꢉ
ꢄ
ꢌ
ꢎ
ꢉ
ꢕ
ꢄ
ꢁ
ꢀ
ꢍ
ꢄꢉ
ꢋ
ꢗ
ꢁ
ꢄ
ꢁ
ꢑ
ꢙ
ꢏ
ꢀ
ꢉ
ꢄ
ꢉ
ꢎ
ꢗ
ꢒ
ꢉ
ꢓ
ꢒ
ꢉ
ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
Open
GND
t
Open
L
pd
/t
From Output
Under Test
t
2 × V
CCO
GND
PLZ PZL
/t
PHZ PZH
t
C
L
R
L
(see Note A)
t
LOAD CIRCUIT
w
V
CCI
V /2
CCI
V /2
CCI
Input
V
TP
C
R
V
CCO
L
L
0 V
1.2 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
15 pF
15 pF
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
0.15 V
0.15 V
0.3 V
V
CCA
Output
Control
(low-level
enabling)
V
CCA
/2
V
CCA
/2
0 V
t
t
PLZ
PZL
V
V
CCO
Output
Waveform 1
V
CCI
V
CCO
/2
/2
Input
V /2
CCI
V /2
CCI
V
OL
+ V
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V
CCO
/2
V
/2
CCO
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns,
O
dv/dt ≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
dis
are the same as t
are the same as t .
en
and t
PHL
is the V
pd
associated with the input port.
associated with the output port.
CC
CCI
CC
is the V
CCO
Figure 11. Load Circuit and Voltage Waveforms
14
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃꢊ
ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢐꢋ ꢉ ꢑꢒꢄ ꢍꢏꢀ ꢒꢓꢓꢍꢔ ꢐꢒꢀ ꢉ ꢕꢄꢁꢀ ꢆꢎ ꢋ ꢅꢎ ꢕ
ꢖ ꢋ ꢉꢇ ꢆꢗ ꢁꢘ ꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅꢗ ꢍꢉꢄꢌ ꢎ ꢉ ꢕꢄꢁꢀ ꢍꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓ ꢒꢉꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
APPLICATION INFORMATION
Figure 12 shows an example of the SN74AVCH1T45 being used in a unidirectional logic level-shifting application.
V
CC1
V
CC1
V
CC2
V
CC2
1
2
3
6
5
4
SYSTEM-1
SYSTEM-2
PIN
NAME
FUNCTION
DESCRIPTION
1
V
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
Device GND
V
CCA
CC1
2
3
4
5
6
GND
A
GND
OUT
IN
Output level depends on V
CC1
voltage.
B
Input threshold value depends on V voltage.
CC2
DIR
GND (low level) determines B-port to A-port direction.
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
DIR
V
CCB
V
CC2
Figure 12. Unidirectional Logic Level-Shifting Application
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ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢐꢋ ꢉ ꢑ ꢒꢄ ꢍꢏꢀ ꢒꢓ ꢓꢍꢔ ꢐꢒ ꢀ ꢉꢕ ꢄꢁ ꢀꢆꢎ ꢋꢅꢎ ꢕ
ꢖꢋ ꢉ ꢇ ꢆ ꢗꢁ ꢘꢋ ꢌꢒ ꢕ ꢄꢐꢍ ꢎ ꢅ ꢗꢍꢉꢄꢌ ꢎ ꢉꢕ ꢄꢁ ꢀꢍ ꢄꢉ ꢋꢗ ꢁ ꢄꢁꢑ ꢙ ꢏꢀꢉꢄꢉ ꢎ ꢗ ꢒꢉ ꢓꢒꢉ ꢀ
SCES598C – JULY 2004 – REVISED OCTOBER 2004
APPLICATION INFORMATION
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
V
CC1
V
CC1
V
CC2
V
CC2
I/O-1
I/O-2
1
2
3
6
5
4
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2
to SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
SYSTEM-1 data to SYSTEM-2
Out
In
SYSTEM-2 is getting ready to send data to
SYSTEM-1. I/O-1 and I/O-2 are disabled.
The bus-line state depends on bus hold.
2
H
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
3
4
L
L
Hi-Z
Out
Hi-Z
In
SYSTEM-2 data to SYSTEM-1
Figure 13. Bidirectional Logic Level-Shifting Application
enable times
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
t
t
t
t
(DIR to A) = t
(DIR to B) + t
(DIR to B) + t
(DIR to A) + t
(DIR to A) + t
(B to A)
(B to A)
(A to B)
(A to B)
PZH
PZL
PZH
PZL
PLZ
PLH
PHL
PLH
PHL
(DIR to A) = t
(DIR to B) = t
PHZ
PLZ
PHZ
(DIR to B) = t
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After
the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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