SN74AVCH245DGVR [TI]
AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, PLASTIC, TVSOP-20;
| 型号： | SN74AVCH245DGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, PLASTIC, TVSOP-20 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总11页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
D
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
I
Supports Partial-Power-Down Mode
off
Operation
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V V
CC
D
Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I and I of
OH
OL
±24 mA at 2.5-V V
CC
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16
– Output Current – mA
0
17
34
51
68
85 102 119 136 153 170
0
I
– Output Current – mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This octal bus transceiver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to 3.6-V
CC
V
operation.
CC
The SN74AVCH245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3–33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The SN74AVCH245 is characterized for operation from –40°C to 85°C.
terminal assignments
DGV, DW, OR PW PACKAGE
(TOP VIEW)
DIR
A1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
GND
FUNCTION TABLE
(each transceiver)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
3–34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
†
logic symbol
19
1
G3
OE
DIR
3 EN1 [BA]
3 EN2 [AB]
2
18
A1
1
B1
2
3
4
5
6
7
8
9
17
B2
16
B3
15
B4
A2
A3
A4
A5
A6
A7
A8
14
B5
13
B6
12
B7
11
B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
2
DIR
19
OE
A1
18
B1
To Seven Other Channels
3–35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
O
Voltage range applied to any input/output when the output
is in the high or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
3–36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN
1.4
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
1.2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 1.2 V
0.65 × V
CC
V
High-level input voltage
0.65 × V
V
V
CC
1.7
2
GND
0.35 × V
0.35 × V
0.7
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
–2
–4
–8
†
I
Static high-level output current
mA
mA
OHS
OLS
–12
2
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
4
†
I
Static low-level output current
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.4 V to 3.6 V
ns/V
T
–40
85
°C
A
†
DynamicdrivecapabilityisequivalenttostandardoutputswithI
OH
andI of±24mAat2.5-VV .SeeFigure1forV vsI andV vs I
OL CC OL OL OH OH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= –100 µA
MIN TYP
V –0.2
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
1.4 V to 3.6 V
1.4 V
1.65 V
2.3 V
3 V
OHS
OHS
OHS
OHS
OHS
OLS
OLS
OLS
OLS
OLS
= –2 mA,
= –4 mA,
= –8 mA,
= –12 mA,
= 100 µA
= 2 mA,
V
V
V
V
= 0.91 V
= 1.07 V
= 1.7 V
= 2 V
1.05
1.2
IH
IH
IH
IH
V
V
OH
OL
1.75
2.3
1.4 V to 3.6 V
1.4 V
1.65 V
2.3 V
3 V
0.2
0.4
V
IL
V
IL
V
IL
V
IL
= 0.49 V
= 0.57 V
= 0.7 V
= 0.8 V
V
= 4 mA,
0.45
0.55
0.7
V
= 8 mA,
= 12 mA,
I
I
Control inputs
V = V or GND
CC
3.6 V
1.65 V
2.3 V
3 V
±2.5
µA
µA
I
I
V = 0.57 V
I
25
45
‡
V = 0.7 V
I
BHL
V = 0.8 V
I
75
V = 1.07 V
1.65 V
2.3 V
3 V
–25
–45
–75
200
300
500
I
§
I
I
I
V = 1.7 V
I
µA
µA
µA
BHH
V = 2 V
I
1.95 V
2.7 V
3.6 V
1.95 V
2.7 V
3.6 V
0
¶
#
V = 0 to V
BHLO
I
CC
CC
–200
–300
–500
V = 0 to V
I
BHHO
I
I
I
V or V = 3.6 V
±10
±12.5
40
µA
µA
µA
off
I
O
||
V
= V or GND
CC
3.6 V
3.6 V
2.5 V
3.3 V
2.5 V
3.3 V
OZ
O
V = V
I
or GND,
I
O
= 0
CC
CC
C
C
Control inputs
A or B ports
V = V
I
or GND
pF
pF
i
CC
V
O
= V
or GND
CC
io
†
‡
Typical values are measured at T = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
A
should be measured after lowering V to GND and
IN
IL
BHL
§
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
includes the input leakage current.
For I/O ports, the parameter I
OZ
3–38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
dis
OE
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
CC
= 2.5 V
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
3–39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 1.2 V AND 1.5 V ± 0.1 V
CC
2 × V
CC
Open
S1
2 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 15 pF
t
2 × V
CC
GND
L
PLZ PZL
2 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ 0.1 V
OL
CC
V
0 V
OL
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
– 0.1 V
V
CC
/2
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
3–40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
3–41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 4. Load Circuit and Voltage Waveforms
3–42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
2 × V
CC
TEST
S1
S1
500 Ω
Open
From Output
Under Test
t
Open
pd
GND
t
/t
2 × V
CC
GND
PLZ PZL
/t
t
C
= 30 pF
PHZ PZH
L
500 Ω
(see Note A)
t
LOAD CIRCUIT
w
V
CC
Input
V
CC
/2
V
CC
/2
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
V
CC
/2
V
CC
/2
V
CC
Output
0 V
Control
(low-level
enabling)
V
CC
/2
V
CC
/2
t
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
OL
+ 0.3 V
V
CC
/2
V
/2
CC
S1 at 2 × V
(see Note B)
CC
V
OL
0 V
t
t
t
t
PHZ
PLH
PHL
/2
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
– 0.3 V
OH
V
CC
/2
V
CC
/2
V
Output
CC
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 5. Load Circuit and Voltage Waveforms
3–43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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