SN74AUC2G86_09 [TI]
DUAL 2-INPUT EXCLUSIVE-OR GATE; 双2输入异或门
| 型号： | SN74AUC2G86_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 2-INPUT EXCLUSIVE-OR GATE |
| 文件： | 总13页 (文件大小：544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES479B–AUGUST 2003–REVISED JANUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
•
•
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
•
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Protection Exceeds JESD 22
•
Ioff Supports Partial-Power-Down Mode
Operation
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
Sub-1-V Operable
1000-V Charged-Device Model (C101)
Max tpd of 1.7 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
2A
4 5
GND
1A
1B
VCC
1Y
2B
2A
1
2
3
4
8
7
6
5
1
2
8
7
VCC
1Y
1A
1B
3 6
2B
2Y
1B
1A
2
7
1Y
2Y
1 8
VCC
GND
3
4
6
5
2B
2A
2Y
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC2G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74AUC2G86YZPR
_ _ _UH_
–40°C to 85°C
Reel of 3000
Reel of 3000
SN74AUC2G86DCTR
SN74AUC2G86DCUR
U86_ _ _
U86_
VSSOP – DCU
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES479B–AUGUST 2003–REVISED JANUARY 2007
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
L
B
L
L
H
H
L
L
H
L
H
H
H
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74AUC2G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC Supply voltage range
3.6
3.6
VI
Input voltage range(2)
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)
3.6
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±20
±100
220
DCT package
DCU package
YZP package
θJA
Package thermal impedance(3)
227
°C/W
°C
102
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES479B–AUGUST 2003–REVISED JANUARY 2007
Recommended Operating Conditions(1)
MIN
0.8
MAX
UNIT
VCC
Supply voltage
2.7
V
VCC = 0.8 V
VCC
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
0.65 × VCC
1.7
V
V
0
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.35 × VCC
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
Low-level output current
mA
mA
IOL
5
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
TA
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCC
0.8 V to 2.7 V
0.8 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
0.55
1.1 V
0.8
1
VOH
V
1.4 V
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
V
VOL
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
2.3 V
0.45
0.6
IOL = 9 mA
II
A or B inputs
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
0 to 2.7 V
0
±5
±10
10
µA
µA
µA
pF
Ioff
ICC
Ci
IO = 0
0.8 V to 2.7 V
2.5 V
2.5
(1) All typical values are at TA = 25°C.
3
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SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES479B–AUGUST 2003–REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.2 V VCC = 1.5 V
± 0.1 V ± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX MIN MAX MIN TYP MAX MIN MAX
0.8 3.8 0.5 2.6 0.4 1.7 0.3 1.3 ns
tpd
A or B
Y
5.3
1
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
MIN
MAX
tpd
A or B
Y
0.8
1.5
2.6
0.7
2
ns
Operating Characteristics
TA = 25°C
VCC = 0.8 V
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Power dissipation
capacitance
Cpd
f = 10 MHz
15
15
16
19
27
pF
4
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SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES479B–AUGUST 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
2 × VCC
Open
GND
S1
RL
From Output
Under Test
CL
V
RL
VCC
CL
(see Note A)
D
RL
0.8 V
2 kW
2 kW
2 kW
2 kW
2 kW
1 kW
500 W
0.1 V
0.1 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
LOAD CIRCUIT
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0 V
tW
tsu
th
VCC
VCC
0 V
Input
VCC/2
VCC/2
Data Input
VCC/2
VCC/2
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
0 V
VCC
0 V
Output
Control
VCC/2
VCC/2
Input
VCC/2
VCC/2
tPZL
tPLZ
tPLH
tPHL
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VOL
VCC
VOL
VCC/2
VCC/2
Output
Output
VOL + V
D
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VCC/2
VCC/2
VCC/2
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W,
slew rate ³ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
5
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74AUC2G86DCTR
SN74AUC2G86DCTRE4
SN74AUC2G86DCTRG4
SN74AUC2G86DCUR
SN74AUC2G86DCURE4
SN74AUC2G86DCURG4
SN74AUC2G86YZPR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DCT
8
8
8
8
8
8
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SM8
SM8
DCT
DCT
DCU
DCU
DCU
YZP
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
US8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
US8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
US8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AUC2G86DCUR
SN74AUC2G86YZPR
US8
DCU
YZP
8
8
3000
3000
180.0
180.0
9.2
8.4
2.25
1.02
3.35
2.02
1.05
0.63
4.0
4.0
8.0
8.0
Q3
Q1
DSBGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AUC2G86DCUR
SN74AUC2G86YZPR
US8
DCU
YZP
8
8
3000
3000
202.0
220.0
201.0
220.0
28.0
34.0
DSBGA
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
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